EE 434 ecture 34 ogic Design
Review from last time: Transfer characteristics of the static CMOS inverter (Neglect λ effects) Case 5 M cutoff, M triode V -V > V -V -V Tp V < V Tn V V V Tp
Transfer characteristics of the static CMOS inverter (Neglect λ effects)
Review from last time: Transfer characteristics of the static CMOS inverter (Neglect λ effects)
Review from last time: Inverter Transfer Characteristics of Inverter Pair V V
Review from last time: Static CMOS ogic Family Pull-up Network PUN Pull-down Network PDN Observe PUN is p-channel, PDN is n-channel
Review from last time: Static CMOS ogic Family V M M 4 M 3 M 4 A M 3 Y V V Y A M M B M M B M V M M 3 M 4 Y V V A M M B M n-channel PDN and p-channel PUN
Static CMOS ogic Family V M 3 M 4 M Y V V A M M B M A B Y A B Y Any number of inputs can be added to NAND or NOR Gates NAND and NOR ogic Families are Complete Can now build ANY combinational logic function!
Review from last time: General ogic Family p-channel PUN n-channel PDN Arbitrary PUN and PDN
Review from last time: Other CMOS ogic Families
Review from last time: Static Power Dissipation in Static CMOS Family V M When V is ow, I D =0 When V is High, I D =0 V V Thus, P STATIC =0 M This is a key property of the static CMOS ogic Family and is the major reason Static CMOS ogic is so dominant It can be shown that this zero static power dissipation property can be preserved if the PUN is comprised of n-channel devices, the PDN is comprised of n-channel devices and they are never both driven into the conducting states at the same time
Review from last time: Static Power Dissipation in Ratio ogic V Families Example: Assume V =5V V T =V, μc OX =0-4 A/V, W / = and M sized so that V =V Tn M P =(5V)(0.5mA)=.5mW V M V If a circuit has 00,000 gates and half of them are in the V =V state, the static power dissipation will be Enhancement oad NMOS 5 P STATIC = 0. 5mW = 6.5W This power dissipation is way too high and would be even larger in circuits with 00 million or more gates the level of integration common in SoC circuits today
Review from last time: Propagation Delay in Static CMOS Family V V S R SWp M C GSp V G V V V G G D D V M C GSn R SWn V G S Switch-level model of Static CMOS inverter (neglecting diffusion parasitics)
Review from last time: Propagation Delay in Static CMOS Family V S RSWp CGSp V G VG D V V G RSWn D CGSn VG PU S M V G V V M C PD V G Switch-level model of Static CMOS inverter (neglecting diffusion parasitics)
Propagation Delay in Static CMOS Family Since operating in triode through most of transition: I D μcoxw V R R PD = μ n C OX μcoxw ID = V PU = μpcox GS GS V W W T ( V V ) V V V V DS Tn μc V DS OX T DS ( V + V ) Tp DS W ( W W ) C = C + OX μcoxw ( V GS V T ) V DS ( V GS V T ) V DS
Propagation Delay in Static CMOS Family R R PD PU = = μ μ n p C C OX OX W W ( V V ) Tn ( V + V ) Tp OX ( W W ) C = C + If u n C OX =00μAV -, C OX =4 ffμ -, V Tn =V /5, V TP =-V /5, μ n /μ p =3, =W = M, =W = M, M =0.5μ and V =5V R PD = = Ω 0 0.8V.5K -4 5 C = 4 0 M = ff R PU = = 7.5KΩ -4 0 0.8V 3
Propagation Delay in Static CMOS Family R R PD PU = = μ μ n p C C OX OX W W ( V V ) Tn ( V + V ) Tp OX ( W W ) C = C + If u n C OX =00μAV -, C OX =4 ffμ -, V Tn =V /5, V TP =-V /5, μ n /μ p =3, =W = M, =W = M, M =0.5μ and V =5V R PD = = Ω 0 0.8V.5K -4 5 C = 4 0 M = ff R PU = = 7.5KΩ -4 0 0.8V 3
Propagation Delay in Static CMOS Family Consider: For H output transition, C charged to V Ideally:
Propagation Delay in Static CMOS Family For H output transition, C charged to V Actually: What is the transition time t H?
Propagation Delay in Static CMOS Family
Propagation Delay in Static CMOS Family For H output transition, C charged to V PD C V G V V e - V t t=0 t V t t R τ PD () t = F + ( I F) e = 0 + ( V 0) e C V e t RPDC = V e PD t = R C
Propagation Delay in Static CMOS Family For H output transition, C charged to V PD C V G V V e - V t t=0 t t R H PD t R H C PU C
Propagation Delay in Static CMOS Family
Propagation Delay in Static CMOS Family
Device Sizing M V V M