MC4049B, MC4050B Hex Buffer The MC4049B Hex Inverter/Buffer and MC4050B Noninverting Hex Buffer are constructed with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure. These complementary MOS devices find primary use where low power dissipation and/or high noise immunity is desired. These devices provide logic level conversion using only one supply voltage,. The inputsignal high level (V IH ) can exceed the supply voltage for logic level conversions. Two TTL/DTL loads can be driven when the devices are used as a CMOStoTTL/DTL converter ( = 5.0 V, V OL 0.4 V, I OL 3.2 ma). Note that pins 3 and 6 are not connected internally on these devices; consequently connections to these terminals will not affect circuit operation. Features High Source and Sink Currents HightoLow Level Converter Supply Voltage Range = 3.0 V to V V IN can exceed Meets JEDEC B Specifications Improved ESD Protection On All Inputs PbFree Packages are Available* MAXIMUM RATINGS (Voltages Referenced to ) Symbol Parameter Value Unit DC Supply Voltage Range 0.5 to +.0 V V in Input Voltage Range (DC or Transient) 0.5 to +.0 V V out Output Voltage Range (DC or Transient) 0.5 to + 0.5 V I in Input Current (DC or Transient) per Pin ±0 ma I out Output Current (DC or Transient) per Pin ±45 ma P D Power Dissipation, per Package (Note ) (Plastic) (SOIC) 25 740 mw T A Ambient Temperature Range 55 to +25 C T stg Storage Temperature Range 65 to +50 C T L Lead Temperature (Second Soldering) 260 C. Temperature Derating: See Figure 3. This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the pin only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum rated voltages to this highimpedance circuit. For proper operation, the ranges V in V and V out are recommended. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. xx A WL, L YY, Y WW, W PDIP6 P SUFFIX CASE 64 SOIC6 D SUFFIX CASE 75B TSSOP6 DT SUFFIX CASE 94F SOEIAJ6 F SUFFIX CASE 966 MARKING DIAGRAMS MC40xxBCP AWLYYWW 40xxB AWLYWW 4 0xxB ALYW MC40xxB AWLYWW = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 6 6 6 6 *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 February, 2005 Rev. 5 Publication Order Number: MC4049B/D
MC4049B, MC4050B MC4049B LOGIC DIAGRAM MC4050B PIN ASSIGNMENT 3 2 3 2 6 NC 5 4 5 4 OUT A IN A 2 3 5 4 OUT F IN F 7 6 7 6 OUT B IN B 4 5 3 2 NC OUT E 9 0 9 0 OUT C 6 IN E 2 2 IN C 7 0 9 OUT D IN D 4 5 NC = PIN 3, 6 = PIN = PIN 4 5 NC = PIN 3, 6 = PIN = PIN ORDERING INFORMATION Device Package Shipping MC4049BCP PDIP6 500 Units / Rail MC4049BCPG PDIP6 500 Units / Rail (PbFree) MC4049BD SOIC6 4 Units / Rail MC4049BDG SOIC6 (PbFree) 4 Units / Rail MC4049BDR2 SOIC6 2500 Units / Tape & Reel MC4049BDR2G SOIC6 (PbFree) 2500 Units / Tape & Reel MC4049BFEL SOEIAJ6 2000 Units / Tape & Reel MC4050BCP PDIP6 500 Units / Rail MC4050BCPG PDIP6 (PbFree) 500 Units / Rail MC4050BD SOIC6 4 Units / Rail MC4050BDR2 SOIC6 2500 Units / Tape & Reel MC4050BDR2G SOIC6 (PbFree) 2500 Units / Tape & Reel MC4050BDT TSSOP6* 96 Units / Rail MC4050BDTR2 TSSOP6* 2500 Units / Tape & Reel MC4050BFEL SOEIAJ6 2000 Units / Tape & Reel MC4050BFELG SOEIAJ6 (PbFree) 2000 Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD0/D. *This package is inherently PbFree. 2
MC4049B, MC4050B ELECTRICAL CHARACTERISTICS (Voltages Referenced to ) Î 55 C + 25 C ÎÎ + 25 C Î Characteristic Î Symbol Vdc Min MaxÎ Min TypÎ Max Min Max Unit (Note 2) Output Voltage 0 Level V Î V in = Î OL 5.0 0.05 0 0.05 0.05 Vdc ÎÎ 0 0 0.05 5 0.05Î 0 Î 0.05 0.05 Î Level Î V OH 5.0 4.95 Î 4.95 5.0Î 4.95 Vdc V Î in = 0 0 9.95 9.95 0 9.95 5 4.95 4.95 5 4.95 Î Input Voltage 0 Level V IL ÎÎ Vdc Î (V O = 4.5 Vdc) 5.0.5Î 2.25Î.5.5 (V Î O = 9.0 Vdc) 0 3.0 4.50 3.0 3.0 (V O = 3.5 Vdc) 5 4.0Î 6.75Î 4.0 4.0 Î Level V IH ÎÎ Vdc Î (V O = 0.5 Vdc) 5.0 3.5 Î 3.5 2.75Î 3.5 (V Î O =.0 Vdc) 0 7.0 7.0 5.50 7.0 (V O =.5 Vdc) 5 Î.25Î Î Output Drive Current Î I OH ÎÎ madc Î (V OH = 2.5 Vdc) Source 5.0.6 Î.25 2.5Î.0 (V Î OH = 9.5 Vdc) 0.6.30 2.6.0 (V OH = 3.5 Vdc) 5 4.7 Î 3.75 0Î 3.0 Î (V OL = 0.4 Vdc) Sink Î I OL 5.0 Î (V OL = 0.5 Vdc) 0 3.75 0 3.2 Î.0 6.0 2.6 6 Î 6.6 madc (V OL =.5 Vdc) 5 30 24 40 9 Input Current I in 5 ± 0. ±0.0000 ± 0. ±.0 Adc Input Capacitance (V in = 0) C in 0 20 pf Î Î Î ÎÎ Quiescent Current (Per Package) I Î DD 5.0.0 0.002.0 30 Adc 0 2.0Î 0.004Î 2.0 60 5 4.0 0.006 4.0 20 Î Total Supply Current (Notes 3 & 4) Î I T 5.0 ÎÎ I T = (. A/kHz) f + I DD (Dynamic plus Quiescent, 0 I T = (3.5 A/kHz) f + I DD Adc Î per package) 5 ÎÎ I T = (5.3 A/kHz) f + I DD (C Î L = 50 pf on all outputs, all buffers switching 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 3. The formulas given are for the typical characteristics only at + 25 C 4. To calculate total supply current at loads other than 50 pf: I T (C L ) = I T (50 pf) + (C L 50) Vfk Where: I T is in A (per Package), C L in pf, V = ( ) in volts, f in khz is input frequency and k = 0.002. 3
MC4049B, MC4050B AC SWITCHING CHARACTERISTICS (Note 5) (C L = 50 pf, T A = + 25 C) Characteristic ÎÎ Symbol Î Î Min Î Typ Î Max Unit Vdc (Note 6) Output Rise Time t t TLH = (0.7 ns/pf) C L ÎÎ TLH ns Î Î Î + 65 ns 5.0 00 60 t TLH = (0.25 ns/pf) C L + 37.5 ns ÎÎ 0 Î Î 50 Î 0 t TLH = (0.2 ns/pf) C L + 30 ns 5 40 60 Output Fall Time t t THL = (0.2 ns/pf) C L + 30 ns ÎÎ THL ns Î 5.0 Î Î 40 Î 60 t THL = (0.06 ns/pf) C L + 7 ns ÎÎ 0 Î Î 20 Î 40 t THL = (0.04 ns/pf) C L + 3 ns 5 5 30 Propagation Delay Time t t PLH = (0.33 ns/pf) C L + 63.5 ns ÎÎ PLH ns Î 5.0 Î Î 0 Î 40 t PLH = (0.9 ns/pf) C L + 30.5 ns ÎÎ 0 Î Î 40 Î 0 t PLH = (0.06 ns/pf) C L + 27 ns 5 30 60 Propagation Delay Time t t PHL = (0.2 ns/pf) C L + 30 ns ÎÎ PHL ns Î 5.0 Î Î 40 Î 0 t PHL = (0. ns/pf) C L + 5 ns ÎÎ 0 Î Î 20 Î 40 t PHL = (0.05 ns/pf) C L + 2.5 ns 5. The formulas given are for the typical characteristics only at 25 C. 6. Data labeled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 5 5 30 MC4049B MC4050B MC4049B MC4050B I OH I OL V OH V OL I OL V OL I OH V OH V DS = V OH = V OL 0 60 I OH, OUTPUT SOURCE CURRNT (madc) 0 20 30 40 V GS = 0 Vdc V GS = 5 Vdc V GS = 5.0 Vdc MAXIMUM CURRENT LEVEL I OL, OUTPUT SINK CURRENT (madc) 20 0 40 V GS = 5 Vdc V GS = 0 Vdc MAXIMUM CURRENT LEVEL V GS = 5.0 Vdc 50 0.0 6.0 4.0 2.0 0 V DS, DRAINTOSOURCE VOLTAGE (Vdc) Figure. Typical Output Source Characteristics 0 0 2.0 4.0 6.0.0 0 V DS, DRAINTOSOURCE VOLTAGE (Vdc) Figure 2. Typical Output Sink Characteristics 4
MC4049B, MC4050B P D, MAXIMUM POWER DISSIPATION (mw) PER PACKAGE 200 00 000 900 25 00 740 700 600 500 400 300 200 00 0 25 (P) PDIP (D) SOIC 50 75 00 25 T A, AMBIENT TEMPERATURE ( C) 50 75 75 mw (P) 20 mw (D) Figure 3. Ambient Temperature Power Derating 20 ns 20 ns INPUT 90% 50% 0% PULSE GENERATOR V in # V out t PHL OUTPUT MC4049B t PLH 90% 50% 0% t THL t PLH t TLH V OH V OL # Invert on MC4049B only C L OUTPUT MC4050B t PHL 90% 50% 0% t PHL V OH V OL t TLH t THL Figure 4. Switching Time Test Circuit and Waveforms 5
MC4049B, MC4050B PACKAGE DIMENSIONS PDIP6 P SUFFIX PLASTIC DIP PACKAGE CASE 640 ISSUE T 6 A 9 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 92. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. H G F D 6 PL S C K 0.25 (0.00) M T SEATING T PLANE A M J L M INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.740 0.770.0 9.55 B 0.250 0.270 6.35 6.5 C 0.45 0.75 3.69 4.44 D 0.05 0.02 0.39 0.53 F 0.040 0.70.02.77 G 0.00 BSC 2.54 BSC H 0.050 BSC.27 BSC J 0.00 0.05 0.2 0.3 K 0.0 0.30 2.0 3.30 L 0.295 0.305 7.50 7.74 M 0 0 0 0 S 0.020 0.040 0.5.0 SOIC6 D SUFFIX PLASTIC SOIC PACKAGE CASE 75B05 ISSUE J A 6 9 B P PL 0.25 (0.00) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 92. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G K C D 6 PL 0.25 (0.00) M T B S A S M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.0 0.00 0.36 0.393 B 3.0 4.00 0.50 0.57 C.35.75 0.054 0.06 D 0.35 0.49 0.04 0.09 F 0.40.25 0.06 0.049 G.27 BSC 0.050 BSC J 0.9 0.25 0.00 0.009 K 0.0 0.25 0.004 0.009 M 0 7 0 7 P 5.0 6.20 0.229 0.244 R 0.25 0.50 0.00 0.09 6
MC4049B, MC4050B PACKAGE DIMENSIONS TSSOP6 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 94F0 ISSUE A 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 C 6X K REF 0.0 (0.004) M T U S V S 6 9 A V G B U N H N J J F DETAIL E DETAIL E K K ÇÇÇ ÉÉ ÇÇÇ SECTION NN 0.25 (0.00) M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 92. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.0 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.0 0.93 0.200 B 4.30 4.50 0.69 0.77 C.20 0.047 D 0.05 0.5 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0. 0.2 0.007 0.0 J 0.09 0.20 0.004 0.00 J 0.09 0.6 0.004 0.006 K 0.9 0.30 0.007 0.02 K 0.9 0.25 0.007 0.00 L 6.40 BSC 0.252 BSC M 0 0 7
MC4049B, MC4050B PACKAGE DIMENSIONS SOEIAJ6 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 9660 ISSUE O e 6 9 Z b D A H E A 0.3 (0.005) M 0.0 (0.004) E VIEW P M L E Q L DETAIL P c NOTES: М. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 92. М 2. CONTROLLING DIMENSION: MILLIMETER. М 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. М 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. М 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.0 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.0). MILLIMETERS INCHES DIM MIN MAX MIN MAX A 2.05 0.0 A 0.05 0.20 0.002 0.00 b 0.35 0.50 0.04 0.020 c 0. 0.27 0.007 0.0 D 9.90 0.50 0.390 0.43 E 5.0 5.45 0.20 0.25 e.27 BSC 0.050 BSC H E 7.40.20 0.29 0.323 L 0.50 0.5 0.020 0.033 L E.0.50 0.043 0.059 M 0 0 0 0 Q 0.70 0.90 0.02 0.035 Z 0.7 0.03 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 632, Phoenix, Arizona 50232 USA Phone: 4029770 or 00344360 Toll Free USA/Canada Fax: 40297709 or 00344367 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 0022955 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 29 Kamimeguro, Meguroku, Tokyo, Japan 53005 Phone: 35773350 ON Semiconductor Website: Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MC4049B/D