Data Sheet, Rev..0, June 2007 BTM7700G TrilithIC Automotive Power
Table of Contents Table of Contents................................................................ 2 Overview....................................................................... 3 2 Pin Configuration................................................................ 4 2. Pin Assignment................................................................... 4 2.2 Terms.......................................................................... 6 3 Block Diagram................................................................... 7 4 Circuit Description............................................................... 8 4. Input Circuit...................................................................... 8 4.2 Output Stages.................................................................... 8 4.3 Short Circuit Protection............................................................. 8 4.4 Overtemperature Protection......................................................... 8 4.5 Undervoltage ockout.............................................................. 8 4.6 Status Flag...................................................................... 8 5 Electrical Characteristics......................................................... 0 5. Absolute Maximum Ratings........................................................ 0 5.2 Functional Range................................................................ 5.3 Thermal Resistance.............................................................. 5.4 Electrical Characteristics.......................................................... 2 6 Application Information.......................................................... 5 7 Package Outlines............................................................... 6 8 Revision History................................................................ 7 Data Sheet Rev..0, 2007-06-2
TrilithIC BTM7700G Overview Features Quad D-MOS switch driver Free configurable as bridge or quad-switch Optimized for DC motor management applications ow R DS ON High side: 0 mω typ. @ 25 C, 280 mω max. @ 50 C ow side: 80 mω typ. @ 25 C, 200 mω max. @ 50 C Peak current: typ. 9.5 A @ 25 C Very low quiescent current: typ. 5 µa @ 25 C Small outline, enhanced power PG-DSO-package Operates up to 40 V PWM frequencies up to khz oad and GND-short-circuit-protection Overtemperature shut down with hysteresis Undervoltage detection with hysteresis Status flag diagnosis Internal clamp diodes Isolated sources for external current sensing Green Product (RoHS compliant) AEC Qualified PG-DSO-28-22 Description The BTM7700G is part of the TrilithIC family containing three dies in one package: One double high-side switch and two low-side switches. The drains of these three vertical DMOS chips are mounted on separated lead frames. The sources are connected to individual pins, so the BTM7700G can be used in H-bridge- as well as in any other configuration. The double high-side switch is manufactured in SMART SIPMOS technology which combines low R DS ON vertical DMOS power stages with CMOS circuitry for control, protection and diagnosis. To achieve low R DS ON and fast switching performance, the low-side switches are manufactured in S-FET logic level technology. Type Package Marking BTM7700G PG-DSO-28-22 BTM7700G Data Sheet Rev..0, 2007-06-2
Description 2 Pin Configuration 2. Pin Assignment D 28 D I 2 27 S D N.C. 3 4 S-eadframe 26 S 25 D DHVS 5 24 DHVS GND 6 23 SH IH ST 7 8 HS-eadframe 22 SH 2 SH2 IH2 9 20 SH2 DHVS 0 9 DHVS N.C. D2 2 S-eadframe 8 D2 7 S2 I2 3 6 S2 D2 4 5 D2 Figure Pin Assignment BTM7700G (Top View) Data Sheet 2 Rev..0, 2007-06-2
Description Table Pin Definitions and Functions Pin No. Symbol Function, 3, 25, 28 D Drain of low-side switch, leadframe ) 2 I Analog input of low-side switch 4 N.C. not connected 5, 0, 9, 24 DHVS Drain of high-side switches and power supply voltage, leadframe 2 ) 6 GND Ground 7 IH Digital input of high-side switch 8 ST Status of high-side switches; open Drain output 9 IH2 Digital input of high-side switch2 N.C. not connected 2, 4, 5, 8 D2 Drain of low-side switch2, leadframe 3 ) 3 I2 Analog input of low-side switch2 6,7 S2 Source of low-side switch2 20,2 SH2 Source of high-side switch2 22,23 SH Source of high-side switch 26,27 S Source of low-side switch ) To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe. Pins written in bold type need power wiring. Data Sheet 3 Rev..0, 2007-06-2
Description 2.2 Terms V S =2V I S C S 470nF C 00µF I FH,2 DHVS I ST K 5,0,9,24 I ST ST 8 V DSH2 V DSH -V FH2 -V FH Diagnosis Biasing and Protection V ST V ST I IH IH 7 Gate Driver V STZ V IH I IH IH2 9 Gate Driver R O R O2 20,2 2,4,5,8 SH2 D2 I SH2 I D2 V IH2 GND 6 I D K 2 V UVON I GND 22,23 SH I SH V UVOFF I KC,3,25,28 D I D I D K I I I 2 V I I I2 I2 3 V I th V I2 26,27 6,7 V DS V DS2 V I th 2 S S2 -V F -V F2 I SCP I SCP 2 I S I S2 Figure 2 Terms BTM7700G Table 2 HS-Source-Current Named during Short Circuit Named during eakage-cond. I SH,2 I SCP H I D K Data Sheet 4 Rev..0, 2007-06-2
Description 3 Block Diagram DHVS 5,0,9,24 ST 8 Diagnosis Biasing and Protection IH IH2 7 9 Driver IN OUT 0 0 0 H 0 H H H R O R O2 20,2 2,4,5,8 SH2 D2 GND 6 22, 23 SH,3,25,28 D I 2 I2 3 26, 27 6, 7 S S2 Figure 3 Block Diagram BTM7700G Data Sheet 5 Rev..0, 2007-06-2
4 Circuit Description 4. Input Circuit The control inputs IH,2 consist of TT/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs are protected by ESD clamp-diodes. The inputs I and I2 are connected to the gates of the standard N-channel vertical power-mos-fets. 4.2 Output Stages The output stages consist of an low R DSON Power-MOS H-bridge. In H-bridge configuration, the D-MOS body diodes can be used for freewheeling when communicating inductive loads. If the high-side switches are used as single switches, positive and negative voltage spikes which occur when driving inductive loads are limited by integrated power clamp diodes. 4.3 Short Circuit Protection The outputs are protected against short circuit to ground and short circuit over load An internal OP-Amp controls the Drain-Source-Voltage by comparing the DS-Voltage-Drop with an internal reference voltage. Above this trip point the OP-Amp reduces the output current depending on the junction temperature and the drop voltage. 4.4 Overtemperature Protection The high-side switches also incorporate an over temperature protection circuit with hysteresis which switches off the output transistors and sets the status output to low. 4.5 Undervoltage ockout When V S reaches the switch-on voltage V UVON the IC becomes active with a hysteresis. The high-side output transistors are switched off if the supply voltage V S drops below the switch off value V UVOFF. 4.6 Status Flag The status flag output is an open drain output with zener-diode which requires a pull-up resistor, as shown in the application circuit in Figure 4 Application Example BTM7700G on Page 5. Various errors as listed in the table Diagnosis are reported by switching the open drain output ST to low. Data Sheet Rev..0, 2007-06-2
Table 3 Truth table and Diagnosis (valid only for the High-Side-Switches) Flag IH IH2 SH SH2 ST Remarks Inputs Outputs Normal operation; identical with functional truth table Overtemperature high-side switch 0 Overtemperature high-side switch2 Overtemperature both high-side switches 0 0 0 0 0 0 0 H H H H stand-by mode switch2 active switch active both switches active 0 detected 0 detected 0 0 detected detected Under voltage not detected Inputs: Outputs: Status: 0 = ogic OW Z = Output in tristate condition = No error = ogic HIGH = Output in sink condition 0 = Error = don t care H = Output in source condition = Voltage level undefined Data Sheet 2 Rev..0, 2007-06-2
5 Electrical Characteristics 5. Absolute Maximum Ratings Absolute Maximum Ratings ) 40 C < T j < 50 C Pos. Parameter Symbol imit Values Unit Remarks High-Side-Switches (Pins DHVS, IH,2 and SH,2) 5.. Supply voltage V S 0.3 42 V 5..2 Supply voltage for full short circuit V S(SCP) 28 V protection 5..3 HS-drain current 2) I S 7 3) A T A = 25 C; t P < 00 ms 5..4 HS-input current I IH 5 5 ma Pin IH and IH2 5..5 HS-input voltage V IH 0 6 V Pin IH and IH2 Status Output ST 5..6 Status pull up voltage V ST 0.3 5.4 V 5..7+ Status Output current I ST 5 5 ma Pin ST 5..8 ow-side-switches (Pins D,2, I,2 and S,2) 5..9 Drain-Source-Clamp voltage V DS 55 V V I = 0 V; I D ma T j = 25 C 5..0 S-drain current 2) I D 7 6 A T A = 25 C; t P < 00 ms 5.. 8 A T A = 25 C; t P < 0 ms 5..2 8 A T A = 25 C; t P < ms 5..3 S-input voltage V I 20 20 V Pin I and I2 Temperatures min. ) Not subject to production test; specified by design 2) Single pulse 3) Internally limited 4) ESD susceptibility HBM according to EIA/JESD22-A4-B (.5kΩ, 00pF) max. 5..4 Junction temperature T j 40 50 C 5..5 Storage temperature T stg 55 50 C ESD Protection 4) 5..6 Input S-Switch V ESD 0.3 kv 5..7 Input HS-Switch V ESD kv 5..8 Status HS-Switch V ESD 2 kv 5..9 Output S and HS-Switch V ESD 8 kv all other pins connected to Ground Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as outside normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 3 Rev..0, 2007-06-2
5.2 Functional Range Pos. Parameter Symbol imit Values Unit Remarks min. max. 5.2.20 Supply voltage V S V UVOFF 42 V After V S rising above V UVON 5.2.2 Input voltage HS V IH 0.3 5 V 5.2.22 Input voltage S V I 0.3 20 V 5.2.23 Status output current I ST 0 2 ma 5.2.24 Junction temperature T j 40 50 C Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table 5.3 Thermal Resistance Pos. Parameter Symbol imit Values Unit Conditions 5.3.25 S-junction to soldering point ) Min. Typ. Max. R thjsp 20 K/W measured to pin 3 or 2 5.3.26 HS-junction to soldering point ) R thjsp 20 K/W measured to pin 9 5.3.27 Junction to Ambient ) R thja = T j(hs) / (P (HS) + P (S) ) R thja 36 K/W 2) ) Not subject to production test, specified by design. 2) Specified R thja value is according to Jedec JESD5-2,-5,-7 at natural convection on FR4 2s2p board; The Product (chip+package) was simulated on a 76.2 x 4.3 x.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Data Sheet 4 Rev..0, 2007-06-2
5.4 Electrical Characteristics I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Pos. Parameter Symbol imit Values Unit Test Condition min. typ. max. Current Consumption HS-switch 5.4.28 Quiescent current I S 5 9 µa IH = IH2 = 0 V T j = 25 C 5.4.29 Supply current; one HS-switch active 5.4.30 Supply current; both HS-switches active 5.4.3 eakage current of high-side switch 5.4.32 eakage current through logic GND in free wheeling condition Current Consumption S-switch 3 µa IH = IH2 = 0 V I S 2.5 ma IH or IH2 = 5 V V S = 2 V I S 2 5 ma IH and IH2 = 5 V V S = 2 V I SH K 6 µa V IH = V SH = 0 V V S = 2 V I KC = I FH + 0 ma I FH = 3 A I SH V S = 2 V 5.4.33 Input current I I 0 00 na V I = 20 V; V DS = 0V 5.4.34 eakage current of low-side switch I D K 0 µa V I = 0 V V DS = 40V Under Voltage ockout HS-switch 5.4.35 Switch-ON voltage V UVON 4.8 V V S increasing 5.4.36 Switch-OFF voltage V UVOFF.8 3.5 V V S decreasing 5.4.37 Switch ON/OFF hysteresis V UVHY V V UVON V UVOFF Output stages 5.4.38 Inverse diode of high-side switch; Forward-voltage 5.4.39 Inverse diode of low-side switch; Forward-voltage 5.4.40 Static drain-source on-resistance of high-side switch 5.4.4 Static drain-source on-resistance of low-side switch V FH 0.8.2 V I FH = 3 A V F 0.8.2 V I F = 3 A R DS ON H 0 mω I SH = A; V S = 2 V T j = 25 C 200 280 mω I SH = A; V S = 2 V T j = 50 C R DS ON 80 mω I S = A; V I = 5 V T j = 25 C 40 200 mω I S = A; V I = 5 V T j = 50 C Data Sheet 5 Rev..0, 2007-06-2
I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Pos. Parameter Symbol imit Values Unit Test Condition min. typ. max. Short Circuit of high-side switch to GND 5.4.42 Initial peak SC current t del = 00 µs; V S = 2 V; V DSH = 2V I SCP H 9 3 A T j = 40 C 9.5 A T j = + 25 C 5.5 7 9 A T j = + 50 C Short Circuit of high-side switch to V S 5.4.43 Output pull-down-resistor R O 2 22 50 kω V DS = 3 V Thermal Shutdown ) 5.4.44 Thermal shutdown junction temperature 5.4.45 Thermal switch-on junction temperature T j SD 55 80 90 C T j SO 50 70 80 C 5.4.46 Temperature hysteresis Τ 0 C Τ = T jsd T jso Status Flag Output ST of high-side switch 5.4.47 ow output voltage V ST 0.2 0.6 V I ST =.6 ma 5.4.48 eakage current I ST K 0 µa V ST = 5 V 5.4.49 Zener-limit-voltage V ST Z 5.4 V I ST =.6 ma Switching times of high-side switch ) 5.4.50 Turn-ON-time to 90% V SH t ON 75 60 µs R oad = 2 Ω 5.4.5 Turn-OFF-time to 0% V SH t OFF 60 60 µs V S = 2 V 5.4.52 Slew rate on 0 to 30% V SH dv/d ton.9 V/µs 5.4.53 Slew rate off 70 to 40% V SH -dv/d toff 2.7 V/µs Switching times of low-side switch ) 5.4.54 Turn-ON Delay Time t d(on) 5 ns resistive load I S = 3A; V DS =2V 5.4.55 Rise Time t r 22 ns V I = 5V; R G = 6Ω 5.4.56 Switch-OFF Delay Time t d(off) 3 ns 5.4.57 Fall Time t f 8 ns Gate charge of low-side switch ) 5.4.58 Input to source charge Q IS nc I S = 3 A; V DS =2 V 5.4.59 Input to drain charge Q ID 3 nc I S = 3 A; V DS =2 V 5.4.60 Input charge total Q I 7 5 nc I S = 3 A; V DS =2 V V I = 0 to 5 V 5.4.6 Input plateau voltage V (plateau) 2.8 - V I S = 3 A; V DS =2 V )Not subject to production test; specified by design Data Sheet 6 Rev..0, 2007-06-2
I SH = I SH2 = I S = I S2 = 0 A; 40 C < T j < 50 C; 8 V < V S < 8 V unless otherwise specified Pos. Parameter Symbol imit Values Unit Test Condition min. typ. max. Control Inputs of high-side switches IH, 2 5.4.62 H-input voltage V IH High 2.5 V 5.4.63 -input voltage V IH ow V 5.4.64 Input voltage hysteresis V IH HY 0.3 V 5.4.65 H-input current I IH High 5 30 60 µa V IH = 5 V 5.4.66 -input current I IH ow 5 20 µa V IH = 0.4 V 5.4.67 Input series resistance R I 2.7 4 5.5 kω 5.4.68 Zener limit voltage V IH Z 5.4 V I IH =.6 ma Control Inputs I, 2 5.4.69 Gate-threshold-voltage V I th 0.9.7 2.35 V I D = 0.5 ma ) Not subject to production test; specified by design Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specified mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T A = 25 C and the given supply voltage. Data Sheet 7 Rev..0, 2007-06-2
6 Application Information Note: The following simplified application examples are given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. The function of the described circuits must be verified in the real application Watchdog Reset Q TE 4278G I V S =2V R Q 00 kω C Q 22µF D C D 47nF D0 Z39 C S 0µF WD R V CC DHVS 5,0,9,24 R S ST 8 0 kω Diagnosis Biasing and Protection IH 7 Gate Driver IH2 9 Gate Driver R O R O2 20,2 2,4,5,8 SH2 D2 C866 µp GND 6 22,23 SH M,3,25,28 D I 2 I2 3 26,27 6,7 GND S S2 Figure 4 Application Example BTM7700G Data Sheet Rev..0, 2007-06-2
Green Product (RoHS compliant) 7 Package Outlines -0. 0.2 2.45-0.2 2.65 max 7.6 0.35 x 45 ) -0.2 0.23 +0.09 8 max.27 0.4 +0.8 +0.5 2) 0.35 0.2 28x 0. 0.3 ±0.3 28 5 Index Marking 4 ) 8. -0.4 ) Does not include plastic or metal protrusions of 0.5 max rer side 2) Does not include dambar protrusion of 0.05 max per side GPS0523 Figure 5 PG-DSO-28-22 (Plastic Transistor Single Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm Data Sheet Rev..0, 2007-06-2
8 Revision History Rev. Date Changes.0 2007-06-2 Initial Version Data Sheet Rev..0, 2007-06-2
Edition 2007-06-2 Published by Infineon Technologies AG 8726 Munich, Germany 6/25/07 Infineon Technologies AG All Rights Reserved. egal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. ife support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.