Standard Products UT54AS273/UT54ATS273 Octal -Flip-Flops with lear atasheet ecember 16, 2011 www.aeroflex.com/logic FEATUES ontains eight flip-flops with single-rail outputs Buffered clock and direct clear inputs Individual data input to each flip-flop Applications include: - Buffer/storage registers, shift registers, and pattern generators MOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin IP - 20-lead flatpack UT54AS273 - SM 5962-96578 UT54ATS273 - SM 5962-96579 ESIPTION The UT54AS273 and the UT54ATS273 are positive-edgetriggered -type flip-flops with a direct clear input. Information at the inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. When the clock input is at either the high or low level, the input signal has no effect at the output. The devices are characterized over full military temperature range of -55 to +125. FUNTION TABLE PINOUTS L 1Q 1 2 2Q 3Q 3 4 4Q V SS LOGI SYMBOL L 1Q 1 2 2Q 3Q 3 4 4Q V SS 20-Pin IP Top View 1 2 3 4 5 6 7 20 19 18 17 16 15 14 8 13 9 12 10 11 20-Lead Flatpack Top View 1 2 3 4 5 6 20 19 18 17 16 15 7 14 8 13 9 12 10 11 V 8Q 8 7 7Q 6Q 6 5 5Q LK V 8Q 8 7 7Q 6Q 6 5 5Q LK INPUTS OUTPUTS L LK x Q x L X X L H H H L H L X H L No change (1) L (11) LK (3) 1 (4) 2 (7) 3 (8) 4 (13) 5 (14) 6 (17) 7 (18) 8 1 1 (2) 1Q (5) 2Q (6) 3Q (9) 4Q (12) 5Q (15) 6Q (16) 7Q (19) 8Q 1 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IE Publication 617-12.
2 LOGI IAGAM 1 (3) 1Q (2) 2 (4) 2Q (5) 3 (7) 3Q (6) 4 (8) 4Q (9) 5 (13) 5Q (12) 6 (14) 6Q (15) 7 (17) 7Q (16) 8 (18) 8Q (19) (11) (1) L LK
OPEATIONAL ENVIONMENT 1 PAAMETE LIMIT UNITS Total ose 1.0E6 rads(si) SEU Threshold 2 80 MeV-cm 2 /mg SEL Threshold 120 MeV-cm 2 /mg Neutron Fluence 1.0E14 n/cm 2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. evice storage elements are immune to SEU affects. ABSOLUTE MAXIMUM ATINGS SYMBOL PAAMETE LIMIT UNITS V Supply voltage -0.3 to 7.0 V V I/O Voltage any pin -.3 to V +.3 V T STG Storage Temperature range -65 to +150 T J Maximum junction temperature +175 T LS Lead temperature (soldering 5 seconds) +300 J Thermal resistance junction to case 20 /W I I input current 10 ma P Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EOMMENE OPEATING ONITIONS SYMBOL PAAMETE LIMIT UNITS V Supply voltage 4.5 to 5.5 V V IN Input voltage any pin 0 to V V T Temperature range -55 to + 125 3
ELETIAL HAATEISTIS 7 (V = 5.0V 10%; V SS = 0V 6, -55 < T < +125 ); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PAAMETE ONITION MIN MAX UNIT V IL Low-level input voltage 1 ATS AS V IH High-level input voltage 1 ATS AS 0.8 V.3V.5V V.7V I IN Input leakage current ATS/AS V IN = V or V SS -1 1 A V OL Low-level output voltage 3 ATS AS I OL = 8.0mA I OL = 100 A 0.40 0.25 V V OH High-level output voltage 3 ATS AS I OH = -8.0mA I OH = -100 A.7V V - 0.25 V I OS Short-circuit output current 2,4 ATS/AS V O = V and V SS -200 200 ma I OL Output current 10 (Sink) V IN = V or V SS V OL = 0.4V 8 ma I OH Output current 10 (Source) V IN = V or V SS V OH = V - 0.4V -8 ma P total Power dissipation 2, 8, 9 L = 50pF 1.9 mw/ MHz I Q Quiescent Supply urrent V = 5.5V 10 A I Q Quiescent Supply urrent elta ATS For input under test V IN = V - 2.1V 1.6 ma For all other inputs V IN = V or V SS V = 5.5V IN Input capacitance 5 = 1MHz @ 0V 15 pf OUT Output capacitance 5 = 1MHz @ 0V 15 pf 4
Notes: 1. Functional tests are conducted in accordance with MIL-ST-883 with the following input test conditions: V IH = V IH (min) + 20%, - 0%; V IL = V IL (max) + 0%, - 50%, as specified herein, for TTL, MOS, or Schmitt compatible inputs. evices may be tested using any input voltage within the above specified range, but are guaranteed to V IH (min) and V IL (max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PF-38535, for current density 5.0E5 amps/cm 2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. apacitance measured for initial qualification and when design changes may affect the value. apacitance is measured between the designated terminal and V SS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 5
A ELETIAL HAATEISTIS 2 (V = 5.0V 10%; V SS = 0V 6, -55 < T < +125 ); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PAAMETE MINIMUM MAXIMUM UNIT t PLH LK to Q 4 17 ns t PHL LK to Q 4 19 ns t PHL L to Q 5 19 ns f MAX Maximum clock frequency 63 MHz t SU1 L inactive setup time before LK 5 ns t SU2 ata setup time before LK 5 ns t H ata hold time after LK 3 ns t W Minimum pulse width L low LK high LK low 8 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(si). 6
PAKAGING Side-Brazed Packages 7
FLATPAK PAKAGES 8
UT54AS273/UT54ATS273: SM 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder = Gold X = Optional Package Type: X = 20-lead ceramic bottom-brazed dual-in-line Flatpack = 20-lead ceramic side-brazed dip lass esignator: Q = QML lass Q V = QML lass V evice Type: 01 rawing Number: 96578 = UT54AS273 96579 = UT54ATS273 Total ose: (Notes 3 & 4) = 1E5 rads(si) F = 3E5 rads(si) G = 5E5 rads(si) H = 1E6 rads(si) Notes: 1. Lead finish (A,, or X) must be specified. 2. If an X is specified when ordering, part marking will match the lead finish and will be either A (solder) or (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. 4. evice type 02 is only offered with a TI tolerance guarantee of 3E5 rads(si) or 1E6 rads(si) and is tested in accordance with MIL-ST-883 Test Method 1019 ondition A and section 3.11.2. evice type 03 is only offered with a TI tolerance guarantee of 1E5 rads(si), 3E5 rads(si), and 5E5 rads(si), and is tested in accordance with MIL-ST-883 Test Method 1019 ondition A. 9
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