2-K Microwir Srial CMOS EEPROM CT93C57 Not Rcommndd for Nw signs: Rplac with CT93C56 scription Th CT93C56/57 is a 2 k CMOS Srial EEPROM dvic which is organizd as ithr 128 rgistrs of 16 its (ORG pin at V CC ) or 256 rgistrs of 8 its (ORG pin at GN). Each rgistr can writtn (or rad) srially y using th (or ) pin. Th CT93C56/57 faturs squntial rad and slf timd intrnal writ with auto clar. On chip Powr On Rst circuitry protcts th intrnal logic against powring up in th wrong stat. Faturs High Spd Opration: 2 MHz 1.8 V to 5.5 V Supply Voltag Rang Slctal x8 or x16 Mmory Organization Squntial Rad Softwar Writ Protction Powr up Inadvrtnt Writ Protction Low Powr CMOS Tchnology 1,000,000 Program/Eras Cycls 100 Yar ata Rtntion Industrial and Extndd Tmpratur Rangs 8 pin PP, SOIC, TSSOP and 8 pad TFN Packags Ths vics ar P Fr, Halogn Fr/BFR Fr and ar RoHS Compliant ORG V CC CT93C56 CT93C57 GN Figur 1. Functional Symol NOTE: Whn th ORG pin is connctd to V CC, th x16 organization is slctd. Whn it is connctd to ground, th x8 pin is slctd. If th ORG pin is lft unconnctd, thn an intrnal pullup dvic will slct th x16 organization. SOIC 8 V or W SUFFIX CSE 751B Pin Nam V CC GN ORG NC PP 8 L SUFFIX CSE 646 1 2 3 4 SOIC 8 EIJ X SUFFIX CSE 751BE TSSOP 8 Y SUFFIX CSE 948L PIN CONFIGURTIONS 8 V CC 7 NC 6 ORG 5 GN PP (L), SOIC (V, X), TSSOP (Y), TFN (VP2) * SOIC (W) rotatd pin out packag not rcommndd for nw dsigns PIN FUNCTION Chip Slct Clock Input Srial ata Input Srial ata Output Powr Supply Ground Function Mmory Organization No Connction TFN 8 VP2 SUFFIX CSE 511K NC 1 8 ORG V CC 2 3 4 7 6 5 GN SOIC (W*) ORERING INFORMTION S dtaild ordring and shipping information in th packag dimnsions sction on pag 15 of this data sht. Smiconductor Componnts Industris, LLC, 2014 May, 2014 Rv. 19 1 Pulication Ordr Numr: CT93C56/
Tal 1. BSOLUTE MXIMUM RTINGS Paramtrs Ratings Units Storag Tmpratur 65 to +150 C Voltag on ny Pin with Rspct to Ground (Not 1) 0.5 to +6.5 V Strsss xcding thos listd in th Maximum Ratings tal may damag th dvic. If any of ths limits ar xcdd, dvic functionality should not assumd, damag may occur and rliaility may affctd. 1. Th C input voltag on any pin should not lowr than 0.5 V or highr than V CC + 0.5 V. uring transitions, th voltag on any pin may undrshoot to no lss than 1.5 V or ovrshoot to no mor than V CC + 1.5 V, for priods of lss than 20 ns. Tal 2. RELIBILITY CHRCTERISTI (Not 2) Symol Paramtr Min Units N EN (Not 3) Enduranc 1,000,000 Program / Eras Cycls T R ata Rtntion 100 Yars 2. Ths paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat EC Q100 and JEEC tst mthods. 3. Block Mod, V CC = 5 V, 25 C Tal 3..C. OPERTING CHRCTERISTI, CT93C56 (V CC = +1.8 V to +5.5 V, T = 40 C to +125 C unlss othrwis spcifid.) Symol Paramtr Tst Conditions Min Max Units I CC1 Powr Supply Currnt (Writ) f = 1 MHz, V CC = 5.0 V 1 m I CC2 Powr Supply Currnt (Rad) f = 1 MHz, V CC = 5.0 V 500 I SB1 I SB2 I LI I LO Powr Supply Currnt (Standy) (x8 Mod) Powr Supply Currnt (Standy) (x16 Mod) Input Lakag Currnt Output Lakag Currnt V IN = GN or V CC, = GN ORG = GN T = 40 C to +85 C 2 T = 40 C to +125 C 4 V IN = GN or V CC, = GN ORG = Float or V CC T = 40 C to +85 C 1 T = 40 C to +125 C 2 V IN = GN to V CC T = 40 C to +85 C 1 V OUT = GN to V CC, = GN T = 40 C to +125 C 2 T = 40 C to +85 C 1 T = 40 C to +125 C 2 V IL1 Input Low Voltag 4.5 V V CC < 5.5 V 0.1 0.8 V V IH1 Input High Voltag 4.5 V V CC < 5.5 V 2 V CC + 1 V V IL2 Input Low Voltag 1.8 V V CC < 4.5 V 0 V CC x 0.2 V V IH2 Input High Voltag 1.8 V V CC < 4.5 V V CC x 0.7 V CC + 1 V V OL1 Output Low Voltag 4.5 V V CC < 5.5 V, I OL = 2.1 m 0.4 V V OH1 Output High Voltag 4.5 V V CC < 5.5 V, I OH = 400 V OL2 Output Low Voltag 1.8 V V CC < 4.5 V, I OL = 1 m 2.4 V 0.2 V V OH2 Output High Voltag 1.8 V V CC < 4.5 V, I OH = 100 V CC 0.2 V Product paramtric prformanc is indicatd in th Elctrical Charactristics for th listd tst conditions, unlss othrwis notd. Product prformanc may not indicatd y th Elctrical Charactristics if opratd undr diffrnt conditions. 2
Tal 4..C. OPERTING CHRCTERISTI, CT93C57, i Rv. E Matur Product (NOT RECOMMENE FOR NEW ESIGNS) (V CC = +1.8 V to +5.5 V, T = 40 C to +125 C unlss othrwis spcifid.) Symol Paramtr Tst Conditions Min Max Units I CC1 Powr Supply Currnt (Writ) f = 1 MHz, V CC = 5.0 V 3 m I CC2 Powr Supply Currnt (Rad) f = 1 MHz, V CC = 5.0 V 500 I SB1 Powr Supply Currnt (Standy) (x8 Mod) V IN = GN or V CC, = GN ORG = GN 10 I SB2 Powr Supply Currnt (Standy) (x16 Mod) V IN = GN or V CC, = GN 10 ORG = Float or V CC I LI Input Lakag Currnt V IN = GN to V CC 1 I LO Output Lakag Currnt V OUT = GN to V CC, = GN 1 V IL1 Input Low Voltag 4.5 V V CC < 5.5 V 0.1 0.8 V V IH1 Input High Voltag 4.5 V V CC < 5.5 V 2 V CC + 1 V V IL2 Input Low Voltag 1.8 V V CC < 4.5 V 0 V CC x 0.2 V V IH2 Input High Voltag 1.8 V V CC < 4.5 V V CC x 0.7 V CC + 1 V V OL1 Output Low Voltag 4.5 V V CC < 5.5 V, I OL = 2.1 m 0.4 V V OH1 Output High Voltag 4.5 V V CC < 5.5 V, I OH = 400 2.4 V V OL2 Output Low Voltag 1.8 V V CC < 4.5 V, I OL = 1 m 0.2 V V OH2 Output High Voltag 1.8 V V CC < 4.5 V, I OH = 100 V CC 0.2 V Tal 5. PIN CPCITNCE (T = 25 C, f = 1 MHz, V CC = 5 V) Symol Tst Conditions Min Typ Max Units C OUT (Not 4) Output Capacitanc () V OUT = 0 V 5 pf C IN (Not 4) Input Capacitanc (,,, ORG) V IN = 0 V 5 pf 4. Ths paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat EC Q100 and JEEC tst mthods. 3
Tal 6..C. CHRCTERISTI (Not 5), CT93C56 (V CC = +1.8V to +5.5V, T = 40 C to +125 C, unlss othrwis spcifid.) Symol Paramtr Limits t S Stup Tim 50 ns t H Hold Tim 0 ns t S Stup Tim 100 ns t H Hold Tim 100 ns t P1 Output lay to 1 0.25 s t P0 Output lay to 0 0.25 s t HZ (Not 6) Output lay to High Z 100 ns t EW Program/Eras Puls Width 5 ms t MIN Minimum Low Tim 0.25 s t HI Minimum High Tim 0.25 s t LOW Minimum Low Tim 0.25 s t SV Output lay to Status Valid 0.25 s MX Maximum Clock Frquncy C 2000 khz Tal 7..C. CHRCTERISTI (Not 5), CT93C57, i Rv. E Matur Product (NOT RECOMMENE FOR NEW ESIGNS) Symol Paramtr Min Limits Max V CC = 1.8 V 5.5 V V CC = 2.5 V 5.5 V V CC = 4.5 V 5.5 V Min Max Min Max Min Max t S Stup Tim 200 100 50 ns t H Hold Tim 0 0 0 ns t S Stup Tim 400 200 100 ns t H Hold Tim 400 200 100 ns t P1 Output lay to 1 1 0.5 0.25 s t P0 Output lay to 0 1 0.5 0.25 s t HZ (Not 6) Output lay to High Z 400 200 100 ns t EW Program/Eras Puls Width 10 10 10 ms t MIN Minimum Low Tim 1 0.5 0.25 s t HI Minimum High Tim 1 0.5 0.25 s t LOW Minimum Low Tim 1 0.5 0.25 s t SV Output lay to Status Valid 1 0.5 0.25 s MX Maximum Clock Frquncy C 250 C 500 C 1000 khz Units Units Tal 8. POWER UP TIMING (Nots 6 and 7) Symol Paramtr Max Units t PUR Powr up to Rad Opration 1 ms t PUW Powr up to Writ Opration 1 ms 5. Tst conditions according to.c. Tst Conditions tal. 6. Ths paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat EC Q100 and JEEC tst mthods. 7. t PUR and t PUW ar th dlays rquird from th tim V CC is stal until th spcifid opration can initiatd. 4
Tal 9..C. TEST CONTIONS Input Ris and Fall Tims 50 ns Input Puls Voltags 0.4 V to 2.4 V 4.5 V V CC 5.5 V Timing Rfrnc Voltags 0.8 V, 2.0 V 4.5 V V CC 5.5 V Input Puls Voltags 0.2 V CC to 0.7 V CC 1.8 V V CC 4.5 V Timing Rfrnc Voltags 0.5 V CC 1.8 V V CC 4.5 V Output Load Currnt Sourc I OLmax /I OHmax ; CL=100 pf vic Opration Th CT93C56/57 is a 2048 it nonvolatil mmory intndd for us with industry standard microprocssors. Th CT93C56/57 can organizd as ithr rgistrs of 16 its or 8 its. Whn organizd as X16, svn 10 it instructions for 93C57 or svn 11 it instructions for 93C56 control th rading, writing and ras oprations of th dvic. Whn organizd as X8, svn 11 it instructions for 93C57 or svn 12 it instructions for 93C56 control th rading, writing and ras oprations of th dvic. Th CT93C56/57 oprats on a singl powr supply and will gnrat on chip, th high voltag rquird during any writ opration. Instructions, addrsss, and writ data ar clockd into th pin on th rising dg of th clock (). Th pin is normally in a high impdanc stat xcpt whn rading data from th dvic, or whn chcking th rady/usy status aftr a writ opration. Th srial communication protocol follows th timing shown in Figur 2. Th rady/usy status can dtrmind aftr th start of intrnal writ cycl y slcting th dvic ( high) and polling th pin; low indicats that th writ opration is not compltd, whil high indicats that th dvic is rady for th nxt instruction. If ncssary, th pin may placd ack into a high impdanc stat during chip slct y shifting a dummy 1 into th pin. Th pin will ntr th high impdanc stat on th rising dg of th clock (). Placing th pin into th high impdanc stat is rcommndd in applications whr th pin and th pin ar to tid togthr to form a common /O pin. t HI t LOW t H t S t H VLI VLI t S t S t P0, t P1 t MN T VLI Figur 2. Synchronous ata Timing 5
Th format for all instructions snt to th dvic is a logical 1 start it, a 2 it (or 4 it) opcod, 7 it addrss (CT93C57) / 8 it addrss (CT93C56) (an additional it whn organizd X8) and for writ oprations a 16 it data fild (8 it for X8 organizations). Th instruction format is shown in Instruction St tal. Tal 10. INSTRUCTION SET Instruction vic Typ Start Bit Opcod ddrss ata x8 x16 x8 x16 Commnts RE 93C56 (Not 8) 1 10 8 0 7 0 Rad ddrss 93C57 1 10 7 0 6 0 N 0 ERSE 93C56 (Not 8) 1 11 8 0 7 0 Clar ddrss 93C57 1 11 7 0 6 0 N 0 WRITE 93C56 (Not 8) 1 01 8 0 7 0 7 0 15 0 Writ ddrss 93C57 1 01 7 0 6 0 7 0 15 0 N 0 EWEN 93C56 (Not 8) 1 00 11XXXXXXX 11XXXXXX Writ Enal 93C57 1 00 11XXXXXX 11XXXXX EWS 93C56 (Not 8) 1 00 00XXXXXXX 00XXXXXX Writ isal 93C57 1 00 00XXXXXX 00XXXXX ERL 93C56 (Not 8) 1 00 10XXXXXXX 10XXXXXX Clar ll 93C57 1 00 10XXXXXX 10XXXXX ddrsss WRL 93C56 (Not 8) 1 00 01XXXXXXX 01XXXXXX 7 0 15 0 Writ ll 93C57 1 00 01XXXXXX 01XXXXX 7 0 15 0 ddrsss 8. ddrss it 8 for 256x8 organization and 7 for 128x16 organization ar on t Car its, ut must kpt at ithr a 1 or 0 for RE, WRITE and ERSE commands. 6
Rad Upon rciving a RE command and an addrss (clockd into th pin), th pin of th CT93C56/57 will com out of th high impdanc stat and, aftr snding an initial dummy zro it, will gin shifting out th data addrssd (MSB first). Th output data its will toggl on th rising dg of th clock and ar stal aftr th spcifid tim dlay (t P0 or t P1 ). For th CT93C56/57, aftr th initial data word has n shiftd out and rmains assrtd with th clock continuing to toggl, th dvic will automatically incrmnt to th nxt addrss and shift out th nxt data word in a squntial RE mod. s long as is continuously assrtd and continus to toggl, th dvic will kp incrmnting to th nxt addrss automatically until it rachs to th nd of th addrss spac, thn loops ack to addrss 0. In th squntial RE mod, only th initial data word is prcdd y a dummy zro it. ll susqunt data words will follow without a dummy zro it. Th RE instruction timing is illustratd in Figur 3. Eras/Writ Enal and isal Th CT93C56/57 powrs up in th writ disal stat. ny writing aftr powr up or aftr an EWS (ras/writ disal) instruction must first prcdd y th EWEN (ras/writ nal) instruction. Onc th writ instruction is nald, it will rmain nald until powr to th dvic is rmovd, or th EWS instruction is snt. Th EWS instruction can usd to disal all CT93C56/57 writ and ras instructions, and will prvnt any accidntal writing or claring of th dvic. ata can rad normally from th dvic rgardlss of th writ nal/disal status. Th EWEN and EWS instructions timing is shown in Figur 4. 1 1 0 N N 1 0 on t Car HIGH Z t P0 ummy 0 15... 0 or 7... 0 Figur 3. RE Instruction Timing ddrss + 1 ddrss + 2 ddrss + n 15... 0 15... 0 15... or or or 7... 0 7... 0 7... STNBY 1 0 0 * * ENBLE = 11 SBLE = 00 Figur 4. EWEN/EWS Instruction Timing 7
Writ ftr rciving a WRITE command (Figur 5), addrss and th data, th (Chip Slct) pin must dslctd for a minimum of t MIN. Th falling dg of will start th slf clocking clar and data stor cycl of th mmory location spcifid in th instruction. Th clocking of th pin is not ncssary aftr th dvic has ntrd th slf clocking mod. Th rady/usy status of th CT93C56/57 can dtrmind y slcting th dvic and polling th pin. Sinc this dvic faturs uto Clar for writ, it is NOT ncssary to ras a mmory location for it is writtn into. Eras Upon rciving an ERSE command and addrss, th (Chip Slct) pin must dassrtd for a minimum of t MIN (Figur 6). Th falling dg of will start th slf clocking clar cycl of th slctd mmory location. Th clocking of th SaK pin is not ncssary aftr th dvic has ntrd th slf clocking mod. Th rady/usy status of th CT93C56/57 can dtrmind y slcting th dvic and polling th pin. Onc clard, th contnt of a clard location rturns to a logical 1 stat. t MIN STTUS VERIFY STNBY N N 1 0 N 0 1 0 1 HIGH Z t SV BUSY REY t HZ HIGH Z t EW Figur 5. Writ Instruction Timing STTUS VERIFY STNBY N N 1 0 t 1 1 1 HIGH Z t SV BUSY REY t HZ HIGH Z t EW Figur 6. Eras Instruction Timing 8
Eras ll Upon rciving an ERL command (Figur 7), th (Chip Slct) pin must dslctd for a minimum of t MIN. Th falling dg of will start th slf clocking clar cycl of all mmory locations in th dvic. Th clocking of th pin is not ncssary aftr th dvic has ntrd th slf clocking mod. Th rady/usy status of th CT93C56/57 can dtrmind y slcting th dvic and polling th pin. Onc clard, th contnts of all mmory its rturn to a logical 1 stat. Writ ll Upon rciving a WRL command and data, th (Chip Slct) pin must dslctd for a minimum of t MIN (Figur 8). Th falling dg of will start th slf clocking data writ to all mmory locations in th dvic. Th clocking of th pin is not ncssary aftr th dvic has ntrd th slf clocking mod. Th rady/usy status of th CT93C56/57 can dtrmind y slcting th dvic and polling th pin. It is not ncssary for all mmory locations to clard for th WRL command is xcutd. STTUS VERIFY STNBY t 1 0 0 1 0 HIGH Z t SV BUSY REY t HZ HIGH Z t EW Figur 7. ERL Instruction Timing STTUS VERIFY STNBY t MIN 1 0 0 0 1 N 0 t SV t HZ BUSY REY HIGH Z t EW Figur 8. WRL Instruction Timing 9
PCKGE MENSIONS PP 8, 300 mils CSE 646 01 ISSUE SYMBOL MIN NOM MX PIN # 1 IENTIFICTION E1 5.33 2 2 c 0.38 2.92 0.36 1.14 0.20 9.02 3.30 0.46 1.52 0.25 9.27 4.95 0.56 1.78 0.36 10.16 E 7.62 7.87 8.25 E1 B 6.10 7.87 6.35 2.54 BSC 7.11 10.92 L 2.92 3.30 3.80 TOP VIEW E 2 L 2 c B SIE VIEW EN VIEW Nots: (1) ll dimnsions ar in millimtrs. (2) Complis with JEEC MS-001. 10
PCKGE MENSIONS SOIC 8, 150 mils CSE 751B 01 ISSUE O SYMBOL MIN NOM MX 1.35 1.75 0.10 0.25 0.33 0.51 E1 E c 0.19 4.80 0.25 5.00 E 5.80 6.20 E1 3.80 4.00 1.27 BSC h 0.25 0.50 PIN # 1 IENTIFICTION L 0.40 1.27 θ 0º 8º TOP VIEW h θ c L SIE VIEW EN VIEW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) Complis with JEEC MS-012. 11
PCKGE MENSIONS SOIC 8, 208 mils CSE 751BE 01 ISSUE O SYMBOL MIN NOM MX E1 E c E E1 0.05 0.36 0.19 5.13 7.75 5.13 2.03 0.25 0.48 0.25 5.33 8.26 5.38 1.27 BSC L 0.51 0.76 θ 0º 8º PIN#1 IENTIFICTION TOP VIEW L c SIE VIEW EN VIEW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) Complis with EIJ ER-7320. 12
PCKGE MENSIONS TSSOP8, 4.4x3 CSE 948L 01 ISSUE O SYMBOL MIN NOM MX 1.20 0.05 0.15 2 0.80 0.90 1.05 0.19 0.30 E1 E c 0.09 0.20 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.65 BSC L 1.00 REF L1 θ 0.50 0.60 0.75 0º 8º TOP VIEW 2 1 c SIE VIEW L1 EN VIEW L Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) Complis with JEEC MO-153. 13
PCKGE MENSIONS TFN8, 2x3 CSE 511K 01 ISSUE E E2 PIN#1 IENTIFICTION PIN#1 INEX RE 2 L TOP VIEW SIE VIEW BOTTOM VIEW SYMBOL MIN NOM MX 0.70 0.75 0.80 0.00 0.02 0.05 2 0.45 0.55 0.65 2 3 0.20 REF 0.20 0.25 0.30 3 1.90 2.00 2.10 2 1.30 1.40 1.50 FRONT VIEW E 2.90 3.00 3.10 E2 1.20 1.30 1.40 0.50 TYP L 0.20 0.30 0.40 Nots: (1) ll dimnsions ar in millimtrs. (2) Complis with JEEC MO-229. 14
Exampl of Ordring Information OPN CT93C56LI G I*4G / 93C56LI Spcific vic Marking Pkg Typ Tmpratur Rang PP 8 Lad Finish Shipping Tu, 50 Units / Tu CT93C56VE G I*4G / 93C56LE SOIC 8, JEEC E = Extndd ( 40 C to +125 C) Tu, 100 Units / Tu CT93C56VE GT3 I*4G / 93C56VE SOIC 8, JEEC E = Extndd ( 40 C to +125 C) Tap & Rl, 3000 Units / Rl CT93C56VI G I*4G / 93C56VI SOIC 8, JEEC Tu, 100 Units / Tu CT93C56VI GT3 I*4G / 93C56VI SOIC 8, JEEC Tap & Rl, 3000 Units / Rl CT93C56VP2I GT3 HB TFN 8 Tap & Rl, 3000 Units / Rl CT93C56WI G I*4G / 93C56WI SOIC 8, JEEC Tu, 100 Units / Tu CT93C56WI GT3 93C56W SOIC 8, JEEC Tap & Rl, 3000 Units / Rl CT93C56XI I*3G / 93C56XI SOIC 8, EIJ Matt Tin Tu, 94 Units / Tu CT93C56XI T2 I*3G / 93C56XI SOIC 8, EIJ Matt Tin Tap & Rl, 2000 Units / Rl CT93C56YI G M56 TSSOP 8 CT93C56YI GT3 M56 TSSOP 8 Tu, 100 Units / Tu Tap & Rl, 3000 Units / Rl CT93C57LI G I*4E/ 93C57LI PP 8 Tu, 50 Units / Tu CT93C57VI G I*4E / 93C57VI SOIC 8, JEEC Tu, 100 Units / Tu CT93C57VI GT3 I*4E / 93C57VI SOIC 8, JEEC Tap & Rl, 3000 Units / Rl CT93C57XI I*3E / 93C57X SOIC 8, EIJ Matt Tin Tu, 94 Units / Tu CT93C57XI T2 I*3E / 93C57X SOIC 8, EIJ Matt Tin Tap & Rl, 2000 Units / Rl CT93C57YI GT3 M57 TSSOP 8 Tap & Rl, 3000 Units / Rl 9. ll packags ar RoHS compliant (Lad fr, Halogn fr). 10. Th standard lad finish is. 11. CT93C57 NOT rcommndd for nw dsigns. 12. For information on tap and rl spcifications, including part orintation and tap sizs, plas rfr to our Tap and Rl Packaging Spcifications Brochur, BR8011/. 15
ON Smiconductor and ar rgistrd tradmarks of Smiconductor Componnts Industris, LLC (SCILLC). SCILLC owns th rights to a numr of patnts, tradmarks, copyrights, trad scrts, and othr intllctual proprty. listing of SCILLC s product/patnt covrag may accssd at www.onsmi.com/sit/pdf/patnt Marking.pdf. SCILLC rsrvs th right to mak changs without furthr notic to any products hrin. SCILLC maks no warranty, rprsntation or guarant rgarding th suitaility of its products for any particular purpos, nor dos SCILLC assum any liaility arising out of th application or us of any product or circuit, and spcifically disclaims any and all liaility, including without limitation spcial, consquntial or incidntal damags. Typical paramtrs which may providd in SCILLC data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. ll oprating paramtrs, including Typicals must validatd for ach customr application y customr s tchnical xprts. SCILLC dos not convy any licns undr its patnt rights nor th rights of othrs. SCILLC products ar not dsignd, intndd, or authorizd for us as componnts in systms intndd for surgical implant into th ody, or othr applications intndd to support or sustain lif, or for any othr application in which th failur of th SCILLC product could crat a situation whr prsonal injury or dath may occur. Should Buyr purchas or us SCILLC products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold SCILLC and its officrs, mploys, susidiaris, affiliats, and distriutors harmlss against all claims, costs, damags, and xpnss, and rasonal attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that SCILLC was nglignt rgarding th dsign or manufactur of th part. SCILLC is an Equal Opportunity/ffirmativ ction Employr. This litratur is sujct to all applical copyright laws and is not for rsal in any mannr. PUBLICTION ORERING INFORMTION LITERTURE FULFILLMENT: Litratur istriution Cntr for ON Smiconductor P.O. Box 5163, nvr, Colorado 80217 US Phon: 303 675 2175 or 800 344 3860 Toll Fr US/Canada Fax: 303 675 2176 or 800 344 3867 Toll Fr US/Canada Email: ordrlit@onsmi.com N. mrican Tchnical Support: 800 282 9855 Toll Fr US/Canada Europ, Middl East and frica Tchnical Support: Phon: 421 33 790 2910 Japan Customr Focus Cntr Phon: 81 3 5817 1050 16 ON Smiconductor Wsit: www.onsmi.com Ordr Litratur: http://www.onsmi.com/ordrlit For additional information, plas contact your local Sals Rprsntativ CT93C56/