MSP0x Processor V_. V_ V_. U Vcc Vcc R 0K SW, ETHER_T_00, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0 P.0/TLK P./T0 P./T P./T P./SMLK P./T0 P./T P./T /RST/NMI 0.u P UTTON_ UTTON_ ILTER_LK_SWITH _ILTER_LK_TMR _ILTER_LK_TMR LE_RE LE_GREEN LE_YELLOW USR_0 I_S URT_V# I_SL URT_TX_YG URT_RX_YG URT_TX URT_RX, ETHER_RESS_00, ETHER_RESS_0, ETHER_RESS_0, ETHER_RESS_0, _ILTER_LK_TMR, _ILTER_LK_TMR, ETHER_IOW#, ETHER_IOR# SPI_MEM_S# SPI_MOSI SPI_MISO SPI_LK SPI_MEM_RST# USR_ ETHER_SLEEP ETHER_RESET 0 0 0 0 P.0/LK P./TLK P.//T0 P./0/T P.//T P./Rosc P./LK/ME0 P./T0 P.0/STE0 P./SIMO0/S P./SOMI0 P./ULK0/SL P./UTX0 P./URX0 P./UTX P./URX P.0/T0 P./T P./T P./T P./T P./T P./T P./TLK P.0/STE P./SIMO P./SOMI P./ULK P./MLK P./SMLK P./LK P./ToutH/SVS TK TMS TI TO/TI XT Xout/Tclk X VRef XT LK_0_ LK_0_ LK_0_ LK_0_ Y.0000 MHZ Y. KHZ MSP_JTG_RST# MSP_JTG_TK MSP_JTG_TMS MSP_JTG_TI MSP_JTG_TO p 0 p N0_ N_ N_ N_ MI_ SYS_URRENT 0 0 P.0/0 P./ P./ P./ P./ P./ P.//0 P.///SVS VeRef Vref/VeRef 0 Vss MSP0 Vss _ MSP0x Processor Size ocument Number Rev MSP0x_LX ate: Saturday, June, 00 Sheet of
V_. V_. V_. J U V_ V_ V_ V_ TEST# V_ 0 V_ V_ RESET 0.u ETHER_RESET R. % R. % 0p T:.T Xmit T: Receive T T T R T R TX TX RX RX, ETHER_RESS_00, ETHER_RESS_0, ETHER_RESS_0, ETHER_RESS_0 0 0 0 S0 S S S S S S S S S S0 S S S S S S S S S MRQ0 MRQ MRQ MK0# MK# MK# IOHRY IOS# TX TX RX RX SLEEP# HIPSEL# S# V_. R 00K ETHER_SLEEP R 00 % 0.0u 0 0.0u 0 K K J000 Green LE Yellow LE V_., ETHER_T_00, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_IOW#, ETHER_IOR# 0 S0 S S S S S S S S0 S0 S0 S S S S S MEMS# EN MEMR# MEMW# RERESH# IOW# IOR# LNLE# 00 LKLE#/H0# STTUS#/H# SHE# ELS# EES EESK EEataOut EEataIn TRQ0 TRQ TRQ 0 TRQ O O I I 0 I I XTL Y R 0 R 0 R.K % 0 0 RES XTL _ 0MHZ_XTL S00 Ethernet Size ocument Number Rev MSP0x_LX ate: Saturday, June, 00 Sheet of
Segment isplays and I IO User LEs V_. J0 ON V_ V_. I_SL I_S R 0K R 0K V_. U V SL S T# 0 N N P0 0 P P P P P P P 0 N N PRGYR ddr = 0x RN 0 0 E 0 G P SEGMENT ISPLY The LTS0P isplays are common cathode. jumper should be installed between pins and of J and J. or a common anode part such as the LTS0 the jumper should be installed beween pins and. V_ J RE GRN YEL User Input R 00 R 00 R 00 V Y Y Y U SNLVGTR LE_RE LE_GREEN LE_YELLOW V_. U V SL S T# 0 N N P0 0 P P P P P P P 0 N N PRGYR RN 0 0 E 0 G P SEGMENT ISPLY V_ J SW P V_. R 0K 0.u UTTON_ ddr = 0xE V_. V_. U V SL S T# 0 N N P0 0 P P P P P P P 0 N N PRGYR N0_ILTER_ON N_ILTER_ON N_ILTER_ON N_ILTER_ON MI_ILTER_ON 0_ILTER_ON _ILTER_ON 0_MP_SHN SW P R 0K 0.u UTTON_ ddr = 0x RS V_. Mbit atalash URT_RX URT_TX URT_V# 0.u 0.u U R_ T_ OREON EN# V OREO# V V VLI# 0 R_ T_ MXUE 0.u Use a M passthrough cable to connect RS to a P. 0.u J ONN SU P J0 ON SPI_LK SPI_MOSI SPI_MISO SPI_MEM_RST# SPI_MEM_S# J ON V_. U SK V SI WP# SO RESET# S# T igital Peripherals Size ocument Number Rev MSP0x_LX ate: Saturday, June, 00 Sheet of
SYS_URRENT V_US RE R 00 U0 Vin u R % Iout Load ZXT00 VLO Max V R 00 % hanged this value so it is possible to measure up to 00m current draw. 0.u u V_ U Vin Vout Vin Vout ERR# NR EN REG0U. V_. u REG0_O# J V_. URT_TX_YG URT_RX_YG R 0 R 0 YEL RE GRN RE VTRG no longer is in the circuit. 0.u J J V SHELL SHELL US US Type onnector 0 V.u R 0K VLO V_ V_US U P.0 P0.0 P. P0. P. P0./XTL P. P0./XTL P. P0. 0 P. P0. P.P0./NVSTR P. P0./Vref VUS REG V P.0 P. P. P. P. P. P. 0 P. P.0/ 0 /RST/K 00 U N N ET_MOE Y_ Y_TO Y_OE# Y_TI Y_TMS Y_TK Y_RST Y_TST SN0VT US Transient Surge Suppresor 0.u J R.K ygnal Programming Port ONNX Xilinx Programming Port V_ When the switch is not installed, putting a jumper here will give the ygnal chip full control over the REG0. J V_. SW SW PT (NI) R.K R.K J ON R.K PL_TI PL_TK PL_TMS PL_TO ET_MOE RE (NI) R 00 (NI) _ILTER_LK 0_ILTER_LK _ILTER_LK_TMR _ILTER_LK_TMR, _ILTER_LK_TMR, _ILTER_LK_TMR Y_TMS Y_TI Y_OE# Y_TO ET_MOE Y_TK Y_RST Y_TST ET_TO ET_TI V_. ET_RESET ET_TK ET_TMS ET_TI ET_TO U 0 IO V_. V V 0 0/LK0 /Lk /LK /LK V V TI XR0XL TK TMS TO PORT_EN TO to ygnal Should be Inverted RST#/NMI Test/Vpp TK N TMS N TI/Vpp N 0 TI/TO N N N JTG HEER (NI) 0 0 V MSP_JTG_TMS MSP_JTG_TK MSP_JTG_TI MSP_JTG_RST# MSP_JTG_TO ILTER_LK_SWITH MI_ILTER_LK ET_TMS ET_TK ET_RESET USR_0 USR_ N0_ILTER_LK N_ILTER_LK N_ILTER_LK N_ILTER_LK JTG & rossonnect Size ocument Number Rev MSP0x_LX ate: Saturday, June, 00 Sheet of
nalog Input h 0 (00mVpp Max) nalog Input h (0mVpp Max) 00mVpp N0_ N0_ILTER_ON N0_ILTER_LK J MJSMT _ J ON V_ R 0K.u R 0K 0.u R.K U OP R 0K V_ 0 0.u U SHN# LK V OM OS MX 0.u J ON 0mVpp N_ N_ILTER_ON N_ILTER_LK J MJSMT _ J ON V_ R0 0K.u R 0K 0.u R.K U OP R 0K V_ 0.u U SHN# LK V OM OS MX 0.u J ON nalog Input h (00mVpp Max) N_ N_ILTER_ON N_ILTER_LK V_ J ON V J ON nalog Input h (Vpp Max) N_ N_ILTER_ON N_ILTER_LK V_ J ON V J ON J MJSMT R 0K 0.u 0 0.u J MJSMT R K 0.u 0 0.u 00mVpp.u R0 0K R K U OP R 0K LK V U SHN# OM OS MX 0.u Vpp.u R 0K R0 K U OP R 0K LK V U SHN# OM OS MX 0.u 0 Output & Speaker Output V_ 0.u V ILTER_ON 0_MP_SHN 0_ILTER_ON J ON 0_ 0_ILTER_LK U SHN# LK V 0.u OM OS MX u R 0K 0.u u U SHN VO PSS V VO TPGNR R0 K V_ LS OHM SPK.u J ON ILTER_LK LK V U0 SHN# OM OS MX 0.u _ J ON nalog Size ocument Number Rev MSP0x_LX ate: Saturday, June, 00 Sheet of
Microphone Input MI_ MI_ILTER_ON MI_ILTER_LK J ON R 0K R K V _ ELETRET MK V_ R0.K 0.0u R K R 0K _ R 0K R V 0.u _ U OP 00K 0.0u R K V R K 0.u _ U OP V_ 0.u U SHN# LK V OM OS MX 0.u _ Mechanical iducials and other Mounting Holes IUIL Test Points IUIL V_. IUIL V_ MT MT MT MT SPKRMNT SPKRMNT, ETHER_RESS_00, ETHER_RESS_0, ETHER_RESS_0, ETHER_RESS_0, _ILTER_LK_TMR, _ILTER_LK_TMR, ETHER_IOW#, ETHER_IOR#, ETHER_T_00, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0 V_. J0 P.0/TLK P./T0 P./T P./T P./SMLK P./T0 P./T P./T 0 V P.0/T0 P./T P./T P./T P./T P./T P./T P./TLK 0 V ON0 P P P P TP RE TP RE TP LK TP LK V P TP ORNGE nalog & Mechanical Size ocument Number Rev MSP0x_LX ate: Saturday, June, 00 Sheet of
V_ V_. 0 0.u 0.u R. L 0uH 0u.u R Low Pass ilter for Power Supply ecoupling 0u.u.u.u 0.u 0.u 0.u 0.u 0.u 0.u L 0uH 0.u 0.u _ ulk ecoupling Size ocument Number Rev MSP0x_LX ate: Saturday, June, 00 Sheet of