References Digital Electronics I Katz, R.H. (2004). Contemporary logic design. Benjamin/Cummings. Hayes, J.P. (1993). Introduction to digital logic design. Addison-Wesley. Horowitz, P. & Hill, W. (1989). The art of electronics. Cambridge University Press. J. & Hayes-Gill, B. (1998). Introduction to digital electronics. Butterworth-Heinemann. Practical references http://www.play-hookey.com/digital/ http://en.wikipedia.org/wiki/digital_circuit http://www.ee.ic.ac.uk/hp/staff/dmb/courses/dig2/dig2.htm
The nature of the p-n junction is that it will conduct current in the forward direction but not in the reverse direction.
From Analog to Digital : TTL, xmos TTL The transistor-transistor-logic (TTL) family was developed in the use of transistor switches for logical operations and defines the binary values as 0 V to 0.8 V = logic 0 2 V to 5 V = logic 1 TTL are inexpensive, but draw a lot of power and must be supplied with +5 volts. Individual gates may draw 3 to 4 ma. The low power Schottky versions draw only 20% of the power, but are more expensive. CMOS The complementary metal oxide semiconductor family (CMOS) has equivalents to most of the TTL chips. CMOS chips are much lower in power requirements (drawing about 1 ma) and operate with a wide range of supply voltages (typically 3 to 18 volts). A drawback is extreme sensitivity to static electricity - they must be carefully protected from static discharges. NMOS and PMOS P- and N-channel Metal Oxide Semiconductors (PMOS and NMOS) offer the advantage of higher component density than TTL chips. They are sensitive to damage from electrical discharge.
npn pnp
7404
TTL logic levels: making the digital (standard TTL) VOH Min = Output voltage high minimum with up to 0.4 ma load. A good chip is guaranteed to output a minimum of 2.4 V logic high up to 0.4 ma VOL Max = Output voltage low maximum with up to 16 ma load. A good chip is guaranteed to output a maximum of 0.4 volts up to 16 ma VIH Min = Input voltage high minimum 2.0 V. A good chip will recognize 2.0 V or greater as a logic high and draw no more than 0.04 ma input current. VIL Min = Input voltage low maximum 0.8 V. A good chip will recognize 0.8 V or less as a logic low and draw no more than 1.6 ma input current.
Binary number system -> 0,1 0 0 10 1010 1 11 1011 10 12 1100 11 13 1101 100 14 1110 101 15 1111 110 16 10000 111 1000 4+5 = 100+101 = 1001 11 1001
The Mathematics of Boolean Algebra (Stanford Encyclopedia of Philosophy - plato.stanford.edu/entries/boolalg-math) Boolean algebra is the algebra of two-valued logic with only sentential connectives, or equivalently of algebras of sets under union and complementation. The rigorous concept is that of a certain kind of algebra, analogous to the mathematical notion of a group. This concept has roots and applications in logic (Lindenbaum-Tarski algebras and model theory), set theory (fields of sets), topology (totally disconnected compact Hausdorff spaces), foundations of set theory (Boolean-valued models), measure theory (measure algebras), functional analysis (algebras of projections), and ring theory (Boolean rings). The study of Boolean algebras has several aspects: structure theory, model theory of Boolean algebras, decidability and undecidability questions for the class of Boolean algebras, and the indicated applications. x + (x y) = x x (x + y) = x x + ( x) = 1 x ( x) = 0
Binary functions of two variables: 3 operations on two variables, ( blank and, or,! not) Null 0 A not or B!(A B) A and B AB A exclusive nor B AB (!A)(!B) A and not B A(!B) not B!B A A A or not B A!B not A and B (!A)B not A!A B B not A or B!A B A exclusive or B A(!B) (!A)B not A and B (!A)B A or B A B identity 1
Boolean Algebra Theorems: ( blank and, or,! not) ABC = (AB)C = A(BC) A B C = A (B C) = (A B) C associative property AB = BA A B = B A commutative property A (!A) = 0 A =!(!A) A!A = 1 single value theorems A AB = A A (!A)B = A B two variable theorems A 1 = 1 A 0 = A A0 = 0 identity operations
Bitwise Operations Bitwise AND and OR c = a & b where ci = 1 if ai = 1 and bi = 1, i [0,7] d = a b where dj = 1 if aj = 1 or bj = 1, j [0, 7] example Position 7 6 5 4 3 2 1 0 Value 128 64 32 16 8 4 2 1 a 1 0 0 0 0 1 1 b 1 1 0 0 0 0 1 c (a & b) 1 0 0 0 0 0 1 d (a b) 1 1 0 0 0 1 1
Bitwise Operations Bit Shifting Bit shifting (left or right) is simply pushing all of the bits in a byte left or right, filling the gaps made at one end with zeros, kicking the high bits off the other end. Shifting left is equivalent to multiplying by a power of 2 as long as only zeros are discarded from the top. Shifting right is equivalent to dividing by a power of 2, discarding any remainder. a << 3 == a 2 3 4-4 ; a >> 4 == a 2 == a 2 example Position Value 7 6 5 4 3 2 1 0 128 64 32 16 8 4 2 1 a 1 0 0 0 0 1 1 0 a << 1 0 0 0 0 1 1 0 0 a >> 1 0 1 0 0 0 0 1 1
Bitwise Operations Masking To retrieve the value of one bit, all we have to do is create a mask that hides all of the other bits. The solution is, to get the value V of bit i from byte a: V = ((a & (1 << i))!= 0) example Position Value 7 6 5 4 3 2 1 0 128 64 32 16 8 4 2 1 a 1 0 0 0 0 1 1 0 1 << 2 0 0 0 0 0 1 0 0 a & (1 << 2) 0 0 0 0 0 1 0 0 1 << 3 0 0 0 0 1 0 0 0 a & (1 << 3) 0 0 0 0 0 0 0 0
Bitwise Operations Setting and Unsetting Bits To set a bit (change its value to 1), we have to find an operation which will leave a '1' where we want and leave other bits unchanged. To set bit i in byte a, leaving the result as a new : a new = a (1 << i) example Position Value 7 6 5 4 3 2 1 0 128 64 32 16 8 4 2 1 a 1 0 0 0 0 1 1 0 1 << 3 0 0 0 0 1 0 0 0 a (1 << 3) 1 0 0 0 1 1 1 0 ~(1 << 2) 1 1 1 1 1 0 1 1 a & ~(1 << 2) 1 0 0 0 0 0 1 0
Combinational Logic Gates
Combinational Logic Gates with Truth Tables
DeMorgan s Theorem Any logical binary expression remains unchanged if one 1. Changes all variables to their complements. 2. Changes all AND operations to ORs. 3. Changes all OR operations to ANDs. 4. Takes the complement of the entire expression.
Sequential Logic Gates S/R flip-flop Clocked S/R flip-flop state and next state table S R Q (now) Q+ (next) 0 0 0 Q 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 x 1 1 1 x characteristic equation: Q+ = S + R Q
Sequential Logic Gates state and next state table clocked JK flip flop J K Q (now) Q+ (next) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 characteristic equation: Q+ = K Q + JQ
Sequential Logic Gates state and next state table clocked D flip-flop D Q (now) Q+ (next) 0 0 0 0 1 0 1 0 1 1 1 1 characteristic equation: Q+ = D whatever D is will be Q+ (the next Q) -> D flip flop is a hold circuit (a latch)
Sequential Logic Gates, applied: timers 555 timer (control voltage) Vcc Threshold input Application circuit trigger output reset input ground See: http://www.play-hookey.com/digital/timer_555.html for more details
The three resistors in the voltage divider all have the same value so the comparator reference voltages are 1/3 and 2/3 of the supply voltage, The internal flip-flop changes state when the trigger input at pin 2 is pulled down below +VCC/3. When this occurs, the output (pin 3) changes state to +VCC and the discharge transistor (pin 7) is turned off. If the threshold input (pin 6) is now raised above (2/3)+VCC, the output will return to ground and the discharge transistor will be turned on again. When the threshold input returns to ground, the IC will remain in this state, which was the original state. One way to allow the threshold voltage (pin 6) to gradually rise to (2/3)+VCC is to connect it to a capacitor being allowed to charge through a resistor. In this one can adjust the R and C values for almost any time interval. The 555 can either produce a single pulse when triggered, or it can produce a continuous pulse train (as long as it remains powered).
Multiplexers many inputs, one output two inputs X0, X1: data A, B: addressing lines 1 addressing line selects from 2 data sources 2 addressing lines select from 4 data source -> 8 lines select from 2^8 data sources four inputs -> n lines select from 2^n data sources -> used to combine multiple digital signals onto a single transmission line Requirement: frequency of the slowest data line must be at least twice the frequency of the address line switching
Demultiplexers one input, many outputs two outputs 2 outputs need one address line 4 outputs require 2 address lines -> 2^n outputs require n address lines four outputs These circuits take in a n-bit binary number and produce an output on one of the 2^n output lines. The output line is chosen by the current state of the address lines.
NAND Gate IC7400