ENGR400 Test S Fall 005 ENGR400 Fall 005 Test S Name solution Section uestion (5 points) uestion (5 points) uestion (5 points) uestion 4 (5 points) Total (00 points): Please do not write on the crib sheets. On all questions: SHOW ALL WORK. BEGIN WITH FORMULAS, THEN SUBSTITUTE VALUES AND UNITS. No credit will be given for numbers that appear without justification. of
ENGR400 Test S Fall 005 uestion Astable Multivibrator (5 points) The multivibrator above was built with the 555 timer chip shown. In the diagram, Vs is the source voltage, Vc is the voltage across the capacitor C, and V D is the voltage at the discharge pin of the timer. You are given the following component values: Test A: R = 4.7k ohms R = 6.8k ohms C = 0.68µF Vs = 6V Test B: R =.k ohms R = 4.7k ohms C =.5µF Vs = V Test C: R = 6.8k ohms R = 8.6k ohms C = 0.47µF Vs = 5V ) Calculate the on time and off time of the multivibrator. (4 pt) T = 0.69( R + R) C T = 0.69(4.7K+6.8K)(0.68µ) = 5.4ms T = 0.69( R) C T = 0.69(6.8k)(0.68µ) =.0ms Test A: Ton = 5.4ms Toff =.0ms Test B: Ton = 7.7ms Toff = 4.89ms Test C: Ton = 5.0ms Toff =.80ms ) Calculate the frequency and period of the multivibrator. (4 pt) T=Ton + Toff f=/t T=5.4m+.0m = 8.6ms f=/8.6m=6hz Test A: T = 8.6ms f = 6 Hz Test B: T =.06ms f = 8.9 Hz Test C: T = 7.8ms f = 8 Hz ) Calculate the duty cycle of the multivibrator. ( pt) DC = 00*Ton/T DC=00*5.4m/8.6m=6.9% Test A: DC = 6.9% Test B: DC = 59.5% Test C: DC = 64.% of
ENGR400 Test S Fall 005 4) In theory, what are the maximum and minimum voltage across the capacitor, Vc? ( pt) Vmin = Vs/ Vmax = *Vs/ Vmin=6/=V Vmax = *6/ = 4V Test A: Vmin = V Vmax = 4V Test B: Vmin = 4V Vmax = 8V Test C: Vmin =.67V Vmax =.V 5) When the transistor inside the 555 timer is closed, the output at pin 7 is grounded, and therefore, equal to zero. When the transistor is open, the output at pin 7 can be found using the voltage divider formed by R and R. Find an expression for the voltage at pin 7 (when pin 7 is not grounded) in terms of the voltage across the capacitor, Vc, the source voltage, Vs, and the two resistors R and R. [Hint: Recall how you calculate the voltage at the non-inverting input for a Schmitt trigger.] Do not substitute values. ( pt) R V D = + R + R ( VS VC ) VC This can be simplified further, but it is not necessary. 6) Use the equation in 5) to find the maximum and minimum voltage at pin 7 when the transistor is open. ( pt) V Dlow = [6.8k/(6.8k+4.7k)](6-) + = 4.6V V Dhigh = [6.8k/(6.8k+4.7k)](6-4) + 4 = 5.8V Test A: V Dlow = 4.6V V Dhigh = 5.8V Test B: V Dlow = 9.44V V Dhigh = 0.7V Test C: V Dlow =.5V V Dhigh = 4.7V 7) On the graph below, identify the outputs at pin (, 6), 7 and of the multivibrator. Identify both parts of the cycle for each. (6 pt) This shows the basic shape of the signals. The image on each test was different. of
ENGR400 Test S Fall 005 uestion Combinational Logic Circuits (5 points) Test A and B: ) You are given the following circuit A UA 74 C UA 740 F UA 7486 E B UA 7400 D U5A 7408 G a) Fill out the truth table below (0 pt) A B C D E F G 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b) What gate is the output at G equivalent to (circle one)? ( pt) AND NAND OR NOR XOR XNOR NOT ) Fill out the truth table below to prove the following relationship: (4 pt) ( A B) + ( A B) + ( A B) then = A B if = + A B A B A B A B A B A+B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 of
ENGR400 Test S Fall 005 Test C: ) You are given the following circuit A U5A 7408 C UA 740 F UA E 7400 B UA 7486 D U5A 7408 G a) Fill out the truth table below (0 pt) A B C D E F G 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b) What gate is the output at G equivalent to (circle one)? ( pt) AND NAND OR NOR XOR XNOR NOT ) Fill out the truth table below to prove the following relationship: (4 pt) if = ( A + B) ( A + B) ( A + B) then = A B A B A B A + B A + B A + B A B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 of
ENGR400 Test S Fall 005 uestion Sequential Logic Gates (5 points) uiz A and B: You are given the following circuit DSTM provides the clock for the counter. DSTM provides the clock to the two flip flops. DSTM provides an initial reset pulse to all the sequential chips. Therefore, you can assume that A, B, C, D,, and are all initially low. DSTM UA UA A A 4 B 5 C 6 D CLR 749 U4A 4 J K CLR U6A 7407 DSTM UA U5A 4 J K CLR U7A 7407 ) Sketch the timing trace for each of the signals shown. (4 pt) 6 of
ENGR400 Test S Fall 005 uiz C: You are given the following circuit DSTM provides the clock for the counter. DSTM provides the clock to the two flip flops. DSTM provides an initial reset pulse to all the sequential chips. Therefore, you can assume that A, B, C, D,, and are all initially low. DSTM UA UA A A 4 B 5 C 6 D CLR 749 U4A 4 J K CLR U6A 7407 DSTM UA U5A 4 J K CLR U7A 7407 ) Sketch the timing trace for each of the signals shown. (4 pt) 7 of
ENGR400 Test S Fall 005 ) We take the output of this circuit and use it as the input to the transistor circuit shown below: uiz A uiz B and C Fill in the following table for all possible values of and. (4 pt) uiz A uiz B and C Vout 0V 0V 5V 0V 5V 5V 5V 0V 5V 5V 5V 0V Vout 0V 0V 5V 0V 5V 0V 5V 0V 0V 5V 5V 0V ) What are the values of the signals at, and Vout after 8.9 milliseconds? ( pt) All Tests: : 0V : 0V Vout: 5V 8 of
ENGR400 Test S Fall 005 uiz A and B 4) IC chips have a standard numbering convention that you should now know. Label pins #-8 on the IC below. (HINT: It doesn t matter what the chip s function is just label #, #, ). ( pt) 5) Like op-amps, IC chips need two power connections in order to function. Label the power (Vcc) and ground pins on the IC chip pictured below with the appropriate voltage values. ( pt) 6) The chip contains more than one inverter. How many does it contain? ( pt) 6 7) You ve primarily used two types of capacitors in the studio: electrolytic and ceramic disc, each shown below: Electrolytic: Ceramic Disc: Which one is polarized (e.g. has a + and lead) (circle one)? ( pt) neither electrolytic ceramic disc both 9 of
ENGR400 Test S Fall 005 uiz C 4) IC chips have a standard numbering convention that you should now know. Label pins #-8 on the IC below. (HINT: It doesn t matter what the chip s function is just label #, #, ). ( pt) 5) We ve talked about the use of bypass capacitors when working with digital logic chips. Which answer below best describes where they should be located and why we use them? ( pt) a. Place one or more between digital logic inputs and ground to smooth the sharp transients of digital switching signals that could otherwise corrupt proper chip operation. b. Place one or more in series with logic power (Vcc) where it enters the protoboard to filter noise coming from the power supply. c. Place one or more in parallel with Vcc and ground at each chip to filter noise. d. Place only one between Vcc and high speed logic chip outputs to suppress output oscillation (e.g. ringing). 6) What was the recommended range of bypass capacitor values given for the TTL logic family used in the studio? (circle one) ( pt) a) 0.pF 0.5pF b) 0.0nF 0.nF c) 0.0uF 0.uF d) 0.uF 0uF e) 0uF 00uF f) I don t know because I slept through that lecture. 7) You ve primarily used two types of capacitors in the studio: electrolytic and ceramic disc, each shown below: Electrolytic: Ceramic Disc: Which one is polarized (e.g. has a + and lead) (circle one)? ( pt) neither electrolytic ceramic disc both 0 of
ENGR400 Test S Fall 005 uestion 4 Switching Circuits (5 points) _ + _ + uiz A: V=4V V= -0V V4=V V5=8V R4=0k R5=k uiz B: V=6V V= -8V V4=V V5=0V R4=0k R5=k uiz C: V=5V V= -7V V4=V V5=9V R4=40k R5=k ) In the circuit shown, circle the model of a Schmitt trigger. ( pt) ) What is the reference voltage of the Schmitt trigger model? ( pt) Test A: Vref = V Test B: Vref = V Test C: Vref=V ) If the op-amp is putting out its maximum voltage at C, what is the voltage at point B, the non-inverting input to the op-amp? ( pt) R v + = vout Vref + V R R ( ) + ref v+ = [k/(k+0k)](8-) + =.75V Test A: v+ =.8V Test B: v+ =.V Test C: v+ =.V 4) If the op-amp is putting out is minimum voltage at point C, what is the voltage at point B, the non-inverting input to the op-amp? ( pt) R v + = vout Vref + V R R ( ) + ref v+ = [k/(k+0k)](-0 -) + =.5V Test A: v+ =.5V Test B: v+ =.48V Test C: v+ =.57V of
ENGR400 Test S Fall 005 5) On the following plot, the input at point A is shown. a) Mark the upper and lower thresholds of the hysteresis ( pt), and b) sketch and label the output at points B, C, D and E for the input shown. ( pt) Many of the signals will overlap. Use the PSpice labeling convention to identify the signals by drawing unique symbols on important parts of each trace. Note that the input has a little box. Use the following: B = + C = D = Ο and E =. This plot shows the basic shape of the signals for all three tests. Specific high and low values are given below. Test A: Signals change when input rises above.8v or falls below.5v Signal B toggles between.5 and.8 volts. (H-L-H-L-H) Signal C toggles between +8V and -0V (H-L-H-L-H) Test B: Signals change when input rises above.v or falls below.48v Signal B toggles between.48 and. volts. (H-L-H-L-H) Signal C toggles between +0V and -8V (H-L-H-L-H) Test C: Signals change when input rises above.v or falls below.57v Signal B toggles between.57 and. volts. (H-L-H-L-H) Signal C toggles between +9V and -7V (H-L-H-L-H) All Tests: Signal D toggles between 0V and some voltage less than 5V (L-H-L-H-L) (You do not know enough about diodes to know the exact voltage, so we accepted anything in this range that was recognizable as not zero.) Signal E is constant at 5V 8) Are the LEDs on or off at the following times ( points)? time LED LED 0.ms ON ON 0.8ms OFF ON.ms ON ON of