Transmission Lines Author: Michael Leddige 1
Contents PCB Transmission line structures Equivalent Circuits and Key Parameters Lossless Transmission Line Analysis Driving Reflections Systems Reactive Elements Losses Frequency Content of Digital Signals Physical Effects Impacts on Performance 2
PC Transmission Lines Integrated Circuit Stripline Microstrip T PCB substrate Cross section view taken here Copper Trace W Cross Section of Above PCB Via FR4 Dielectric Signal (microstrip) T Copper Plane W Ground/Power Signal (stripline) Signal (stripline) Ground/Power Signal (microstrip) 3
PCB Transmission Line Structures Parallel plate Microstrip + - + - Stripline Coplanar - + - - + - 4
Fields H E The signal is a wave propagating between the conductors 5
Transmission Line Characteristics Characteristic Impedance (Z 0 ) [Ω] Propagation constant (g) [m -1 ] Propagation delay per unit length (t p ) [ps/m] or velocity (v p ) [in/ps] Per-unit-length capacitance (C) [pf/m] Per-unit-length inductance (L) [nh/m] Per-unit-length (Series) resistance (R) [Ω/m] Per-unit-length (Parallel) conductance (G) [S/m] R, L, G & C are frequency dependent Rdz Ldz Equivalent circuit + V(s,z) - I(s) Cdz Gdz + V(s,z+dz) - 6
Wave Propagation on a Transmission Line Equivalent circuit + V(s,z) - I(s) Rdz Ldz Cdz Gdz + V(s,z+dz) - Wave equation 2 v z 2 = LC 2 v v + RG + LC t2 t + RGv Propagation tr degradation Attenuation 2 i z 2 = LC 2 i i + RG + LC t2 t + RGi General Solution v z, ω = v + z e jzωγt + v z e jzωγt i z, ω = 1 Z 0 v + z e jzωγt + v z e jzωγt 7
Transmission Line Parameters Equivalent circuit + V(s,z) - I(s) v z, ω = v + z e jzγωt + v z e jzγωt Rdz Ldz Cdz Gdz + V(s,z+dz) - R, L, G and C are frequency dependent. Characteristic Impedance Z 0 = V f I f = R + jωl G + jωc Propagation Constant γ = R + jωl G + jωc Propagation Velocity γ = α + jβ v p = 2πf β attenuation phase 8
Lossless Transmission Lines Equivalent circuit + V(s,z) - I(s) v z, ω = v + z e jzβωt + v z e jzβωt Ldz Cdz + V(s,z+dz) - R=G=0, L & C are frequency independent. Characteristic Impedance Z 0 = V f I f = jωl jωc = L C Propagation Constant γ = jωl jωc = jω LC α = 0 β = ω LC attenuation phase Propagation Velocity v p = ω β = 1 LC 9
Driving a T-Line Goal: Determine the initial signal driven onto the line. R S Z 0 V S t r We can treat the circuit as a voltage divider. R S This simple model only works if there is no steady state current. V S t r Z 0 We can calculate for circuits with steady state current, too. 10
Driving a T-Line Determine the initial signal driven onto the line for V S =2V, R S =30W, Z 0 =50W. R S Z 0 V S t r V = Z 0 R S +Z 0 V S = 50 30+50 2V = 1.25V 11
Reflections on Transmission Lines v i v r z Z 01 Z 02 v t i i -i r i t i Reflection V V r i Z Z 02 02 Z Z 01 01 V I V r r 01 r I = V Ii Z01 Vi Vi Z V Transmission Vt V i I t i r 1 V V I I I i Ii I I 1 Applies to impedance discontinuities from any source. e.g. layer transition, termination, parasitics 12
Reflections on Transmission Lines Example: Z 01 =50W, Z 02 =200W, V i =1V v i v t v r z Z 01 Z 02 I i V Z i 01 1V 50W 20mA i i -i r i t i V I r r Z Z I V 02 02 i Z Z 01 01 V i 0.620mA 200W 50W (1V ) 200W 50W 12mA 0.6V V t 1 Z Z 02 02 Z Z 01 01 V i 1 200W 50W (1V ) 200W 50W 1.6V I t I i I r 20mA 12mA 32mA 13
Example: Propagation V 2I I 2V R S = Z 0 Z 0 z 0 v =0 z l v = V I t 0 V l z I l z V I t 0 < t 1 < l/v p 2V V l z 2I I l z V I l/v p < t 2 l z l z 14
Example: Waveforms R S = Z 0 Z 0 z l 2V z 0 2V z = 0 z = l 2I z = 0 z = l V I 0 0 l/v p 2l/v p 0 0 2l/v p 2l/v p 15
Solving Simple Transmission Line Problems Calculate initial and final steady state voltages & currents. Calculate the reflection coefficients at the source (transmitter) and load (receiver). Calculate the amplitude of the voltage and current waves launched by the transmitter. Calculate the amplitude of the reflected waves at the load. Return to the source and calculate the reflected waves. Repeat until the reflected waves fall below your threshold. Sum the waves (superposition) to get the waveforms at the source and load. 16
Example Analysis Lattice Diagram 0 t d t d t d t d t d t d t d t d V S = 5.0V V(z=0) I(z=0) V(z=l) I(z=l) 0.000V 0.00mA 3.333V 66.7mA 4.074V 40.4mA 3.992V 40.4mA 4.000V 40.0mA 0 l (z=0) = 1/3 3.333V 66.7mA -0.370V -7.41mA 0.041V 0.82mA -0.005V -0.09mA 1.111V 22.2mA -0.123V -2.47mA 0.013V -0.002V -0.27mA -0.03mA <0.001V (z=l) = 1/3 z 0.000V 0.00mA 4.444V 44.5mA 3.951V 39.6mA 4.005V 40.1mA 4.000V 40.0mA R S = 25W z = 0 I Features Z 0 = 50W, t D = Z3 0 ns = 50W Position: horizontal axis Time: vertical axis Reflection coefficients at ends Waves on diagonal vectors Voltages & currents accumulate via superposition z = l R T = 100W t d t <0.01mA t 17
Capacitive Discontinuities Step Response V S (t) R S z = 0 Z 0, l, v p z = l C L tt dl 2Z0 Z0 V l, t t dl VS 1 e Z0 RS C L 0 t=0 VS V S (t) = V S u(t) t Z 0 C L Delay V Vr L 0 V i C Z t r Reflection R S V S (t) z = 0 Z 0, l 1, v p Z 0, l, v p C L Z 0, l 2, v p t Z0CL 2 Delay V CLZ 2t r 0 Reflection 18
Inductive Discontinuities Step Response V S (t) R S z = 0 Z 0, l, v p z = l tt dl 2Z0 Z0 V l, t t dl VS 1 e Z0 RS C L L t L L 2Z 0 Delay V V r i L 2Z L 0 t r V Reflection R S Z 0, l, v p Z 0, l, v p V S (t) t L L Z 0 Delay V r LLVi Z t 0 r Reflection 19
To Explore Further Hall and Heck give more in-depth treatments for topics relating to lossless transmission line systems: Simple linear models for I/O transmitters and receivers Chapter 11 Lattice diagrams provide a simple tool for analyzing lossless transmission line problems pp. 118-129 Bergeron diagrams provide an alternative method that accounts for steady state currents pp. 465-475 20
Frequency Content of Digital Signals Digital signals have broadband frequency content. Losses & their impacts on high performance signals are frequency dependent. 21
Lossy Line Characteristics Equivalent circuit + V(s,z) - I(s) Rdz Ldz Cdz Gdz + V(s,z+dz) - R, L, G and C are frequency dependent. Propagation Constant Propagation Velocity γ = R + jωl G + jωc = α + jβ v p = 2πf β v z, ω, t = v + z e αz e jβz e jωt + v z e αz e jβz e jωt 22
Transmission Line Losses Input Signal to Transmission Line Output Signal from Lossless Transmission Line Attenuation (a) Propagation Delay Output Signal from Lossy Transmission Line Rise Time Degradation (a, b) 23
Frequency Dependent Loss f Dependent PCB Loss 12 trace PCB Loss @ 5GHz Transmission Line losses depend upon frequency and length. Channel loss includes parasitic I/O capacitance 24
Loss/Margin Relationship 1000mV Transmitter 4 PCB 780mV -5.3dB 533mV/87ps 600mV -9.6dB 204mV/60ps 8 PCB 12 PCB 450mV -13.5dB -55mV 25
Bitwise Simulation (1000 bits) 4 PCB 8 PCB 12 PCB 26
Loss/Margin Relationship PDA Eye closes completely just beyond -12dB loss @ Nyquist frequency (5GHz). 27
To Explore Further Hall and Heck give more in-depth treatments for topics relating to lossy transmission line systems: Skin effect, surface roughness, causality,and the relationship between frequency dependent L and R. Chapter 5 Dielectric losses, causality, the relationship between er and tand, the relationship between C and G. Chapter 6 Mathematical requirements for physical channels: Chapter 8 Modeling of transmission lines with losses Chapter 10 28
Background Connectors, packages, and vias are part of every major IA high speed interface. Understanding their performance and modeling is essential to successful interconnect design. Graphics Connector CPU Socket Chipset Package Memory Connectors 29
Agenda Vias Definition: what are they and why do we need them? Electrical models of via parasitics Connectors Definition: what are they and why do we need them? Electrical effects Packages Inductance SLEM-style approximation Power and ground pins Design considerations (tradeoffs, rules of thumb) Definition: what they are and why we need them Common types (e.g. flip-chip, bondwire) and history Creating package models Effect of a package on signal integrity Design considerations 30
Vias Vertical connections between layers made by drilling a small hole and filling it with conductive material. Vias connect metal layers on Silicon chips, within packages, and on printed circuit boards. vias capacitor chip chip pkg PCB 31
Via Functions Vias are typically used to Connect metal planes of the same potential (e.g., all ground planes conductively attached) Carry a signal from a trace on one layer to another Connect components (such as a capacitor) to a signal trace or a voltage plane. Provide probe points for testing production boards. 32
Via Structures Barrel: conductive cylinder filling the drilled hole Pad: connects the barrel to the component/plane/trace Antipad: clearance hole between via and no-connect metal layer Trace connected to pad on layer 1. Pad Barrel / Drill Via pad does not contact plane in this case; void is called the anti-pad 33
PCB Via Types Through Hole Via Blind Via Stepped Via Buried Via Stacked Via Filled or not 34
Via Cross-sections Laser generated via Stacked via Through hole via 35
Via Modeling As long as the delay through the via is <1/10 of the signal edge, we can model it as a lumped circuit. L barrel To red t-line C pad C pad D 1 Via pad diameter D 2 Via anti-pad diameter T PCB thickness C pad in pf h via length d barrel diameter L barrel in nh Via delay 36
Resonance Due Via Stubs Via drill diameter: 28 mils Via pad diameter: 42 mils Via anti-pad diameter: 58 mils Board thickness: 62 mils C=0.4 pf, L=0.7 nh L barrel C pad C pad 0-20 db(vin) -40-60 -80-100 m2 freq=5.033ghz db(vin)=-94.045 m2 0 2 4 6 8 10 freq, GHz f R = 9.5GHz delay ~ 17ps 37
Agenda Packages
Packages 39
Key Features (Cross-section view) Build-Up Core Build-Up Eutectic Solder Ball Grid Array (BGA) Chip Capacitor Integrated Circuit (Die) micro-via (uvia) Plated Through Hole (PTH) Pin Grid Array (BGA) Solder Resist (SR) Copper Layer Insulator (Dielectric) 40
Package Routing Small T-lines route from bond pad of package to the board attachment (e.g., pin or solder ball) High speed design requires controlled impedance A miniature PCB: layers, power/ground planes. Layers have well-defined impedance & routing rules that consider effects like crosstalk. 41
Package to PCB Attach Types Lead frame: metal frame connects wire bonds to PCB PGA: array of pins that stick out of the package BGA: array of solder balls that attach to board LGA: array of pads that attach to board LGA & PGA are socketable to provide Interchangeability (e.g., memory sticks, CPU upgrades) for OEM inventory control, the impact of tax and duty, and manufacturing flexibility. 42
Modeling of a Package with Socket Traces Via Transmission Line Sectioned Pi models Connector Lumped element sections Pwr/Gnd plane Ensure significant return path effects are modeled 43
Package Modeling Package Traces: coupling and x- sections Top-view of pkg D C Bondwire side-view and x-sections D 1 2 3 B A A H A B Die C B B H A 44
Agenda Connectors
Card Edge Connectors Connector is mounted on base board (PTH, PF, or SMT) Gold fingers locate near edge of module Module slide into the connector to establish connection to base board Example: PCIe; UDIMM, SODIMM, MXM PCIe connector (X4) Mini PCIe connector (X4) DDR3 UDIMM connector DDR3 SODIMM connector 46
Sockets 47
Connector Modeling Connector housing trace Plated Through Hole Connector contact in air & partially in housing Upper piece of contact & add-in card pad 48
Connector Models Series Loop Inductance a 2d a << d Parallel wires a radius of round wire l length d half distance between wires Approximate L between 2 connector loops Parallel loops g loop to loop spacing d half distance between wires l length 2d g 2d 49
Connector Models Capacitance Inductance a 2d a << d Parallel wires a radius of round wire l length d half distance between wires Approximate C between 2 connector loops Parallel loops g loop to loop spacing d half distance between wires l length 2d g 2d 50
Edge Finger Pad Model 28 mils = 711.2 umeters 4.5 mils = 114.3 micrometers 165 mils = 4191 um 28 mils = 711.2 um Comparison of edge finger to connector pin shows that the edge finer capacitance is much larger. The pin capacitance and mutual capacitance between pins are negligible. 51
Connector Model Breakdown Connector housing trace 1.55 pf 3.13 nh 3.13 nh 0.017 pf 1.0 pf Sectioned connector model need to ensure that there is enough sections for your frequency requirements. Is 1/TD of the section less than 1/10 a wavelength of the highest frequency of interest? 52
Multi-Gb/s Modeling: 3D Field Solver-Based PCIe DDR3 UDIMM SATA3 USB3 53