2/9/26 Loic Desin Chapter 4: Optimized Implementation o Loic Functions Introduction The combinin property allows us to replace two minterms that dier in only one variable with a sinle product term that does not include that variable. Combinin property can be used to reduce the number o product terms in SOP Karnauh map provides a systematic way o perormin this optimization m m m 2 m (a) Truth table m m m m 2 m m m 2 m 6 m 4 2 m m m m m m 7 m 5 m 4 (b) Karnauh map m 5 (b) Karnauh map m 6 m 7 (a) Truth table m m m 5 m m 2 m 6 m 4 m 2 m m 7 m 5 m 4 m 8 m 9 m m K-map How to use the K-map to ind a minimum cost implementation? Find as ew as possible and as lare as possible roup o adjacent s that cover all cases where the unction has a value o Lare roup o s: ewer number o variables in the correspondin product term -> ates with ewer number o inputs Fewer number o roups: less AND ates Keep in mind that cost is the number o ates and number o inputs to the ate Size o roups:, 2, 4, 8,.
2/9/26 K-map Adjacent cells: cells that dier only in one variable Cells in let and riht ede o the K-map are adjacent Cells in top and bottom ede o the K-map are adjacent You can visualize the map as bein olded around a cylinder Four corners o the map are adjacent to each other and can orm a roup K-map How to ind out the product term correspondin to a roup? The product term correspondin to a roup must include only those variables that have the same value ( or ) or all the cells in the roup Note: i it helps in ormin bier roups a cell can be used or more than once This is ine since m i =m i +m i = + = + 2 = + = + + 4 = + + or = Five Variable Map = Selection o roups on the K-map may be made more systematic usin implicants. Literal: Each appearance o a variable, either uncomplemented or complemented, in a product term, is called a literal Eample: has three literals. A product term or which a iven unction is equal to is called an implicant. Eample: do the eample on board = + + 2
2/9/26 I the removal o any literal rom an implicant P results in a product term that is not an implicant o the unction, then P is a prime implicant. A collection (set) o implicants that account or all variations or which a iven unction is equal to is called a cover o that unction. Cost o the unction: total number o ates plus total number o all inputs to all ates The cover consistin o prime implicants leads to the lowestcost implementation. How to determine the minimum-cost subset o prime implicants that will cover the unction? I a prime implicant includes a minterm or which = that is not included in any other prime implicant, then it is called an essential prime implicant and must be included in the cover Do the eample on the board Process o indin a minimum-cost circuit:. Generate all prime implicants or the ive unction 2. Find the set o essential prime implicants. I the set o essential prime implicants covers all valuations or which =, then this set is the desired cover o. Otherwise, determine the nonessential prime implicants that should be added to orm a complete minimum-cost cover The choice o nonessential prime implicants to be included in the cover is overned by the cost considerations One approach: arbitrarily select one nonessential prime implicant and include it in the cover, and determine the rest o the cover. Determine another cover, assumin that this prime implicant is not in the cover. Choose the less epensive cover. Do an eample on board Minimization o POS Forms Find the minimum cost SOP implementation o the complement o (look or zeros in the K-map) Apply DeMoran s theorem to obtain the simplest POS realization Do the eample on board Incompletely speciied unctions Functions with undeined outputs or some input combinations are called "incompletely speciied unctions". These "don t care" conditions may be used to advantae to provide urther simpliication o the unction The desiner can assume that the unction value o don t care conditions is or whichever is more useul. To indicate don t-care conditions on the K-map, they are normally marked as d
2/9/26 ( Incompletely speciied unctions,.., 4) m(2,4,5,6,) D(2,,4,5) Incompletely speciied unctions (,.., ) m(2, 4,5,6,) D(2,,4,5) 4 2 4 2 4 ( )( )( ) 2 4 2 2 4 ( )( ) 2 4 d d d d + d d + d d (a) SOP implementation (b) POS implementation Multilevel Synthesis Minimum cost sum-o-products or product-o-sums realizations have two levels (staes) o ates Sum-o-product: irst level AND ates connected to a second level OR ate Product-o-sum: irst level OR ates connected to a second level AND ate As the number o inputs increases a two-level circuit may result in an-in problem Whether or not this is an issue depends on the type o technoloy used to implement the circuit (, 2,..., 7 ) 6 4 5 6 2 7 2 4 5 7 Multi-level synthesis A C C E To solve the an-in problem should be epressed in a orm that has more than two levels Multi-level loic epression Two important techniques or synthesis o multi-level circuits:. Factorin 2. Functional decomposition B A B D D E 4
2/9/26 Factorin Factorin (,,..., ) 2 7 6 4 5 6 2 7 2 4 5 7 ( ) ( ) 6 4 5 2 7 4 5 ( )( ) 6 2 7 4 5 A 6 C C E B 7 A B D D E Factorin Factorin 2 4 5 6 ( ) 5 4 6 2 5 2 4 5 6 2 2 4 5 6 2 4 5 6 ( ) 4 6 2 5 2 5 67 inputs Functional decomposition Compleity o a loic circuit can oten be reduced by decomposin a two-level circuit into sub-circuits where one or more sub-circuit implements unctions that may be used in several places to construct the inal circuit 2 2 2 4 2 4 ( ) ( ) 2 2 2 2 4 2 2 2 2 4 5
2/9/26 Functional decomposition Decoders Decoder: decodes encoded inormation A binary decoder is a loic circuit with n inputs and 2 n outputs Only one output is asserted at a time (correspondin to one valuation o inputs) Enable: En= none o the decoder outputs is asserted h n inputs Enable w w n En y y 2 n 2 n outputs Binary coded decimal (BCD) Each diit in a decimal number is represented by its binary orm Since there are diits we need 4 bits per diit w w w 2 w a b c d e e a d b c (a) Code converter (b) 7-sement display w w 2 w w a b c d e (c) Truth table Fiure 6.25. A BCD-to-7-sement display code converter. Multi-level NAND and NOR Circuits Multi-level NAND and NOR Circuits (a) Circuit with AND and OR ates 6
2/9/26 Multi-level NAND and NOR Circuits (c) NAND-ate circuit Analysis o Multi-level Circuits In order to derive the unction o a multi-level circuit, we have to trace the circuit either by trackin the inputs and workin towards the outputs or the other way. Findin the unction o intermediate points is helpul. (b) NOR-ate circuit Analysis o Multi-level Circuits Analysis o Multi-level Circuits P P 9 P 2 P P 4 P 5 P 7 2 P P 6 P 8 P, P 2 4 P P P 4 2 P P 5 4 P P P 6 4 5 P P 7 P P 8 6 P PP 9 6 P PP 7 8 P P PP PP 9 6 7 8 ( )( P P) PP 2 5 4 5 6 ( )( P P) P P 2 5 2 4 2 5 4 5 ( )( ) ( )( ) 2 5 4 4 2 5 4 4 4 4 2 4 2 4 5 4 5 4 2 5 4 2 5 4 7
2/9/26 Analysis o Multi-level Circuits P P 2 P 4 P 2 P P P 2 P 4 4 P P P 4 2 P P P P P 4 5 4 5 2 5 ( P ) 4 5 ( ) 2 4 5 5 2 5 5 4 5 8