VLSI. Faculty. Srikanth

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J.B. Institute of Engineering & Technology Department of CSE COURSE FILE VLSI Faculty Srikanth

J.B. Institute of Engineering & Technology Department of CSE SYLLABUS Subject Name: VLSI Subject Code: VLSI Class : IV B.Tech. I Semester ECE Faculty Name: Srikanth Sl.No Unit # Details of the unit MOS, PMOS, NMOS, CMOS & BiCMOS technologies- Oxidation, Lithography, Diffusion, Ion Introduction to IC Technology implantation, Metallization, Encapsulation, Probe testing, Integrated Resistors and Capacitors 2 Basic Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships, MOS transistor BASIC ELECTRICAL PROPERTIES threshold Voltage, gm, gds, figure of merit. Pass transistor, NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters. 3 4 VLSI CIRCUIT DESIGN PROCESSES GATE LEVEL DESIGN VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 um CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits, Limitations of Scaling. Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Basic circuit concepts, Sheet Resistance RS and its concept to MOS, Area Capacitance Units, Calculations - Delays, Driving large Capacitive Loads, Wiring Capacitances, Fan-in and fan-out, Choice of layers 5 SUBSYSTEM DESIGN Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity generators, Comparators, Zero/One Detectors, Counters, High Density Memory Elements. 6 SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN 7 PLAs, FPGAs, CPLDs, Standard Cells, Programmable Array Logic, Design Approach. VHDL SYNTHESIS VHDL Synthesis, Circuit Design Flow, Circuit Synthesis, Simulation, Layout, Design capture tools, Design Verification Tools, Test Principles. 8 CMOS Testing, Need for testing, Test Principles,

CMOS TESTING Design Strategies for test, Chip level Test Techniques, System-level Test Techniques, Layout Design for improved Testability. Text Book: TB.. Essentials of VLSI circuits and systems Kamran Eshraghian, Eshraghian Dougles and A. Pucknell, PHI, 2005 Edition. TB2. 2. Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education, 999 References: RB.. VLSI DESIGN by LAL KISHORE. RB2. 2. CMOS VLSI DESIGN by Wayne wolf. J.B. Institute of Engineering & Technology Department of CSE SUBJECT PLAN Subject Name: VLSI Subject Code: VLSI Class : IV-B.Tech-Isem-IT Faculty Name: Srikanth Unit # Topics Total No of Lessons INTRODUCTION 08 2 08 BASIC ELECTRICAL PROPERTIES 3 VLSI CIRCUIT DESIGN PROCESSES 08 4 08 GATE LEVEL DESIGN 5 08 SUBSYSTEM DESIGN 6 SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN 08 7 08 VHDL SYNTHESIS 8 CMOS TESTING 08 Total 64

Each Period is of 50 Minutes. 5 periods each Week. J.B. Institute of Engineering & Technology Department of CSE LESSON PLAN Subject Name: VLSI Subject Code: VLSI Class : III B.Tech. II Semester CSE Faculty Name: B.Kishore Kumar S.N o Topic as per JNTU syllabus *Lesson s# Suggested Books ** (Refer the list) Unit Introduction to IC Technology 2 TB OQ 2 MOS, PMOS, NMOS, CMOS & BiCMOS technologies Question Bank OQ DQ AQ DQ A 3 TB A Hand outs H 3 Oxidation, Lithography, Diffusion, Ion implantation, Metallization 3 RB A Unit 2 4 Basic Electrical Properties of MOS and BiCMOS Circuits 2 TB OQ DQ A H2 5 Ids-Vds relationships, MOS transistor threshold Voltage, gm, 2 TB A

gds, figure of merit 6 Pass transistor, NMOS Inverter, Various pull ups 7 CMOS Inverter analysis and design, Bi-CMOS Inverters. 2 TB A 2 TB A S.N o Topic as per JNTU syllabus *Lesson s# Suggested Books ** (Refer the list) Question Bank OQ DQ AQ Hand outs Unit 3 VLSI Design Flow, MOS Layers, 2 RB OQ DQ A 8 9 Stick Diagrams, Design Rules 2 RB A and Layout, 2 H3 0 m CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates 2 TB A Scaling of MOS circuits, Limitations of Scaling. 2 TB A Unit 4 2 Logic Gates and Other complex gat 2 RB OQ DQ A 3 Switch logic, Alternate gate circuits 2 RB A H4 4 Time Delays, Driving large Capacit Loads, Wiring Capacitances 2 TB A 5 Fan in,fan out, Choice of layers 2 RB A Unit 5 6 Subsystem Design 2 TB OQ DQ 2 A2 7 Subsystem Design, Shifters, Adders 2 TB A2 ALUs, H5 Multipliers 8 Parity generators, Comparators, 2 TB A2

Zero/One Detectors 9 Counters, High Density Memory Elements 2 TB A2 S.N o Topic as per JNTU syllabus *Lesson s# Suggested Books ** (Refer the list) Unit 6 Question Bank OQ DQ AQ OQ DQ 2 20 Array Subsystems 2 RB A2 Hand outs H6 2 SRAM,DRAM,ROM, 2 RB A2 22 Serial access memories 2 RB A2 23 Content addressable memory 2 RB A2 S.N o Topic as per JNTU syllabus *Lesson s# Suggested Books ** (Refer the list) Question Bank OQ DQ AQ Hand outs Unit -7 24 Semiconductor Integrated Circuit Design OQ DQ 2 A2 2 TB A2 H7 25 PLAs, FPGAs, CPLDs 2 TB A2 26 Standard Cells, Programmable Arra Logic, 2 RB A2 27 Design Approach 2 RB A2 Unit -8 OQ DQ 2 28 CMOS Testing, Need for testing, Te 2 TB A2 Principles H8 29 Design Strategies for test, Chip leve Test Techniques 2 RB A2 30 System-level Test Techniques, 2 RB A2 3 Layout Design for improved Testability. 2 TB A2 Total Lessons 64

Abbreviations and Notes OQ: Objective Questions DQ: Descriptive Questions AQ: Assignment Questions TB: Text Book RB: Reference Book SB: Suggested reference books (SB) Text Book: TB: Essentials of VLSI circuits and systems Kamran Eshraghian, Eshraghian Dougles and A. Pucknell, PHI, 2005 Edition TB2: Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education, 999. References: RB.. VLSI DESIGN by Lal Kishore. RB2. 2. CMOS VLSI DESIGN by Wayne wolf.

Assignment No. 0 Class : III B.Tech. II Semester CSE VLSI Objective: ) What is Moore s law? Explain the evolution of IC technology? 2) Expalin the CMOS fabrication using n-well and p-well? 3) Explain the Bi-CMOS fabrication using n-well process? 4) Explain drain characteristics of an n-channel enhancement MOSFET? 5) Define threshold voltage of an MOS device? 6) Explain the body effect of MOSFET? 7) What is the stick diagram? Draw various symbols for it. 8) Draw the stick diagram for nmos inverter? 9) Discuss the cmos design style? 0) Explain the clocked CMOS logic? ) Compare the geometry aspects between 2-input NMOS NAND and CMOS NAND gates Question No 0 Marks

) Explain the steps involved in IC fabrication? 2) Explain the NMOS fabrication procedure? 3) Explain the Thermal oxidation technique and kinetics of thermal oxidation? 4) Describe the 3 sources of wiring capacitance? 5) Explain the effect of wiring capacitance on the performance of a VLSI circuit. 6) Explain the domino logic and n-p CMOS logic? 7) Design a layout diagram for pmosnand? 8) What are the effects of scaling on Vt. 9) What are design rules? Why is metal-metal spacing larger than poly-poly spacing. 0) Derive an equation for Ids of an n-ch enhancement MOSFET operating in saturation region? ) Explain channel length modulation of the MOSFET? 2) Explain the latch up problem in CMOS circuits? 3) Explain the transfer characteristics of a CMOS inverter? 4) Explain the steps involved in IC fabrication? 5) Explain the NMOS fabrication procedure? 6) Explain the Thermal oxidation technique and kinetics of thermal oxidation? Question No 2 0 Marks ) Explain the NMOS fabrication procedure? 2) Explain the Thermal oxidation technique and kinetics of thermal oxidation? 3) What is Moore s law? Explain the evolution of IC technology?

Assignment No. 02 Class : III B.Tech. II Semester CSE Web Technologies Objectives ) Draw the circuit diagram for 4-by-4 barrel shifter? 2) Explain the booth recorded multiplier? 3) Draw schematic for tiny XOR gate? 4) Explain the serial access memories?. 5) Content addressable memory? 6) Draw and explain the architecture for SRAM, DRAM, and ROM? 7) Write about channeled gate arrays. 8) Write about channeled gate arrays with neat sketch? Question No 0 Marks ) Explain the shifting operation for barrel shifter 4x4? 2) Explain the basic memory chip architecture? 3) Design a magnitude comparator based on the data path operation? 4) Draw the circuit diagram of one transistor with transistor capacitor dynamic RAM? 5) Explain the basic memory chip architecture? 6) Draw and explain the architecture of an FPGA? 7) What are the advantages and disadvantages of the reconfiguration? 8) Explain the gate level and function level of testing? 9) Draw the structure of parallel scan? Question No 2 0 Marks

) Design a magnitude comparator based on the data path operation? 2) Draw the circuit diagram of one transistor with transistor capacitor dynamic RAM? VLSI : QUESTION BANK (Objective)-OQ ). The output of 3 iput OR gate when the inputs are 0,and 0 is (b) (a) 0 (b) (c) cannot be determined (d) oscillating between 0, 2. Switch logic is based on? (a) (a) pass transistor (b) inverters (c) gates (d) nmos gates 3) Area capacitance is given by? (d) (a) C= eoa/d. (b) C=e0/D (c) C=A/D (d) UML Profiles can be stereotyped for backward compatibility.

3). The n type pass transistor has length L=4λ,w= 2 λ Rs=? (b) most likely to be found in the main scenario of the use case get drink? (a) Rs (b) 2Rs (c) 3 Rs (d) 4 Rs 4) The number of gates that can be connected at the input? (a) (a) Fan IN (b) FAN OUT (c) D C FAN OUT (d) AC FANOUT 5) The yellow colour that is used in stickdiagram in NMOS design for? (d) (a) N diffusion (b) Polysilicon (c) metal (d) implant 6). The layers -------- at room temperature? (a) lead oxide (b) silicon oxide (c) silicondioxide (d) none 7). Inter layer capacitance is highly depended on. (a) fringing field (c) (b) layers. (c) layout. (d) wirelength.

8) For the 4X4 bit barrel shifter, the regularity factor is given by? (a). 8. (b) 4 (c) 2. (d) 6. 9) The level of any particular design can be measured by (c) (a) SNR (b) Ratio of amplitude (c) Regularity (d) Quantity 0). The subsystem design is classified as [a] first level [b] top level [c] bottom level [d] leaf-cell level ). A design that requires high density memory is usually (c) O (a. a single ship b. on chip c. partitioned into several chips d. DRAMS 2)A CMOS PLA is realized by (a) (a. pseudo nmos NOR gate (b CMOS NOR gate

(c) pseudo nmos NAND gate. (d) CMOS NAND gate. 3) The mapping of irregular combinational logic functions into regular structures is provided by the? [2 answers] ( d) [a]. FPGA. [b]. CPCD. [c] NAND/NOR structure [d]. EX-OR/OR structure 4) V XP X Z PLA represents as? (c) a. V-no.of input variables P-no.of output functions Z-no.of gates b. V-no.of gates P-no.of OR gates Z- no.of AND gates c. V-no.of input variables P-no.of product terms Z-no.of output functions d. V-no.of gates P-no.of AND gates Z-no.of output functions

VLSI :QUESTION BANK (Descriptive)-DQ ) Explain the steps involved in IC fabrication? 2) Explain the NMOS fabrication procedure? 3) Explain the Thermal oxidation technique and kinetics of thermal oxidation? 4) Describe the 3 sources of wiring capacitance? 5) Explain the effect of wiring capacitance on the performance of a VLSI circuit. 6) Explain the domino logic and n-p CMOS logic? 7) Design a layout diagram for pmos NAND? 8) What are the effects of scaling on Vt. 9) What are design rules? Why is metal-metal spacing larger than poly-poly spacing. 0) Derive an equation for Ids of an n-ch enhancement MOSFET operating in saturation region? ) Explain channel length modulation of the MOSFET? 2) Explain the latch up problem in CMOS circuits? 3) Explain the transfer characteristics of a CMOS inverter? 4) Explain the steps involved in IC fabrication? 5) Explain the NMOS fabrication procedure? 6) Explain the Thermal oxidation technique and kinetics of thermal oxidation? VLSI: QUESTION BANK 3 (Descriptive)-DQ2 7)Explain the shifting operation for barrel shifter 4x4? 8) Explain the basic memory chip architecture? 9) Design a magnitude comparator based on the data path operation? 20) Draw the circuit diagram of one transistor with transistor capacitor dynamic RAM?

2) Explain the basic memory chip architecture? 22) Draw and explain the architecture of an FPGA? 23) What are the advantages and disadvantages of the reconfiguration? 24) Explain the gate level and function level of testing? 25) Draw the structure of parallel scan?

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