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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT97 8-bit shift register with input flip-flops File under Integrated Circuits, IC06 December 1990

74HC/HCT97 FEATURES 8-bit parallel storage register inputs Shift register has direct overriding load and clear Output capability: standard I CC category: MSI GENERAL DESCRIPTION The 74HC/HCT97 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT97 consist each of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from storage) and clear inputs. QUICK REFERENCE DATA GND = 0 V; T amb =2 C; t r =t f = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS HC HCT UNIT t PHL / t PLH propagation delay C L = 1 pf; V CC =V SH CP to Q 17 ns ST CP to Q 2 29 ns PL to Q 21 26 ns f max maximum clock frequency SH CP 96 83 MHz C I input capacitance 3. 3. pf C PD power dissipation capacitance per package notes 1 and 2 29 32 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in MHz f o = output frequency in MHz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V 2. For HC the condition is V I = GND to V CC For HCT the condition is V I = GND to V CC 1. V ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2

74HC/HCT97 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 8 GND ground (0 V) 9 Q serial data output 10 MR asynchronous reset input (active LOW) 11 SH CP shift clock input (LOW-to-HIGH, edge-triggered) 12 ST CP storage clock input (LOW-to-HIGH, edge-triggered) 13 PL parallel load input (active LOW) 14 D S serial data input 1, 1, 2, 3, 4,, 6, 7 D 0 to D 7 parallel data inputs 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3

74HC/HCT97 Fig.4 Functional diagram. FUNCTION TABLE ST CP SH CP PL MR FUNCTION X X X data loaded to input latches X L H data loaded from inputs to shift register no clock edge X L H data transferred from input flip-flops to shift register X X L L invalid logic, state of shift register indeterminate when signals removed X X H L shift register cleared X H H shift register clocked Q n =Q n 1, Q 0 =D S Notes 1. H = HIGH voltage level L = LOW voltage level X = don t care = LOW-to-HIGH CP transition December 1990 4

74HC/HCT97 Fig. Logic diagram. December 1990

74HC/HCT97 Fig.6 Timing diagram. December 1990 6

74HC/HCT97 DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard I CC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; t r =t f = 6 ns; C L =0pF SYMBOL t PHL / t PLH t PHL t PHL / t PLH t PHL / t PLH PARAMETER propagation delay SH CP to Q propagation delay MR to Q propagation delay ST CP to Q propagation delay PL to Q T amb ( C) 74HC +2 40 to +8 40 to +12 min. typ. max. min. max. min. max. 16 8 21 17 80 29 23 69 2 t THL / t TLH output transition time 19 7 6 t rem t su ST CP pulse width HIGH or LOW SH CP pulse width HIGH or LOW MR pulse width LOW PL pulse width LOW 80 16 14 80 16 14 80 16 14 80 16 14 removal time MR to SH CP 60 12 10 set-up time 60 D n to ST CP 12 10 11 4 3 14 4 22 8 6 22 8 6 3 1 1 8 3 2 17 3 30 17 3 30 0 43 21 43 37 7 1 13 100 17 100 17 100 17 100 17 7 1 13 7 1 13 2 44 37 2 44 37 31 63 4 270 4 46 9 19 16 1 24 1 24 1 24 1 24 90 18 1 90 18 1 26 3 4 26 3 4 37 7 64 32 6 110 22 19 UNIT TEST CONDITIONS V CC (V) 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. WAVEFORMS Fig.7 Fig.8 Fig.7 Fig.9 Fig.9 Fig.7 Fig.7 Fig.8 Fig.9 Fig.10 Fig.11 December 1990 7

74HC/HCT97 SYMBOL t su t su t h t h f max PARAMETER set-up time 60 D S to SH CP 12 10 set-up time 60 PL to SH CP 12 10 hold time D n to ST CP hold time PL, D S to SH CP maximum pulse frequency SH CP 30 3 11 4 3 11 4 3 3 1 1 6 2 2 29 87 104 T amb ( C) 74HC +2 40 to +8 40 to +12 min. typ. max. min. max. min. max. 7 1 13 7 1 13 4.8 24 28 90 18 1 90 18 1 4.0 24 UNIT 4. 4. 4. 4. MHz 2.0 4. TEST CONDITIONS V CC (V) WAVEFORMS Fig.11 Fig.12 Fig.11 Fig.11 Fig.7 December 1990 8

74HC/HCT97 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard I CC category: MSI Note to HCT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D S D n PL, MR ST CP, SH CP UNIT LOAD COEFFICIENT 0.2 0.30 1.0 1.0 December 1990 9

74HC/HCT97 AC WAVEFORMS FOR 74HCT GND = 0 V; t r =t f = 6 ns; C L =0pF T amb ( C) TEST CONDITIONS 74HCT SYMBOL PARAMETER UNIT V +2 40 to +8 40 to +12 CC (V) WAVEFORMS min. typ. max. min. max. min. max. t PHL / t PLH propagation delay 23 40 0 60 ns 4. Fig.7 SH CP to Q t PHL propagation delay 28 49 61 74 ns 4. Fig.8 MR to Q t PHL / t PLH propagation delay 33 7 71 86 ns 4. Fig.7 ST CP to Q t PHL / t PLH propagation delay 30 2 6 78 ns 4. Fig.9 PL to Q t THL / t TLH output transition time 7 1 19 22 ns 4. Fig.9 t rem t su t su t su t h t h f max SH CP pulse width HIGH or LOW 16 7 24 ns 4. Fig.7 ST CP pulse width 16 6 24 ns 4. Fig.7 HIGH or LOW MR pulse width 2 14 31 38 ns 4. Fig.8 LOW PL pulse width 10 2 30 ns 4. Fig.9 LOW removal time 12 2 1 18 ns 4. Fig.10 MR to SH CP set-up time 12 1 18 ns 4. Fig.11 D n to ST CP set-up time 12 2 1 18 ns 4. Fig.11 D S to SH CP set-up time 12 4 1 18 ns 4. Fig.12 PL to SH CP hold time 1 ns 4. Fig.11 D n to ST CP hold time 2 ns 4. Fig.11 PL, D S to SH CP maximum pulse frequency 30 7 24 MHz 4. Fig.7 SH CP December 1990 10

74HC/HCT97 AC WAVEFORMS (1) HC : V M = 0%; V I = GND to V CC. HCT : V M = 1.3 V; V I = GND to 3 V. (1) HC : V M = 0%; V I = GND to V CC. HCT : V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the SH CP and ST CP inputs to Q output propagation delays, the SH CP and ST CP pulse widths and maximum clock pulse frequency. Fig.8 Waveforms showing the MR input to Q output propagation delays and the MR pulse width. (1) HC : V M = 0%; V I = GND to V CC. HCT : V M = 1.3 V; V I = GND to 3 V. (1) HC : V M = 0%; V I = GND to V CC. HCT : V M = 1.3 V; V I = GND to 3 V. Fig.9 Waveforms showing the PL input to Q output propagation delays, PL pulse width and output transition times. Fig.10 Waveforms showing the MR input to SH CP, ST CP removal times. December 1990 11

74HC/HCT97 (1) HC : V M = 0%; V I = GND to V CC. HCT : V M = 1.3 V; V I = GND to 3 V. (1) HC : V M = 0%; V I = GND to V CC. HCT : V M = 1.3 V; V I = GND to 3 V. Fig.11 Waveforms showing hold and set-up times for D S, D n inputs to SH CP, ST CP inputs. Fig.12 Waveforms showing set-up times for PL input to SH CP input. PACKAGE OUTLINES See 74HC/HCT/HCU/HCMOS Logic Package Outlines. December 1990 12