Fundamentals of Nanoelectronics: Basic Concepts Sławomir Prucnal FWIM Page 1
Introduction Outline Electronics in nanoscale Transport Ohms law Optoelectronic properties of semiconductors Optics in nanoscale Band gap Quantum confinement effect Page 2
Photolithography Ion implantation Etching Temporary Gate Formation Silicon wafer metalization http://download.intel.com/newsroom/kits/chipmaking/pdfs/sand-to-silicon_22nm-version.pdf Page 3
Introduction NEAR-TERM 2013-2020 Scaling of Si CMOS - Implementation of fully depleted SOI Implementation of high-mobility CMOS channel materials http://www.itrs.net/links/2013itrs/home2013.htm Page 4
SmartCut Introduction SIMOX process SOI Page 5 From Wikipedia
Introduction Silicon wafer https://www.youtube.com/watch?v=zvqmc7ql2b8 http://www.google.de/imgres?imgurl=http://www.techdesignforums.com/practice/files/2013/05/tdf-snpspvff-fdsoi-3lrg.jpg&imgrefurl=http:// www.techdesignforums.com/practice/ technique/physical-verification-design-finfet-fd-soi/ &h=532&w=980&tbnid=bg2t-9aazopmjm:&tbnh=90&tbnw=166&usg= 3fSXT57run64yrsHWP2cDxmXjfs=&docid=9ZIFDJ9SQcwv AM&sa=X&ved=0CEAQ9QEwBWoVChMIrqu3kfrAxwIVw7kUCh3DKQn5 (Source: Synopsys) Page 6
Introduction http://www.google.de/imgres?imgurl=http://www.techdesignforums.com/practice/files/2013/05/tdf-snpspvff-fdsoi-3lrg.jpg&imgrefurl=http:// www.techdesignforums.com/practice/ technique/physical-verification-design-finfet-fd-soi/ &h=532&w=980&tbnid=bg2t-9aazopmjm:&tbnh=90&tbnw=166&usg= 3fSXT57run64yrsHWP2cDxmXjfs=&docid=9ZIFDJ9SQcwv AM&sa=X&ved=0CEAQ9QEwBWoVChMIrqu3kfrAxwIVw7kUCh3DKQn5 (Source: Synopsys) Page 7
Introduction The main manufacturing challenges for finfets (above 20 nm) are: - controlling the etch along the edges - uniform doping of 3D surfaces - Deposition of all the films used in the gate stack Benefits reduction in power consumption (~50% over 32nm) Faster switching speed Availability of strain engineering Challanges Very restrictive design options Fin width variability and edge quality leads to variability in threshold voltage V T Extra manufacturing complexity and expense Page 8
Fully depleted silicon-on-insulator FD-SOI vs PD-SOI The top silicon layer is typically between 50 and 90 nmthick Silicon under the channel is partially depleted of mobile charge carriers. The top silicon layer is between 5 and 20 nm thick, typically ¼ of the gate length Silicon under the gate is fully depleted of mobile charge carriers. There is no floating body effect. Page 9
Introduction Fully depleted silicon-on-insulator FD-SOI (below 14 nm) Benefits Significant reduction in power consumption below 11 nm Faster switching speed Easier, standard manufacturing process Challanges High cost of initial wafers Variability in V T due to variations in the thickness of silicon thin-film No strain engineering possible Availability of back-biasing to control V T No doping variability Page 10 10
Introduction NEAR-TERM 2013-2020 Scaling of Si CMOS - Implementation of fully depleted SOI Implementation of high-mobility CMOS channel materials LONG-TERM 2021-2028 Implementation of advanced multi-gate structures ultra-thin body multi-gate MOSFETs http://www.itrs.net/links/2013itrs/home2013.htm Page 11
Multi-gate structures http://www.google.de/imgres?imgurl=http%3a%2f%2fwww.fz-juelich.de%2fshareddocs%2fbilder%2fpgi%2fpgi-9%2fen%2fforschung%2fnanowires%2fmultigatmosfet. jpg%253f blob%253dnormal&imgrefurl=http%3a%2f%2fwww.fz-juelich.de%2fpgi%2fpgi-9%2fde%2fforschung%2f05-si-nano-mosfet%2f01-multigate%2520nanowire%2f_node.html&h= 336&w=600&tbnid=4kA-VMzzxXDUlM%3A&docid=ZqBKi7JKfbji2M&ei=OrjaVbjkF4n0ULaHjdAE&tbm=isch&iact=rc&uact=3&dur=2146&page=1&start=0&ndsp=30&ved=0CHQQrQMw GmoVChMIuOnjrIrBxwIVCToUCh22QwNK Page 12
Multi-gate structures http://www.sec.gov/archives/edgar/data/937966/000119312514331751/g784347page_012.jpg Page 13
Hybrid 1D and 3D nanostructures Room temperature semi-logarithmic I-V characteristic of n-inas/p-si heterojunction. AFM topography of annealed and etched sample Prucnal et al. Nanolett. 11, 2814, (2011) Page 14
Hybrid 1D and 3D nanostructures InAs Page 15
Hybrid 1D and 3D nanostructures Page 16
Current (A) GeOI for junctionless transistors 10-8 100x100x3000 nm H x W x L 100 nm Ge 50 nm Ge 10-9 50x50x3000 nm H x W x L 10-10 10-11 0.0 0.5 1.0 1.5 2.0 Voltage (V) Page 17
Electronic transport Page 18
3 cm 300 length scale: transistor density 1 mm = 1m/1000 1985 10 mm channel length 1 mm = 1mm/1000 2010 < 100 nm 2015 < 20 nm 1 nm = 1mm/1000 Atomic distance < 1 nm For the channel length of 10 mm size of transisotr is 100 mm 3 cm 300 10 5 Page 19
3 cm 30000 length scale: transistor density 1 mm = 1m/1000 1985 10 mm channel length 1 mm = 1mm/1000 2010 < 100 nm 2015 < 20 nm 1 nm = 1mm/1000 Atomic distance < 1 nm For the channel length of 100 nm size of transisotr is 1 mm 3 cm 30000 10 9 Page 20
3 cm 150000 length scale: transistor density 1 mm = 1m/1000 1985 10 mm channel length 1 mm = 1mm/1000 2010 < 100 nm 2015 < 20 nm 1 nm = 1mm/1000 Atomic distance < 1 nm For the channel length of 20 nm size of transisotr is 200 nm 3 cm 150000 10 9 25 Page 21
length scale:electronic transport 1 mm = 1m/1000 1985 10 mm 1 mm = 1mm/1000 2010 < 100 nm 2015 < 20 nm 1 nm = 1mm/1000 Atomic distance < 1 nm S V o - + Channel V I =R I D R determines On/Off state and is controlled by 3 rd terminal Page 22
length scale:electronic transport 1 mm = 1m/1000 1985 10 mm 1 mm = 1mm/1000 2010 < 100 nm 2015 < 20 nm 1 nm = 1mm/1000 Atomic distance < 1 nm S e V o - + Channel I e D Diffusive transport Page 23
length scale:electronic transport 1 mm = 1m/1000 1985 10 mm 1 mm = 1mm/1000 2010 < 100 nm 2015 < 20 nm 1 nm = 1mm/1000 Atomic distance < 1 nm S e V o - + Channel I e D Ballistic transport Page 24
length scale: Ohms law S ~mm ~nm V o Channel D S V - + V =R I I W V - V o Channel L + I =R= ρ W L I D I =R= ρ W (L + m eanf ree p ath ) R=r L A, L 0, R 0, R = h q 2=25kW for ballistic transport Page 25
length scale: Ohms law G. Jo et al. J. Appl. Phys. 102, 084508 (2007) Page 26
Mobility Page 27
length scale: mobility Page 28
length scale: mobility Ballistic transport Diffusive transport F Gámiz 2004 Semicond. Sci. Technol. 19 113 Page 29
length scale: mobility Patrick S. Goley * and Mantu K. Hudait Materials 2014, 7(3), 2301-2339 Page 30
Mobility cm 2 /Vs Mobility cm 2 /Vs GeOI for junctionless transistors 200 175 150 125 100 75 50 25 SmartCut GeOI Epi-Ge University of Tokyo hole mobility for 50 nm Ge PECVD+FLA HZDR 0 2.0x10 18 4.0x10 18 6.0x10 18 8.0x10 18 1.0x10 19 Carrier concentration (cm -3 ) Carrier mobility vs. Carrier concentration in 50 nm thick Ge on insulator. 500 Electron mobility for 50 nm Ge 400 300 200 100 Preliminary data SmartCut GeOI Epi-Ge University of Tokyo PECVD+FLA HZDR Xiao Yu, et all. ECS Solid State Lett., 4, P15, (2015) Page 31 0 10 14 10 15 10 19 Carrier concentration (cm -3 )
Downscaling https://www.youtube.com/watch?v=v2gdmj42sim Page 32
Optoelectronic properties of semiconductors Douglas J Paul, Semicond. Sci. Technol. 19, R75-R108 (2004) Page 33
Optoelectronic properties of semiconductors IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 1, JANUARY 2008 Page 34
Optical properties of semiconductors Page 35
Optical properties of semiconductors k=0 (a) Direct-bandgap semiconductors such as GaAs, InP and GaN. (b) An indirect-bandgap semiconductor, such as silicon or germanium. k 0 Page 36
Optical properties of semiconductors Page 37
Optical properties of semiconductors Ge with direct bandgap Direct bandgap energies of unstrained Ge 1 x Sn x alloys (a) and calculated band edges of the various bands for pseudomorphic Ge 1 x Sn x alloys on Ge as a function of Sn composition. Jia-Zhi Chen, et al., Opt. Mater. Express 4, 1178-1185 (2014) Page 38
Optical properties of semiconductors Schematic of the effect of quantum confinement on the electronic structure of a semiconductor. The arrows indicate the lowest energy absorption transition. (a) Bulk semiconductor CB = conduction band; VB = valence band). (b) Three lowest electron (En le ) and hole (En lh ) energy levels in a quantum dot. The corresponding wave functions are represented by dashed lines. (c) Semiconductor nanocrystal (quantum dot). Page 39
Optical properties of semiconductors (a) Three lowest electron (En le ) and hole (En lh ) energy levels in a semiconductor nanocrystal quantum dot. The corresponding wave functions are represented by the dashed lines. Allowed optical transitions are given by the arrows. (b) Assignment of the transitions in the absorption spectrum of colloidal CdTe quantum dots. Page 40
Optical properties of semiconductors Energy of photons emitted by QDs E g = band gap energy of bulk semiconductor; R = radius of quantum dot; m e* = effective mass of excited electron; m h* = effective mass of excited hole; h = Planck s constant. Page 41
Optical properties of semiconductors Energy of photons emitted by QDs CdS QD 1. Experimental data 2. calculation E g = band gap energy of bulk semiconductor; R = radius of quantum dot; m e* = effective mass of excited electron; m h* = effective mass of excited hole; h = Planck s constant. Page 42
Optical properties of semiconductors Energy of photons emitted by QDs E g = band gap energy of bulk semiconductor; R = radius of quantum dot; m e* = effective mass of excited electron; m h* = effective mass of excited hole; h = Planck s constant. "Advanced Biomedical Engineering", book edited by Gaetano D. Gargiulo, Coeditor: Alistair McEwan, ISBN 978-953-307-555-6, Page 43
Optical properties of semiconductors Bohr radius for semiconductors a* b = ε m μ a b a b =0.053 nm dielectric constant m electron mass m effective electron mass Schematic representation of the quantum confinement effect on the energy level structure of a semiconductor material. Celso de Mello Donegá, Chem. Soc. Rev., 40, 1512-1546 (2011) Page 44
Questions?? Page 45