SyreNe System Reduction for Nanoscale IC Design

System Reduction for Nanoscale Max Planck Institute for Dynamics of Complex Technical Systeme Computational Methods in Systems and Control Theory Group Magdeburg Technische Universität Chemnitz Fakultät für Mathematik Mathematik in Industrie und Technik Chemnitz System Reduction for Nanoscale for Complex Dynamical Systems TU Berlin, 2 December 2010

Background What is? is a research network within the BMBF (German Federal Ministry of Education and Research) funded program Mathematics for Innovations in Industry and Services It started July 1, 2007, and will terminate December 31, 2010. 6 projects, 4 universities, 1 research institute, 3 industrial partners. 1st workshop: for Circuit Simulation, held in Hamburg, October 30 31, 2008; proceedings will appear in Springer Lecture Notes in Electrical Engineering, Vol. 74, Feb. 2011. Successor: BMBF research network for Fast Simulation of new Semiconductor Devices for Nano- and Microsystems-Technology, October 1, 2010 September 30, 2013; 4 universities, 2 research institutes, 4 industrial partners cooperate in 6 projects. 2/13

System Reduction for Nanoscale Personnel and Industrial Partners } TU Chemnitz } Prof. Dr. Dipl.-Math. techn. Andre Schneider Dipl.-Math. techn. Thomas Mach Prof. Dr. Michael Hinze Dipl.-Math. Ulrich Matthes Dipl.-Math. techn. Andre Eppler Prof. Dr. Heike Faßbender Juan Pablo Amorocho M.Sc. Dipl.-Math. Oliver Schmidt Dr. Tatjana Stykel Dr. Andreas Steinbrecher { Dipl.-Math. techn. Martin Kunkel } } } 3/13 { z Dr. Patrick Lang TU Berlin ITWM Kaiserslautern z { { z } Prof. Dr. Matthias Bollho fer TU Braunschweig TU Braunschweig z { z Universita t Hamburg z {

Micro-/ Micro- / Miniaturization Circuit Simulation State-of-the-art in 2006 (at proposal writing) Development of electronic devices and integrated circuits (ICs) with structures in the µ- (1 µm= 10 6 m) to nano- (1 nm= 10 9 m) range. Transition from Micro- to in order to achieve higher performance using smaller devices at lower cost. Miniaturization of common ICs based on silicon reaches its physical limits, frequency cannot be increased arbitrarily. Further miniaturization requires use of Nanotechnology, so far without the use of quantum effects (tunnel effect is already employed to some extent). 4/13

Micro-/ Micro- / Miniaturization Circuit Simulation Applications Consumer selectronics (video game consoles, MP3 player,... ) mobile and smart phones, computer technology (CPUs, DRAM,... ) navigation, sensors, ASICs = Application-Specific ICs, e.g. for automotive engineering, automatic control, medical engineering,... 4/13

Miniaturization Moore s Law Moore s Law (1965/75) states that the number of transistors on a chip doubles every 24 months. Micro- / Miniaturization Circuit Simulation 5/13 Source: http://en.wikipedia.org/wiki/file:transistor_count_and_moore s_law_-_2008.svg

Miniaturization Roadmap of CMOS ( Complementary Metal Oxide Semiconductor ) Technology Micro- / Miniaturization Circuit Simulation Production process of ICs is mostly based on CMOS technology ( Complementary Metal Oxide Semiconductor ). 2 complimentary (n-/p-channel) MOSFETs are connected to enable logical operations. 6/13

Miniaturization Roadmap of CMOS ( Complementary Metal Oxide Semiconductor ) Technology Micro- / Miniaturization Circuit Simulation 6/13 CMOS Technology Miniaturization Microtechnology 10 µm e.g., Intel 4004 (1971) 3 µm e.g., Intel 8086 (1978) 1.5 µm e.g., Intel 80286 (1982) 1 µm e.g., Intel 386 (1985) 800 nm (0.80 µm) e.g., Intel 486 (1989) 600 nm (0.60 µm) e.g., Intel 486DX2 (1990) 350 nm (0.35 µm) e.g., Intel Pentium Pro (1995), Nintendo 64 250 nm (0.25 µm) e.g., DEC Alpha (1999), Playstation 2 180 nm (0.18 µm) e.g., Intel Pentium P4 (2000) 130 nm (0.13 µm) Nanotechnology (< 100nm) 90 nm 65 nm e.g., Intel Core 2 Duo (2006) 45 nm e.g., Intel Core 2 Extreme (2007) 32 nm Intel Core i7 980X Gulftown (03/2010) 22 nm limit of CMOS production (2011/12) 16 nm transition to (2018) 11 nm (tunnel effect) (2022) Source: http://en.wikipedia.org, ITRS International Technology Roadmap for Semiconductors

System Reduction for Nanoscale Miniaturization Roadmap of CMOS ( Complementary Metal Oxide Semiconductor ) Technology Micro/ Miniaturization Circuit Simulation Size matters... Transient-Voltage-Suppression (TVS)-Diode (Infineon Technologies). Protection against electro-static discharge, for high-speed interfaces, e.g., USB 2.0, Ethernet 10/1000, etc. 6/13

Circuit Simulation Micro- / Miniaturization Circuit Simulation VLSI Circuit Simulation Uses mathematical models to replicate behavior of electronic circuits (or devices device simulation). VLSI simulation before production of first prototype increases the efficiency of the VLSI design process significantly, errors can be detected and avoided in the prototype. Particularly, photo-masking for IC prototypes is extremely expensive, testing of internal signal transmission is extremely difficult. Hence: numerical simulation is indispensable for VLSI design! Source: http://en.wikipedia.org/wiki/circuit_simulation 7/13

Introduction Further Aspects Micro- / Miniaturization Circuit Simulation Complete IC models cannot be simulated, sub-circuits consist of hundreds to millions of equations, i.e., high-dimensionality!. Numerical simulation is possible by connecting compact models of sub-circuits. Modeling of nonlinear devices (diodes, transistors) leads to nonlinear systems of differential algebraic equations (DAEs). Critical devices can no longer be replaced by partial element equivalent circuits (PEECs). Device simulation requires partial differential equations (PDEs, drift diffusion (DD) model). Coupling of circuits and DD device models leads to partial differential-algebraic equations (PDAEs). 8/13

Motivation for System/ Multi-layer layouts Motivation Goals Source: http://en.wikipedia.org/wiki/image:silicon_chip_3d.png. 9/13

Motivation for System/ Motivation Goals Consequences of miniaturization Moore s Law circuit models require increasingly many equations, for the network topology (Kirchhoff laws) on the one hand and characteristic equations for devices on the other hand. Verification of VLSI design requires numerous simulations for varying input signals. Increasing integration density and multi-layer layout more and more parasitic effects which must be included in the simulation model. 9/13

Motivation for System/ Motivation Goals Consequence: Methods for reduction of the complexity of mathematical models for VLSI design (electronic design automation, EDA) indispensable! System/ 9/13

Goals of Motivation Goals Automatic computation of compact models. Errors in output signals of reduced models should satisfy prescribed error tolerance. Require computable error estimates! Preserve physical properties: stability, passivity. Reduced models should lead to significantly faster simulation times! Reduced models should be realizable as circuit (sufficient: reziprocity). 10/13

System Reduction for Nanoscale http://www.syrene.org Goals Development of methods for model and system reduction of high-dimensional nanoelectronic IC models. Comparison of methods and verification in practical semiconductor development environments. 2 complementary approaches: Reduction of coupled device-circuit system using global method. Decoupling of individual devices and linear sub-circuits, generation of corresponding compact models, coupling of reduced models. 11/13

12/13 TP1 Model order reduction for coupled systems of ICs U Hamburg, PI: Michael Hinze TP2 Passivity preserving model reduction for nonlinear DAEs TU Braunschweig, PI: Heike Faßbender TP3 Element-based model reduction in circuit simulation TU Berlin, PI: Tatjana Stykel TP4 Reduced representation of power grid models TU Chemnitz, PI: TP5 Coupling of numeric/symbolic reduction techniques for the generation of parameterized models of nanoelectronic systems Fraunhofer ITWM Kaiserslautern, PI: Patrick Lang TP6 Numerical solution of systems of equations and coupling of components in model order reduction TU Braunschweig, PI: Matthias Bollhöfer

Results... presented at for Complex Dynamical Systems Friday, December 3, session SYRENE I 14:30 14:50 Ulrich Matthes (TP1) Residual based POD Model Order Reduction of Drift-Diffusion Equations in electrical networks 14:50 15:10 Andreas Steinbrecher (TP3) PABTEC: A software package for model reduction of nonlinear circuit equations 15:10 15:30 André K. Eppler (TP6) Low rank Krylov subsapce methods for solving large Lyapunov equations Saturday, December 4, session SYRENE II 10:00 10:20 André Schneider (TP4) Reduced Representation of Power Grid Models 10:20 10:40 Juan Pablo Amorocho (TP2) Model Order Reduction of Large Nonlinear Electric Circuits via the Trajectory Piecewise- Linear Approach 10:40 11:00 Oliver Schmidt (TP5) Coupled symbolic-numerical model reduction using the hierarchical structure of nonlinear electrical circuits For more details, visit www.syrene.org. Enjoy the workshop! 13/13