PHILIPS 74LVT transparent D-type latch datasheet

Similar documents
74ALVT V/3.3V 16-bit transparent D-type latch (3-State) INTEGRATED CIRCUITS

74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State)

CONDITIONS T amb = 25 C; GND = 0V

74F573 Octal transparent latch (3-State) 74F574 Octal transparent latch (3-State)

74LVC823A 9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)

74LV373 Octal D-type transparent latch (3-State)

74LVC573 Octal D-type transparent latch (3-State)

74ABT899 9-bit dual latch transceiver with 8-bit parity generator/checker (3-State)

74ABT ABTH bit latched transceiver with dual enable and master reset (3-State)

74LVC574A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)

3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state

74LVC374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS

74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS

INTEGRATED CIRCUITS. 74F85 4-bit magnitude comparator. Product specification 1994 Sep 27 IC15 Data Handbook. Philips Semiconductors

Octal buffer/line driver (3-State)

74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger

INTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook

CONDITIONS T amb = 25 C; GND = 0V. C L = 50pF; V CC = 5V 4.4 ns. Outputs disabled; V O = 0V or V CC

INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28

INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook

INTEGRATED CIRCUITS. 74F521 8-bit identity comparator. Product specification May 15. IC15 Data Handbook

INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.

INTEGRATED CIRCUITS. 74ALS138 1-of-8 decoder/demultiplexer. Product specification 1996 Jul 03 IC05 Data Handbook

INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.

INTEGRATED CIRCUITS. 74F804, 74F1804 Hex 2-input NAND drivers. Product specification Sep 14. IC15 Data Handbook

INTEGRATED CIRCUITS. 74ALS30A 8-Input NAND gate. Product specification 1991 Feb 08 IC05 Data Handbook

INTEGRATED CIRCUITS. 74F154 1-of-16 decoder/demultiplexer. Product specification Jan 08. IC15 Data Handbook

INTEGRATED CIRCUITS. 74LV259 8-bit addressable latch. Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook.

74LV393 Dual 4-bit binary ripple counter

PHILIPS 74ALVT16245 transceiver datasheet

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

74ALVCH bit universal bus transceiver (3-State)

74F393 Dual 4-bit binary ripple counter

INTEGRATED CIRCUITS. PCK2002P 533 MHz PCI-X clock buffer. Product data Supersedes data of 2001 May Dec 13. Philips Semiconductors

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting

8-bit shift register with 2:1 mux-in, latched B inputs, and serial out N74F835N FEATURES PIN CONFIGURATION

8-bit binary counter with output register; 3-state

DATA SHEET. 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS

The 74HC21 provide the 4-input AND function.

UNISONIC TECHNOLOGIES CO., LTD

74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.

74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state

DATA SHEET. 74LVC16374A; 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS

74HC164; 74HCT bit serial-in, parallel-out shift register

74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state

Hex inverting Schmitt trigger with 5 V tolerant input

74HC1G125; 74HCT1G125

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

8-bit serial-in/parallel-out shift register

8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground).

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.

74AHC373; 74AHCT373. Octal D-type transparant latch; 3-state

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

DATA SHEET. 74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state INTEGRATED CIRCUITS

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

14-stage binary ripple counter

Octal D-type transparent latch; 3-state

DISCRETE SEMICONDUCTORS DATA SHEET M3D071. BAT74 Schottky barrier double diode. Product specification Supersedes data of 1996 Mar 19.

DATA SHEET. BSN304 N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 17

UNISONIC TECHNOLOGIES CO., LTD

74HC244; 74HCT244. Octal buffer/line driver; 3-state

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state

74LCX16374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

2-input EXCLUSIVE-OR gate

DATA SHEET. PH2369 NPN switching transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr Oct 11.

74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop.

PMWD16UN. 1. Product profile. 2. Pinning information. Dual N-channel µtrenchmos ultra low level FET. 1.1 General description. 1.

74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.

2N7002T. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

DATA SHEET. BSN254; BSN254A N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS

DATA SHEET. BSS192 P-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 20

74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger

TrenchMOS technology Very fast switching Logic level compatible Subminiature surface mount package.

2N7002F. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

74LCXH Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26Ω Series Resistors in Outputs

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

The 74LVC1G02 provides the single 2-input NOR function.

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

PMV65XP. 1. Product profile. 2. Pinning information. P-channel TrenchMOS extremely low level FET. 1.1 General description. 1.

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

74LCX16374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

5.0 V 256 K 16 CMOS SRAM

74HC393; 74HCT393. Dual 4-bit binary ripple counter

DATA SHEET. BC368 NPN medium power transistor; 20 V, 1 A DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Dec 01.

INTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

DISCRETE SEMICONDUCTORS DATA SHEET. PMBT3906 PNP switching transistor. Product specification Supersedes data of 1999 Apr 27.

PMV56XN. 1. Product profile. 2. Pinning information. µtrenchmos extremely low level FET. 1.1 Description. 1.2 Features. 1.

UNISONIC TECHNOLOGIES CO., LTD U74LVC1G125

The 74LVC1G11 provides a single 3-input AND gate.

TrenchMOS ultra low level FET

PMV40UN. 1. Product profile. 2. Pinning information. TrenchMOS ultra low level FET. 1.1 Description. 1.2 Features. 1.

N-channel µtrenchmos ultra low level FET. Top view MBK090 SOT416 (SC-75)

PMN40LN. 1. Description. 2. Features. 3. Applications. 4. Pinning information. TrenchMOS logic level FET

The 74LV08 provides a quad 2-input AND function.

Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;

NPN/PNP low V CEsat Breakthrough in Small Signal (BISS) transistor pair in a SOT457 (SC-74) Surface Mounted Device (SMD) plastic package.

DATA SHEET. BC369 PNP medium power transistor; 20 V, 1 A DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Nov 20.

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:

Transcription:

PIIPS transparent -type latch datasheet http://www.manuallib.com/philips/74lvt162373-transparent-d-type-latch-datasheet.html The is a high-performance BiCMOS product designed for VCC operation at 3.3 V. Manualib.com collects and classifies the global product instrunction manuals to help users access anytime and anywhere, helping users make better use of products. http://www.manuallib.com

INTGRAT CIRCUITS 1999 Sep 23 IC23 ata andbook

FATURS 16-bit transparent latch 3-State buffers Output capability: +12 ma / 12 ma TT input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs ive insertion/extraction permitted Outputs include series resistance of 30 Ω making external resistors unnecessary Power-up reset Power-up 3-State No bus current loading when output is tied to 5 V bus atch-up protection exceeds 500 ma per JC Std 17 S protection exceeds 2000 V per MI ST 883 Method 3015 and 200 V per Machine Model SCRIPTION The is a high-performance BiCMOS product designed for V CC operation at 3.3 V. This device is a 16-bit transparent -type latch with non-inverting 3-State bus compatible outputs. The device can be used as two 8-bit latches or one 16-bit latch. When atch nable () input is igh, the outputs follow the data () inputs. When atch nable is taken ow, the outputs are latched at the levels of the inputs one setup time prior to the igh-to-ow transition. The is designed with 30 Ω series resistance in both the igh and ow states of the output. This design reduces the noise in applications such as memory address drivers, clock drivers, and bus receivers/transmitters. UICK RFRNC ATA SYMBO t P t P Propagation delay nx to nx PARAMTR C = 50 pf; V CC = 3.3 V CONITIONS T amb = 25 C TYPICA UNIT 3.0 ns C IN Input capacitance V I = 0 V or 3.0 V 3 pf C OUT Output capacitance Outputs disabled; V O = 0 V or 3.0 V 9 pf I CCZ Total supply current Outputs disabled; V CC = 3.6 V 70 µa ORRING INFORMATION PACKAGS TMPRATUR RANG ORRING CO WG NUMBR 48-Pin Plastic SSOP Type III 40 C to +85 C SOT370-1 48-Pin Plastic TSSOP Type II 40 C to +85 C GG SOT362-1 1999 Sep 23 2 853-2172 22406

PIN CONFIGURATION OGIC SYMBO 1O 1 48 1 47 46 44 43 41 40 38 37 10 2 47 10 11 3 4 46 45 11 48 10 11 12 13 1 14 15 16 17 12 5 44 12 1 1O 13 6 43 13 10 11 12 13 14 15 16 17 V CC 7 42 V CC 14 15 8 9 41 40 14 15 2 3 5 6 8 9 11 12 10 39 36 35 33 32 30 29 27 26 16 11 38 16 17 20 12 13 37 36 17 20 25 20 221 22 23 2 24 25 26 27 21 14 35 21 24 2O 15 34 20 21 22 23 24 25 26 27 22 16 33 22 23 V CC 24 17 18 19 32 31 30 23 V CC 24 13 14 16 17 19 20 22 23 SA00044 25 20 29 25 21 28 OGIC SYMBO (I/IC) 26 22 27 26 27 2O 23 24 26 27 25 2 SA00043 1O 1 2O 2 1 48 24 25 1N C3 2N C4 PIN SCRIPTION PIN NUMBR SYMBO FUNCTION 47, 46, 44, 43, 41, 40, 38, 37, 36, 35, 33, 32, 30, 29, 27, 26 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 16, 17, 19, 20, 22, 23 10 17 20 27 10 17 20 27 1, 24 1O, 2O 48, 25 1, 2 4, 10, 15, 21, 28, 34, 39, 45 ata inputs ata outputs Output nable inputs (active-ow) atch nable inputs (active-igh) Ground () 7, 18, 31, 42 V CC Positive supply voltage 11 12 13 14 15 16 17 18 21 22 23 24 25 26 27 28 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 3 4 1 2 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 11 12 13 14 15 16 17 18 21 22 23 24 25 26 27 28 SW00010 1999 Sep 23 3

OGIC IAGRAM n0 n1 n2 n3 n4 n5 n6 n7 n no n0 n1 n2 n3 n4 n5 n6 n7 SA00046 FUNCTION TAB INPUTS INTRNA OUTPUTS no n nx l h RGISTR n0 n7 X NC NC old X nx NC nx = igh voltage level h = igh voltage level one set-up time prior to the igh-to-ow transition = ow voltage level l = ow voltage level one set-up time prior to the igh-to-ow transition NC= No change X = on t care Z = igh impedance off state = igh-to-ow transition SCMATIC OF AC OUTPUT Z Z nable and read register atch and read register isable outputs OPRATING MO V CC 27 Ω 27 Ω OUTPUT SW00503 1999 Sep 23 4

ABSOUT MAXIMUM RATINGS 1, 2 SYMBO PARAMTR CONITIONS RATING UNIT V CC C supply voltage 0.5 to +4.6 V I IK C input diode current V I < 0 50 ma V I C input voltage 3 0.5 to +7.0 V I OK C output diode current V O < 0 50 ma V OUT C output voltage 3 Output in Off or igh state 0.5 to +7.0 V Output in ow state 128 I OUT C output current Output in igh state 64 ma T stg Storage temperature range 65 to +150 C NOTS: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. xposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. RCOMMN OPRATING CONITIONS IMITS SYMBO PARAMTR MIN MAX UNIT V CC C supply voltage 2.7 3.6 V V I Input voltage 0 5.5 V V I igh-level input voltage 2.0 V V I Input voltage 0.8 V I O igh-level output current 12 ma I O ow-level output current 12 ma t/ v Input transition rise or fall rate; Outputs enabled 10 ns/v T amb Operating free-air temperature range 40 +85 C 1999 Sep 23 5

C CTRICA CARACTRISTICS IMITS SYMBO PARAMTR TST CONITIONS Temp = 40 C to +85 C UNIT MIN TYP 1 MAX V IK Input clamp voltage V CC = 2.7V; I IK = 18mA 0.85 1.2 V V O igh-level output voltage V CC = 3.; I O = 12mA 2.0 V O ow level output voltage V CC = 3.; I O = 16mA 0.8 V V RST Power-up output ow voltage 5 V CC = 3.6V; I O = 1mA; V I = or V CC 0.1 0.55 V I I Input leakage current V CC = 3.6V; V I = V CC or Control pins 0.1 ±1 V CC = 0 or 3.6V; V I = 5.5V 0.4 10 V CC = 3.6V; V I = V CC 0.1 1 ata pins 4 V CC = 3.6V; V I = 0 0.4 5 I OFF Output off current V CC = ; V I or V O = 0 to 4.5V 0.1 ±100 µa V CC = 3V; V I = 0.8V 75 135 I O Bus old current inputs 7 V CC = 3V; V I = 2. 75 135 µa I X I PU/P V CC = to 3.6V; V CC = 3.6V ±500 Current into an output in the igh state when V O > V CC V O = 5.5V; V CC = 3. 50 125 µa Power up/down 3-State output V CC 1.2V; V O = 0.5V to V CC ; V I = or V CC ; current 3 O/O = on t care µa 1 ±100 µa I OZ 3-State output igh current V CC = 3.6V; V O = 3.; V I = V I or V I 0.5 5 I OZ 3-State output ow current V CC = 3.6V; V O = 0.5V; V I = V I or V I 0.5 5 I CC V CC = 3.6V; Outputs igh, V I = or V CC, I O = 0 0.07 0.12 I CC uiescent supply current V CC = 3.6V; Outputs ow, V I = or V CC, I O = 0 4.0 6 ma I CCZ V CC = 3.6V; Outputs isabled; V I = or V CC, I O = 0 6 0.07 0.12 I CC Additional supply current per input pin 2 V CC = 3V to 3.6V; One input at V CC -0.6V, Other inputs at V CC or µa 0.1 0.2 ma NOTS: 1. All typical values are at V CC = 3.3V and T amb = 25 C. 2. This is the increase in supply current for each input at the specified voltage level other than V CC or. 3. This parameter is valid for any V CC between and 1.2V with a transition time of up to 10msec. From V CC = 1.2V to V CC = 3.3V ± 0.3V a transition time of 100µsec is permitted. This parameter is valid for T amb = 25 C only. 4. Unused pins at V CC or. 5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 6. I CCZ is measured with outputs pulled to V CC or. 7. This is the bus hold overdrive current required to force the input to the opposite logic state. 1999 Sep 23 6

AC CARACTRISTICS = ; t R = t F = 2.5ns; C = 50pF; R = 500Ω; T amb = 40 C to +85 C. IMITS SYMBO PARAMTR WAVFORM V CC = 3.3V ±0.3V V CC = 2.7V UNIT t P t P t P t P t PZ t PZ t PZ t PZ Propagation delay nx to nx Propagation delay n to nx Output enable time to igh and ow level Output disable time from igh and ow evel NOT: 1. All typical values are at V CC = 3.3V and T amb = 25 C. AC STUP RUIRMNTS = ; t R = t F = 2.5ns; C = 50pF; R = 500Ω; T amb = 40 C to +85 C. 2 1 4 5 4 5 MIN TYP 1 MAX MAX 0.5 0.5 0.5 0.5 0.1 0.1 0.1 0.1 2.5 2.5 3.0 3.0 3.5 3.2 3.5 3.2 IMITS SYMBO PARAMTR WAVFORM V CC = 3.3V ±0.3V V CC = 2.7V UNIT t S () t S () t h () t h () t W () Setup time nx to n old time nx to n n pulse width igh 3 3 4.6 4.0 5.1 4.6 5.4 4.9 5.4 5.1 5.1 4.3 5.8 4.3 6.6 5.5 5.7 5.0 MIN TYP MIN 1.5 2.0 1.0 1.5 0.1 0.2 0 0 1.0 2.0 1.0 2.0 1 1.5 0.5 1.5 ns ns ns ns ns ns ns AC WAVFORMS For all waveforms, = 1.5V. n 2.7V nx ÉÉÉ ÉÉ 2.7V ÉÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉ nx t w () t P t P V O n t s () t h () t s () t h () 2.7V V O SW00011 Waveform 1. Propagation elay, atch nable to Output, and atch nable Pulse Width NOT: The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 3. ata Setup and old Times SW00013 2.7V 2.7V nx t P t P no t PZ t PZ nx V O nx V O V O -0.3V V O SW00012 Waveform 2. Propagation elay for ata to Outputs SW00014 Waveform 4. 3-State Output nable time to igh evel and Output isable Time from igh evel 1999 Sep 23 7

2.7V no t PZ t PZ 3V nx V O +0.3V V O SW00015 Waveform 5. 3-State Output nable Time to ow evel and Output isable Time from ow evel TST CIRCUIT AN WAVFORMS V CC 6V t W 90% 90% AMP (V) PUS GNRATOR V IN.U.T. V OUT R OPN NGATIV PUS 10% 10% t T (t F ) t T (t R ) R T C Test Circuit for 3-State Outputs SWITC POSITION TST SWITC t PZ /t PZ t PZ /t PZ 6V t P /t P open R POSITIV PUS 90% 90% t T (t R ) t T (t F ) 10% t 10% W = 1.5V Input Pulse efinition AMP (V) FINITIONS R = oad resistor; see AC CARACTRISTICS for value. C = oad capacitance includes jig and probe capacitance; see AC CARACTRISTICS for value. R T = Termination resistance should be equal to Z OUT of pulse generators. INPUT PUS RUIRMNTS FAMIY Amplitude Rep. Rate t W t R t F 74VT16 2.7V 10Mz 500ns 2.5ns 2.5ns SW00003 1999 Sep 23 8

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 1999 Sep 23 9

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1 1999 Sep 23 10

NOTS 1999 Sep 23 11

ata sheet status ata sheet status Product status efinition [1] Objective specification Preliminary specification Product specification evelopment ualification Production This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. efinitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. imiting values definition imiting values given are in accordance with the Absolute Maximum Rating System (IC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. xposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. isclaimers ife support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 ast Arques Avenue P.O. Box 3409 Sunnyvale, California 94088 3409 Telephone 800-234-7381 Copyright Philips lectronics North America Corporation 1999 All rights reserved. Printed in U.S.A. ate of release: 09-99 ocument order number: 9397 750 06507 1999 Sep 23 12