- Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1
Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2
Floating-gate transistor (FAMOS) Source Floating gate Gate Drain D t ox G n + Substrate p t ox n + S (a) Device cross-section (b) Schematic symbol Floating-Gate Transistor Programming 20 V 0 V 5 V 20 V 10 V 5 V 5 V 0 V 2.5 V 5 V S D S D S D Avalanche injection. Removing programming voltage leaves charge trapped. Programming results in higher V T. 3
Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide n + source programming p-substrate n + drain Flash Operation 12 V S cell G D 0 V array 0 1 WL 0 12 V G 6 V 12 V S D 12 V 0 V 0 1 WL 0 0 V WL 1 0 V WL 1 Erase open 5 V G 1 V open 5 V 0 1 WL 0 6 V 0 V Write S D 0 V 0 V WL 1 Read 1 V 0 V 4
Flash Memories Applications Performance Type of Flash memory Code Storage Program storage for - Cellular Phone - DVD - Set TOP Box BIOS for - PC and peripherals Important : High speed random access Byte programming Acceptable : Slow programming Slow erasing NOR Intel / Sharp AMD / Fujitsu / Toshiba DINOR Mitsubishi File Storage Small form factor card for - Digital Still Camera - Silicon Audio - PDA... etc Mass storage as - Silicon Disk Drive Important : High speed programming High speed erasing High speed serial read Acceptable : Slow random access NAND Toshiba / Samsung AND Hitachi SanDisk: NOR Flash Memories NOR SanDisk AND NAND Bit line(metal) Bit line /Source line(metal) Word line(poly) Contact Erase gate(poly) Word line(poly) Word line(poly) Word line(poly) Source line (Diff. Layer) Sub Bit line (Diff. Layer) 10F 2 Unit Cell Cell 9F 2 Unit Cell Unit Cell 8F 2 Unit 4F 2 Source line (Diff. Layer) Source line (Diff. Layer) From Ken Takeuchi Simplest wiring Smallest area 5
NAND Flash Bit line (Al) Select 1 (poly) Word line (poly) Select 2 (poly) Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended 6
6-transistor CMOS SRAM Cell WL M 2 M 4 Q Q M M 5 6 M 1 M 3 CMOS SRAM Analysis (Write) WL M 4 Q 0 Q 1 M 6 M 5 M 1 C bit C bit 7
Cell Writeability 1.2 1 Voltage rise [V] 0.8 0.6 0.4 0.2 0 0 0.5 1 1.2 1.5 2 Cell Ratio (CR) 2.5 3 CMOS SRAM Analysis (Read) WL M 4 Q 0 M 6 M 5 Q 1 M 1 1 0 8
Cell Stability 0.5 Cell voltage [V] 0.4 0.3 0.2 0.1 0 0 0.5 1 Pull-up Ratio 1.5 1.8 2 6T-SRAM Layout M2 M4 Q Q M1 M3 M5 M6 GND WL 9
Resistance-load SRAM Cell WL R L R L M3 Q Q M4 M1 M2 Static power dissipation -- Want R L large Bit lines precharged to to address t p problem 3-Transistor DRAM Cell 1 2 WWL RWL WWL RWL M1 X M3 M2 X 1 -V T C S 2 -V T V No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn 10
3T-DRAM Layout 2 1 GND RWL M3 M2 WWL M1 1-Transistor DRAM Cell WL WL Write "1" Read "1" M1 C S X GND V T C /2 sensing /2 Write: C S is charged or discharged by asserting WL and. Read: Charge redistribution takes places between bit line and storage capacitance C S V = V V PRE = ( V BIT V PRE )----------------------- C S + C Voltage swing is small; typically around 250 mv. 11
DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than. 1-T DRAM Cell Capacitor Metal word line n + n + poly SiO 2 Field Oxide M1 word line poly Inversion layer induced by plate bias (a) Cross-section Diffused bit line Polysilicon Polysilicon plate gate (b) Layout Used Polysilicon-Diffusion Capacitance Expensive in Area 12
SEM of poly-diffusion capacitor 1T-DRAM Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Storage electrode Isolation Storage Node Poly 2nd Field Oxide Si Substrate Trench Cell Stacked-capacitor Cell 13
Periphery Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder 14
Dynamic Decoders Precharge devices GND GND WL 3 WL 3 WL 2 WL 2 WL 1 WL 1 WL 0 WL 0 A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder Propagation delay is primary concern A NAND decoder using 2-input predecoders WL 1 WL 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 2 A 3 A 2 A 3 A 2 A 3 A 2 A 3 A 1 A 0 A 0 A 1 A 3 A 2 A 2 A 3 Splitting decoder into two or more logic layers produces a faster and cheaper implementation 15
4 input pass-transistor based column decoder 0 1 2 3 A 0 A 1 2 input NOR decoder S 0 S 1 S 2 S 3 D dvantage: speed (t pd does not add to overall memory access time) only 1 extra transistor in signal path sadvantage: large transistor count 4-to-1 tree based column decoder 0 1 2 3 A 0 A 0 A 1 A 1 D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches 16
Decoder for circular shift-register WL 0 WL 1 WL 2 R R R... Memory Timing: Definitions Read Cycle READ Read Access Read Access Write Cycle WRITE Data Valid Write Access DATA Data Written 17
Memory Timing: Approaches MSB LSB Address Bus Row Address Column Address RAS CAS Address Bus Address Address transition initiates memory operation RAS-CAS timing DRAM Timing Multiplexed Adressing SRAM Timing Self-timed Address Transition Detection A 0 DELAY t d ATD ATD A 1 DELAY t d A N-1 DELAY t d... 18
DRAM Timing Sense Amplifiers t p = C ---------------- V I av make V as small as possible large small Idea: Use Sense Amplifer small transition s.a. input output 19
Differential Sensing - SRAM PC y M3 M4 y EQ x M1 M2 SE M5 x x SE x WL i (b) Doubled-ended Current Mirror Amplifier SRAM cell i Diff. x Sense x Amp y y D D x y SE y x (a) SRAM sensing scheme. (c) Cross-Coupled Amplifier Latch-Based Sense Amplifier EQ SE SE Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. 20