COMPACT I-V MODEL FOR AMORPHOUS OXIDE TFTs Benjamin Iñiguez 1, Alejandra Castro-Carranza 1, Muthupandian Cheralathan 1, Slobodan Mijalkovic 2, Pedro Barquinha 3, Rodrigo Martins 3, Elvira Fortunato 3, Magali Estrada 4, Antonio Cerdeira 4 1 Department of Electronic Engineering (DEEiA), Universitat Rovira I Virgili,Tarragona, Catalonia, Spain. E-mail: benjamin.iniguez@urv.cat 2 Silvaco Europe Ltd, St ives, Cambridshire, UK 3 CENIMAT-I3N, FCT-Universidade Nova de Lisboa, Caparica, Portugal 4 Centro de Investigación y Estudios Avanzados del Instituto Politécnico Nacional (CINVESTAV-IPN), 07360 Mexico D.F., Mexico.
OUTLINE Introduction Experimental and simulation tasks AOS TFT DC Model Implementation of the model in EDA Tools Conclusions 2
1. Introduction AOS TFTs The large scale manufacturing of a-si:h TFTs forms the basis of the active matrix flat panel display industry. Poly-Si TFTs facilitate the integration of electronic circuits into portable active matrix liquid crystal displays, and are increasingly used in active matrix organic light emitting diode (AMOLED) displays for smart phones. The recently developed Amorphous Oxide Semiconductor Thin Film Transistors (AOS-TFTs) have received much attention since are seen as an alternative option to poly-si and a-si:h for AMOLED TV and large AMLCD TV applications, respectively. High mobility High on/off ratio Low processing temperatures Possibility of fabrication on large areas and flexible substrates 3
1. Introduction Among AOS materials, amorphous In-Ga-Zn-O (a-gizo) and more recently Hf-In-Zn-O (HIZO) TFTs have been systematically studied. However, they need to be well understood and optimized since problems in these transistors are present, such as: Problems related to the stability with bias. Temperature and illumination effects. In some cases, a parallel displacement of the transfer curves is observed, while in others, a hump or deformation on the curve appears after DC bias stress. Another pending task is the development of models suitable for designing with these transistors, which are frequently described using the same expressions as for MOS transistors 4
1. Introduction Objective In this work we present MOTFT, a compact model for AOS TFTs valid also for GIZO and HIZO devices with and without gate bias-stress effect (hump). It is based on the Unified Model and Extraction Method (UMEM) [*], which has been adapted to different types of TFTs. We present the MOTFT Verilog-A code implementation in Electronic Design Automation tools (EDA). It is shown that a good agreement is obtained with experimental data. [*] -A. Cerdeira, M. Estrada, R. Garcia, A. Ortiz-Conde, and F.J.G. Sanchez, Solid-St. Electron, vol.45, no. 7, pp.1077-1080 (2001). -M. Estrada, I.Mejía, A. Cerdeira, J. Pallarès, L. F. Marsal, and B. Iñiguez, Solid-State Electron., vol.52, no.5, pp.787 794, (2008). 5
2. Experimental and simulation tasks Experimental data were obtained and device simulation was performed in Silvaco ATLAS were used to validate the model. (a) a-gizo TFT structure (b) Fabricated device [*]. AOS TFT cross section used in simulations [**] The active layer is n-type, with impurity concentration NB=1 10 16 cm 3 [*] G. Bahubalindruni, et al. 20 th Telecommunications forum TELFOR 2012, Serbia Belgrade. [**] M. Estrada, A. Cerdeira, B. iñiguez, Microelectron Reliab 52, pp.1342-5 (2012). 6
3. AOS TFT model UMEM Unified Model and Parameter Extraction Method (UMEM) where the mobility is calculated by solving: Poisson s equation assuming an exponential DOS and Qfree<<Qloc Free carrier transport in AOS TFTs Multiple Trapping and Release Estrada, M., Cerdeira, A., Puigdolers, J., et al.: Accurate modeling and parameter extraction method for organic OTFTs, Solid-State Electron., 2005, 49, (6), pp. 1009 1016. M.Estrada, I.Mejía, A.Cerdeira, J.Pallares,L.F.Marsal, B.Iñiguez; Mobility model for OTFTs made of different materials Sol State Electron, 52(2008)787-794 M. Shur and M. Hack, Physics of amorphous silicon based alloy field-effect transistors, J. Appl. Phys., vol. 55, pp. 3831 (1984). 7
3. AOS TFT model Above Threshold ABOVE THRESHOLD Channel length modulation I, VV ab GS DSiFET 1 W VVVV GS T DS C m /1 m L W V DS 1R CVV ifet GS T 1 L ( VV GS T) Sharpness of the knee region Saturation parameter where Empirical parameters defining the variation of mobility with Vgs above threshold a VGS V T 0 FET a Vaa 8
3. AOS TFT DC model Above Threshold In [*] extraction procedure based on the properties of the integral function H(VGS). was developed and applied, first, to a-si:h devices model : V IVdV () 1 a DS GS GS 0 above () GS IV DS () GS HV GS max W CV i Vaa L slope D1 1 a 1 a 2 V GS T V Parameters extracted from the transfer curve in linear regime, and with the slope and the abscissa intercept of the H function. Now we can model the field dependent mobility μ FET Subsequently, parameters R, m, λ, α are extracted as indicated in: -A. Cerdeira, M. Estrada, R. Garcia, A. Ortiz-Conde, and F.J.G. Sanchez, Solid-St. Electron, vol.45, no. 7, pp.1077-1080 (2001). 9
SUBTHRESHOLD 3. AOS TFT model Subthreshold To model the subthreshold region of devices, the drain current can be described as [*]: γ b depends on the temperature T and on the characteristic temperature of the deep states distribution (T 2 ) 2T b 2 2 T Vbb is obtained as indicated in [**] [*] L. Resendiz, M. Estrada, and A. Cerdeira, Solid State Electron 2003;47:135 1358. [**] A. Cerdeira, M. Estrada, B. S. Soto-Cruz, and B. Iñíguez, Microelectron Reliab vol. 52, pp.2532-2536 (2012). 10
T 1 3. AOS TFT model Distribution of localized states in the mobility band Distribution of acceptor type traps Conduction band energy EE C E C gaat 0expg ad 0exp kt 1 kt 2 a2 T2 T 2 T Tail acceptor density of states Deep acceptor density of states b 2 2 The V GS variation above threshold modifies the population of the tail states. The V GS variation in subthreshold modifies the population of the deep states. 11
3. AOS TFT model Subthreshold and above Threshold regions To join the subthreshold and the above threshold regions, an expression I t1 is obtained where the tanh function is applied to sew Iab(VGS, VDS) and Ibt(VGS, VDS). 1E-4 I DS (A) 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 Measurement Iab Ibt It1 Typical non-stress transfer characteristic of a HIZO TFT in linear regime. W=160 m. L=20 m. V DS =0.1 V Experimental data is compared with I t1, which is composed of the above threshold region (V GS > V T ), modeled by Iab, and the subthreshold region, modeled by Ibt. 1E-13-10 -5 0 5 10 V GS V T 12
DEEP SUBTHRESHOLD 3. AOS TFT model Deep subthreshold Well below V T, in deep subthreshold regime where I t1 can no longer model the drain current, diffusion becomes the predominant charge transport mechanism and the current shows an exponential dependence with the gate voltage for V GS which can be expressed as [*]: The region where a hump may be present in stressed devices corresponds to a part of the deep subthreshold region where the slope is different due to the presence of the back interface charges, can be represented by another exponential behavior with an inverse slope S 2 where (V FB + V 2 ) is the gate voltage below V T where the hump starts. [*] A. Cerdeira, M. Estrada, B. S. Soto-Cruz, and B. Iñíguez, Microelectron Reliab vol. 52, pp.2532-2536 (2012). 13
3. AOS TFT model Deep subthreshold To sew the deep subthreshold region (I s1 ) and the hump (I s2 ), an expression I snl is used And then an expression It2 will describe the entire subthreshold region by joining the subthreshold (Ibt) and the deep subthreshold (Isnl) 14
3. AOS TFT model Deep subthreshold Finally an expression to describe the total I DS is obtained 1E-5 1E-7 I DS (A) 1E-9 1E-11 1E-13 Measurement It1 It2 MOTFT total I DS 1E-15-12 -6 0 6 12 Non-stressed transfer characteristic of a HIZO TFT in linear regime (V DS =0.1 V) modeled by MOTFT. V GS 15
3. AOS TFT model Temperature dependence 10-4 10-5 10-6 320K 10-4 10-5 360K 10-6 I DS ( A ) 10-7 10-8 10-9 10-10 10-11 10-12 Measurements V DS = 1 V V DS = 10 V MOTFT 0 2 4 6 8 V GS (V) I DS ( A ) 10-7 10-8 10-9 10-10 10-11 10-12 10-13 Measurements V DS = 1 V V DS = 10 V MOTFT 2 4 6 8 V GS (V) a and b decrease with increasing T T2 still increases with increasing T VT increases linearly with increasing T 20/06/13 GIZO TFT W=160 μm L=20 μm
4. Implementation of UBCM in EDA tools SMASH (from DOLPHIN) is an all-in-one mixed signal, mullti level, multi-language simulator. Mixed Signal Analog and continuous signal and discrete-logic signals Model validation on Mathcad Writting of Verilog-A code Implementation SMASH DC Simulation 17
4. Implementation of UBCM in EDA tools 10-4 10-6 I DS ( V DS = 1 V ) 10-8 10-10 10-12 10-14 Measurement I bt + above threshold current Inclusion of I s2 MOTFT in Mathcad MOTFT Verilog-A 10-16 0 5 10 15 20 V GS (V) GIZO TFT W=160 μm L=20 μm Vds=1 V 18
4. Implementation of UBCM in EDA tools SMASH 10-3 10-5 I DS ( V DS = 20 V ) 10-7 10-9 10-11 10-13 Measurement MOTFT in Mathcad MOTFT Verilog-A 10-15 0 5 10 15 20 V GS (V) GIZO TFT W=160 μm L=20 μm Vds=20 V 19
4. Implementation of UBCM in EDA tools SMASH 6.0x10-4 Measurements MOTFT in Mathcad MOTFT Verilog-A V GS = 20 V 4.0x10-4 V GS = 16 V I DS (A) 2.0x10-4 V GS = 12 V 0.0 V GS = 4 V 0 5 10 15 20 V GS (V) GIZO TFT W=160 μm L=20 μm 20
5. Conclusions MOTFT, the UMEM-based compact model for amorphous oxide semiconductor TFTs is used to model the drain-to-source current of GIZO and HIZO TFTs. These devices might show typically a gate bias-stressed hump in their transfer characteristics which can be modeled by MOTFT. For validation, experimental transfer and output characteristics of GIZO and HIZO TFT was compared with MOTFT, showing a good agreement even at different temperatures, which makes it useful for circuit design applications. We implemented the MOTFT Verilog-A code in Electronic Design Automation tools (EDA) and it is shown that a good agreement is obtained with experimental data. 21
AKNOWLEDGMENTS This research is supported by contract Thin Oxide TFT SPICE Model (T12129S), with Silvaco Inc. 22
AKNOWLEDGMENTS THANK YOU FOR YOUR ATTENTION 23