M EEA Systèmes Microélectroniques Polytech montpellier MEA 4 Analog ntegrated Circuits Design Chapter Basic and Advanced Current Sources Pascal Nouet / 04-05 nouet@lirmm.fr http://www.lirmm.fr/~nouet/homepage/lecture_ressources.html ecture material download http://www.lirmm.fr/~nouet/homepage/lecture_ressources.html
ntroduction Analog ntegrated Circuits are based on elementary stages oltage references Current mirrors Current sources Amplifier stages Main characteristics of a current mirror Current flow to ss (ground) or from Coicient of recopy Quality of recopy High put resistance ange of put voltages (put dynamic) Outline Elementary current mirror Principle Output resistance Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources Overview of advanced current sources PMOS current sources
Current mirroring principle i S in s Biasing (arge Signal Analysis): is saturated è in ds f( gs ) f( ) T must be saturated to deliver a constant current à Output dynamic: ds Small-Signal Analysis à Output resistance S /g m g m.v gs r ds v T s s dsat µ nc ox in v gs v s r ds i s λ dsat Elementary current mirror: put resistance ds (A) mpact of dsat 5,00E- 0 4,50E- 0 4,00E- 0 g ds (µa /) r ds (MΩ) λ( ) dsat (µa) y 0,0044x in S T s 3,50E- 0 3,00E- 0,50E- 0,00E- 0,50E- 0,00E- 0 gds (µa/) inéaire (gds (µa/)) 5,00E- 0 0,00E+00 ds (µa) 0,00E+00,00E+0 4,00E+0 6,00E+0 8,00E+0,00E+0 ds () 3
Elementary current mirror: put resistance ds (A) mpact of transistor length,40e+0,0e+0 rds (Mohms) y 0,093x +,78 in S T s,00e+0 8,00E+00 6,00E+00 4,00E+00,00E+00 0,00E+00 r ds e ( / µm) (µm) + r 0 dsat (A) (µm) 0,00E+00,00E+0 4,00E+0 6,00E+0 8,00E+0,00E+0 ds () Elementary current mirror: put resistance ds (A) mpact of transistor size (/) 4,5 in S 4,0 rds (Mohms) T s 3,5 3,0,5,0,5,0 0,5 0,0 0 0 0 30 40 50 / ds () 4
Elementary current mirror: summary mpact of dsat Output resistance is divided by two when current is multiplied by two mpact of transistor size Output resistance doubled when transistor length is multiplied by two (constant /) in T S s Useful equations orking with constant and transistor length General case à r ds α i s v s r ds ds ds λ( ) dsat (A) r ds e( / µm) (µm) + r 0 dsat (A) Outline Elementary current mirror Elementary stages for increased put resistance Degenerated source current mirror Cascode current mirror Other elementary current mirrors Elementary current sources Overview of advanced current sources PMOS current sources 5
Degenerated source current mirror i S in S /g m v g g m.v gs r ds T v s v s s s s s arge-signal Analysis T always saturated Output dynamic à saturation of T Small-Signal Analysis Output resistance v i S s dsat µ C n ox > + s S S in rds + in ( g ) m s Degenerated source current mirror mpact of s 5,0 r (MOhms) 0,0 5,0 y 0,994x + 3,467 50µA T S 0,0 s s 5,0 0,0 r r ds + + g m r ds ( ) s g m r ds λ n λ n 000 0 5 0 5 0 s(kω) 5 6
Outline Elementary current mirror Elementary stages for increased put resistance Degenerated source current mirror Cascode current mirror Other elementary current mirrors Elementary current sources Overview of advanced current sources PMOS current sources Cascode current mirror i S in S S /g m3 g m4.v gs4 r ds4 T 3 T 4 vs v g4 v s4 v g T /g m g m.v gs r ds v s d d d3 d 4 in arge-signal Analysis T and T 3 are saturated, T also Output dynamic à saturation of T 4 Small-Signal Analysis Output resistance s dsat µ n C ox S v i S S > + tn g in r r m4 ds ds4 7
Cascode current mirror ds (A) mpact of / 800 700 600 500 400 300 00 00 0 r (MOhms) / 0 00 00µA S T 3 T 4 T ds () Outline Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources Overview of advanced current sources PMOS current sources 8
ilson current mirror i x in S /g m3 v gs4 g m4.v gs4 r ds4 T 3 T 4 vx T g m.v gs r ds v gs /g m d d d 3 d 4 Similar performance to cascode mirror s dsat µ n C ox Substrate ect: in v in S > tn + S i s vs ( gm4 + gs4 ) rds rds4 i s g m4 r ds r ds4 PMOS Current Mirrors Every NMOS current mirror has a PMOS dual Caracteristics are identical and easy to transpose: smin à smax, r T S S T T T S T T 3 T 4 T 3 T 4 in S S S r r ds in in in r g m r ds r ds 9
Non-symetrical mirrors Different ratio / may be used in the put branch (generally X> à put current higher than reference current) Same for all transistors means current proportionnal to /: in S in S in S T 3 T 4 s T 3 T 4 s T s T T : X : X : X Multiple puts current mirrors r S S One reference branch may be connected to as many put branches as recessary for the application Each put may deliver a different ratio of current Each put may have a different put resistance in > λ S X ; n in S nx S S ; r > n λ n in X. in S S n S nx nx S n n in S S n n r r S S S S in X >. + >. λ λ n n tn + tn in X. in 0
Overview of put resistance of elementary current mirors,00e+0 (Ω),00E+09,00E+08 Miroir simple SD SD Cascode ilson,00e+07,00e+06,00e+05,00e+04,00e+03 0,00 0,50,00,50,00,50 3,00 S 3,50 ( ) Outline Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources esistance ing Transistor ing mpact of and T C Overview of advanced current sources PMOS current sources
From current mirrors towards current sources Analog ntegrated Circuits are based on elementary stages oltage references Current mirrors Current sources Amplifier stages f() Current flowing through ground or from in S T T s deal versus actual current sources S ö OUT 0 Smin ø Output esistance and dynamics S Sensitivity to and T C s0 Power consumption S min
esistance ing NMOS current sources > T T 3 T 4 > tn + T 3 T 4 > tn + : X T : X T : X Sizing Output dynamics à Output current ( ) à / of T (T 4 ) X à eference current ( in ) à / of (T 3 ), Output resistance calculation (e.g. ilson Current Source ) i x /g m3 v gs4 g m4.v gs4 r ds4 T 3 T 4 > tn + g m.v gs r ds v gs /g m v x T ( ) r i ds p g mv gs p + rds + gm3 gmrds p vg4 p. i( p) p + rds + gm3 vgs4 : X i ( + A) v ( + A) x ( + g ) gs gm vgs Avgs m ix p gm ix vx + rds4 gm ( vx & + rds4 + ' gm r + gm ( i g v ) x m4 gs4 ( + A) gm4 % rds4 # ix g m $ ( + A) rds ( + gm p ) rds 3
Transistor ing NMOS Current Sources T p T p T p > T T 3 T 4 > tn + T 3 T 4 > tn + T T : X : X : X Output dynamics à Output current ( ) à / of T (T 4 ) X à eference current ( in ) à / of (T 3 ), T p Outline Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources esistance ing Transistor ing mpact of and T C Overview of advanced current sources PMOS current sources 4
mpact of S ö OUT 0 ø OUT min fixe esistance ing v (> ) i T /g m v g m.v r ds p µ ncox + ( T tn T ) i Δ Δ g m i. v g g m m ( + g ) v + g g m m m ( + gm p ) p p Δ v 5
Transistor ing v T 3 (> ) /g m3 i T /g m v g m.v r ds µ nc µ pc + ox ox ( T tn 3 3 T ) ( ) tp i g g m m Δ Δ g g + g m3 m3 i. v g m m + 3 g g m3 m + 3 + v + g Δ 3 m3 v mpact of on Current Sources (A) Δ Δ, T T 3 Δ Δ,77 T () 6
mpact of on Current Sources (A) Δ Δ, T Δ Δ,55 T 4 T 3 T () esistance ing and temperature An increase in temperature reduces the saturation current of a transistor,06e+0 (µa),04e+0,0e+0 Polarisation par résistance (> ) T,00E+0 9,80E+0 9,60E+0-0,08 %/ C 9,40E+0 9,0E+0 Temp.( C ) - 40,00-0,00 0,00 0,00 40,00 60,00 80,00 7
esistance ing and temperature esistance may also change with temperature ( TCT. ),5E+0 (µa) p p0 + ésistance fixe,0e+0 TCe- 3 / C,05E+0 (> ) T,00E+0 9,50E+0 9,00E+0 8,50E+0-0,08 %/ C -0,08%/ C -0,57 %/ C 8,00E+0 Temp.( C ) - 40,00-0,00 0,00 0,00 40,00 60,00 80,00 Transistor ing and temperature,0e+0 NMOS et PMOS exhibits same phenomenon (µa),5e+0-0, %/ C Polarisation par constante Polarisation par avec TCe- 3 / C Polarisation par PMOS T 3 (> ) T,0E+0,05E+0,00E+0 9,50E+0 9,00E+0-0,08 %/ C 8,50E+0-0,57 %/ C 8,00E+0 Temp.( C ) - 40,00-0,00 0,00 0,00 40,00 60,00 80,00 8
Cascode Source and temperature Feedback may improve results,5e+0 (µa),0e+0,05e+0 Cascode avec et TCe- 3 / C Polarisation par avec TCe- 3 / C Cascode pplarisé par PMOS 0,036 %/ C T 4 T 3 T,00E+0 9,50E+0 9,00E+0 8,50E+0-0,036 %/ C -0,57 %/ C Temp.( C ) - 40,00-0,00 0,00 0,00 40,00 60,00 80,00 T 3 T 4 T 3 T Outline Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources Overview of advanced current sources -independent current sources -independent and increased put resistance ncreasing put dynamic range PMOS current sources 9
-independent current sources Principle: a resistor implement a feedback that tends to reduce current variations Sizing methods Choice of and α (generally, 4, 9 or 6) is not sensitive to variations Assuming identical currents in and T leads to an expression of depending of T 4, T 5 et T 4 T 5 5 5 α 4 4 4 µ pcox 4 & α # $! % α + α " B T A T 3 -independent current sources Other configurations Dual circuit in PMOS (current from ) T 4 ncreased stability by reduction of ds and ds5 Power consumption à asymmetrical current mirror T 3 T 8 5 5 α 4 4 T 4 B T 5 D T α T 3 T 6 C T A 0. T 7 0
- independent and increased put resistance -independent à, T 4 and T 5 to set value of independently of educed power consumption à asymmetrical current mirror High-voltage operation à T 3 and T 6 are optional T 4 B T T 5 D T 3 T 6 C A 0. T 7 ncreased à Cascode put à Problem à put range of operation T c c T 7c Outline Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources Overview of advanced current sources -independent current sources -independent and increased put resistance ncreasing put dynamic range PMOS current sources
ncreasing put dynamic range Principle S T 3 s T ds gs3 ds d3 gs gs ds s3. tn +. +. tn s3 + tn Trade-off between put range of operation and put resistance ncreasing put dynamic range mplementation: large-swing cascode current source with -independent reference current T 6 T 7 T 8 7 7 6 α 6 7 6 ( α > ) + avec B 6 α 7 A T 9 T 5 T 3 T C 3 5 4 4 3 5 9 9
ncreasing put dynamic range: alternative configurations 5 T 6 T 7 T 8 T 6 T 7 T 8 B A C T 4 T 6 T 7 B T 8 T 9 T 5 A 0. C T 4 T 3 T T 9 T 5 T 3 T Current sources Elementary current mirror Elementary stages for increased put resistance Other elementary current mirrors Elementary current sources Overview of advanced current sources PMOS current sources 3
Current sources Overview of main characteristics mpact of Output resistance Output range of operation Basic current source ±5% 65kΩ > 0,8 -independent current source ±,3% 500kΩ > 0,9 -independent current source with cascoded put ±0,0% 80MΩ > arge-swing - independent cascoded current source ±9% ±,5% 3,54MΩ 4,88MΩ > 0,3 > 0,3 Contrôle des connaissances 4 Novembre : 3 heures Analyse de ay Source de tension Dimensionnement théorique Ajustement fin Schéma petit-signal Sensibilité à Source de courant Dimensionnement théorique Ajustement fin Schéma petit-signal ésistance de sortie 4