8-Kb and 16-Kb SPI Srial CMOS EEPROM Dscription Th CT25080/25160 ar 8 Kb/16 Kb Srial CMOS EEPROM dvics intrnally organizd as 1024x8/2048x8 bits. Thy fatur a 32 byt pag writ buffr and support th Srial Priphral Intrfac (SPI) protocol. Th dvic is nabld through a Chip Slct () input. In addition, th rquird bus signals ar a clock input (), data input () and data output () lins. Th HOLD input may b usd to paus any srial communication with th CT25080/25160 dvic. Ths dvics fatur softwar and hardwar writ protction, including partial as wll as full array protction. Faturs 20 MHz SPI (5 V) Compatibl 1.8 V to 5.5 V Supply Voltag Rang SPI Mods (0,0) & (1,1) 32 byt Pag Writ Buffr Slf timd Writ Cycl Hardwar and Softwar Protction Block Writ Protction Protct 1/4, 1/2 or Entir EEPROM rray Low Powr CMOS Tchnology 1,000,000 Program/Eras Cycls 100 Yar Data Rtntion Industrial and Extndd Tmpratur Rang 8 lad PDIP, IC, TSP and 8 pad TDFN, UDFN Packags Ths Dvics ar Pb Fr, Halogn Fr/BFR Fr, and RoHS Compliant V CC IC 8 V SUFFIX CSE 751BD PDIP 8 L SUFFIX CSE 646 WP V SS PIN CONFIGURTION 1 UDFN 8 HU2 SUFFIX CSE 517W TSP 8 Y SUFFIX CSE 948L TDFN 8* VP2 SUFFIX CSE 511K V CC HOLD PDIP (L), IC (V), TSP (Y), TDFN* (VP2), UDFN (HU2, HU4) PIN FUNCTION UDFN 8 HU4 SUFFIX CSE 517Z * Not rcommndd for nw dsigns WP HOLD CT25080 CT25160 V SS Figur 1. Functional Symbol Pin Nam WP V SS HOLD V CC Function Chip Slct Srial Data Output Writ Protct Ground Srial Data Input Srial Clock Hold Transmission Input Powr Supply Th xposd pad for th TDFN/UDFN packags can b lft floating or connctd to Ground. ORDERING INFORMTION S dtaild ordring and shipping information in th packag dimnsions sction on pag 18 of this data sht. Smiconductor Componnts Industris, LLC, 2012 ugust, 2012 Rv. 8 1 Publication Ordr Numbr: CT25080/D
Tabl 1. BLUTE MXIMUM RTINGS Paramtrs Ratings Units Oprating Tmpratur 45 to +130 C Storag Tmpratur 65 to +150 C Voltag on any Pin with Rspct to Ground (Not 1) 0.5 to V CC + 0.5 V Strsss xcding Maximum Ratings may damag th dvic. Maximum Ratings ar strss ratings only. Functional opration abov th Rcommndd Oprating Conditions is not implid. Extndd xposur to strsss abov th Rcommndd Oprating Conditions may affct dvic rliability. 1. Th DC input voltag on any pin should not b lowr than 0.5 V or highr than V CC + 0.5 V. During transitions, th voltag on any pin may undrshoot to no lss than 1.5 V or ovrshoot to no mor than V CC + 1.5 V, for priods of lss than 20 ns. Tabl 2. RELIBILITY CHRCTERISTI (Not 2) Symbol Paramtr Min Units N END (Not 3) Enduranc 1,000,000 Program / Eras Cycls T DR Data Rtntion 100 Yars 2. Ths paramtrs ar tstd initially and aftr a dsign or procss chang that affcts th paramtr according to appropriat EC Q100 and JEDEC tst mthods. 3. Pag Mod, V CC = 5 V, 25 C. Tabl 3. D.C. OPERTING CHRCTERISTI (V CC = 1.8 V to 5.5 V, T = 40 C to +85 C and V CC = 2.5 V to 5.5 V, T = 40 C to +125 C unlss othrwis spcifid.) Symbol Paramtr Tst Conditions Min Max Units I CC Supply Currnt Rad, Writ, V CC = 5.0 V, opn I SB1 Standby Currnt V IN = GND or V CC, = V CC, WP = V CC, V CC = 5.0 V 10 MHz / 40 C to +85 C 2 m 5 MHz / 40 C to +125 C 2 m 2 I SB2 Standby Currnt V IN = GND or V CC, = V CC, WP = GND, V CC = 5.0 V T = 40 C to +85 C 4 T = 40 C to +125 C 5 I L Input Lakag Currnt V IN = GND or V CC 2 2 I LO Output Lakag Currnt = V CC, T = 40 C to +85 C 1 1 V OUT = GND or V CC T = 40 C to +125 C 1 2 V IL Input Low Voltag 0.5 0.3 V CC V V IH Input High Voltag 0.7 V CC V CC + 0.5 V V OL1 Output Low Voltag V CC > 2.5 V, I OL = 3.0 m 0.4 V V OH1 Output High Voltag V CC > 2.5 V, I OH = 1.6 m V CC 0.8 V V V OL2 Output Low Voltag V CC > 1.8 V, I OL = 150 0.2 V V OH2 Output High Voltag V CC > 1.8 V, I OH = 100 V CC 0.2 V V Tabl 4. PIN CPCITNCE (Not 2) (T = 25 C, f = 1.0 MHz, V CC = +5.0 V) Symbol Tst Conditions Min Typ Max Units C OUT Output Capacitanc () V OUT = 0 V 8 pf C IN Input Capacitanc (,,, WP, HOLD) V IN = 0 V 8 pf 2
Tabl 5..C. CHRCTERISTI Matur Product (T = 40 C to +85 C (Industrial) and T = 40 C to +125 C (Extndd)) (Nots 4, 7) Symbol Paramtr V CC = 1.8 V 5.5 V V CC = 2.5 V 5.5 V T = 40 C to +85 C Min Max Min Max f Clock Frquncy DC 5 DC 10 MHz t SU Data Stup Tim 40 20 ns t H Data Hold Tim 40 20 ns t WH High Tim 75 40 ns t WL Low Tim 75 40 ns t LZ HOLD to Output Low Z 50 25 ns t RI (Not 5) Input Ris Tim 2 2 s t FI (Not 5) Input Fall Tim 2 2 s t HD HOLD Stup Tim 0 0 ns t CD HOLD Hold Tim 10 10 ns t V Output Valid from Clock Low 75 40 ns t HO Output Hold Tim 0 0 ns t DIS Output Disabl Tim 50 20 ns t HZ HOLD to Output High Z 100 25 ns t High Tim 50 20 ns t S Stup Tim 20 15 ns t H Hold Tim 30 20 ns t CNS Inactiv Stup Tim 20 15 ns t CNH Inactiv Hold Tim 20 15 ns t WPS WP Stup Tim 10 10 ns t WPH WP Hold Tim 100 60 ns t WC (Not 6) Writ Cycl Tim 5 5 ms 4. C Tst Conditions: Input Puls Voltags: 0.3 V CC to 0.7 V CC Input ris and fall tims: 10 ns Input and output rfrnc voltags: 0.5 V CC Output load: currnt sourc I OL max /I OH max ; C L = 50 pf 5. This paramtr is tstd initially and aftr a dsign or procss chang that affcts th paramtr. 6. t WC is th tim from th rising dg of aftr a valid writ squnc to th nd of th intrnal writ cycl. 7. ll Chip Slct () timing paramtrs ar dfind rlativ to th positiv clock dg (Figur 2). t H timing spcification is valid for di rvision C and highr. Th di rvision C is idntifid by lttr C or a ddicatd marking cod on top of th packag. For prvious product rvision (Rv. B) th t H is dfind rlativ to th ngativ clock dg. Tabl 6. POWER UP TIMING (Nots 5, 8) Symbol Paramtr Max Units t PUR Powr up to Rad Opration 1 ms t PUW Powr up to Writ Opration 1 ms 8. t PUR and t PUW ar th dlays rquird from th tim V CC is stabl until th spcifid opration can b initiatd. Units 3
Tabl 7..C. CHRCTERISTI Nw Product (Rv D) (T = 40 C to +85 C (Industrial) and T = 40 C to +125 C (Extndd), unlss othrwis spcifid.) (Not 9) V CC = 1.8 V 5.5 V 40 C to +85 C V CC = 2.5 V 5.5 V 40 C to +125 C V CC = 4.5 V 5.5 V 40 C to +85 C Symbol Paramtr Min Max Min Max Min Max Units f Clock Frquncy DC 5 DC 10 DC 20 MHz t SU Data Stup Tim 20 10 5 ns t H Data Hold Tim 20 10 5 ns t WH High Tim 75 40 20 ns t WL Low Tim 75 40 20 ns t LZ HOLD to Output Low Z 50 25 25 ns t RI (Not 10) Input Ris Tim 2 2 2 s t FI (Not 10) Input Fall Tim 2 2 2 s t HD HOLD Stup Tim 0 0 0 ns t CD HOLD Hold Tim 10 10 5 ns t V Output Valid from Clock Low 70 35 20 ns t HO Output Hold Tim 0 0 0 ns t DIS Output Disabl Tim 50 20 20 ns t HZ HOLD to Output High Z 100 25 25 ns t High Tim 80 40 20 ns t S Stup Tim 30 30 15 ns t H Hold Tim 30 30 20 ns t CNS Inactiv Stup Tim 20 20 15 ns t CNH Inactiv Hold Tim 20 20 15 ns t WPS WP Stup Tim 10 10 10 ns t WPH WP Hold Tim 10 10 10 ns t WC (Not 12) Writ Cycl Tim 5 5 5 ms Tabl 8. POWER UP TIMING (Nots 10, 11) Symbol Paramtr Min Max Units t PUR Powr up to Rad Opration 0.1 1 ms t PUW Powr up to Writ Opration 0.1 1 ms 9. C Tst Conditions: Input Puls Voltags: 0.3 V CC to 0.7 V CC Input ris and fall tims: 10 ns Input and output rfrnc voltags: 0.5 V CC Output load: currnt sourc I OL max /I OH max ; C L = 30 pf 10.This paramtr is tstd initially and aftr a dsign or procss chang that affcts th paramtr. 11. t PUR and t PUW ar th dlays rquird from th tim V CC is stabl at th oprating voltag until th spcifid opration can b initiatd. 12.t WC is th tim from th rising dg of aftr a valid writ squnc to th nd of th intrnal writ cycl. 4
Pin Dscription : Th srial data input pin accpts op cods, addrsss and data. In SPI mods (0,0) and (1,1) input data is latchd on th rising dg of th clock input. : Th srial data output pin is usd to transfr data out of th dvic. In SPI mods (0,0) and (1,1) data is shiftd out on th falling dg of th clock. : Th srial clock input pin accpts th clock providd by th host and usd for synchronizing communication btwn host and CT25080/160. : Th chip slct input pin is usd to nabl/disabl th CT25080/160. Whn is high, th output is tri statd (high impdanc) and th dvic is in Standby Mod (unlss an intrnal writ opration is in progrss). Evry communication sssion btwn host and CT25080/160 must b prcdd by a high to low transition and concludd with a low to high transition of th input. WP: Th writ protct input pin will allow all writ oprations to th dvic whn hld high. Whn WP pin is tid low and th WPEN bit in th Status Rgistr (rfr to Status Rgistr dscription, latr in this Data Sht) is st to 1, writing to th Status Rgistr is disabld. HOLD: Th HOLD input pin is usd to paus transmission btwn host and CT25080/160, without having to rtransmit th ntir squnc at a latr tim. To paus, HOLD must b takn low and to rsum it must b takn back high, with th input low during both transitions. Whn not usd for pausing, th HOLD input should b tid to V CC, ithr dirctly or through a rsistor. Functional Dscription Th CT25080/160 dvics support th Srial Priphral Intrfac (SPI) bus protocol, mods (0,0) and (1,1). Th dvic contains an 8 bit instruction rgistr. Th instruction st and associatd op cods ar listd in Tabl 9. Rading data stord in th CT25080/160 is accomplishd by simply providing th RED command and an addrss. Writing to th CT25080/160, in addition to a WRITE command, addrss and data, also rquirs nabling th dvic for writing by first stting crtain bits in a Status Rgistr, as will b xplaind latr. ftr a high to low transition on th input pin, th CT25080/160 will accpt any on of th six instruction op cods listd in Tabl 9 and will ignor all othr possibl 8 bit combinations. Th communication protocol follows th timing from Figur 2. Tabl 9. INSTRUCTION SET Instruction Opcod Opration WREN 0000 0110 Enabl Writ Oprations WRDI 0000 0100 Disabl Writ Oprations RDSR 0000 0101 Rad Status Rgistr WRSR 0000 0001 Writ Status Rgistr RED 0000 0011 Rad Data from Mmory WRITE 0000 0010 Writ Data to Mmory t t CNH t S t WH t WL t H t CNS t SU t H t RI t FI VLID IN t V t V t DIS t HO HI Z VLID OUT HI Z Figur 2. Synchronous Data Timing Status Rgistr Th Status Rgistr, as shown in Tabl 10, contains a numbr of status and control bits. Th RDY (Rady) bit indicats whthr th dvic is busy with a writ opration. This bit is automatically st to 1 during an intrnal writ cycl, and rst to 0 whn th dvic is rady to accpt commands. For th host, this bit is rad only. Th WEL (Writ Enabl Latch) bit is st/rst by th WREN/WRDI commands. Whn st to 1, th dvic is in a Writ Enabl stat and whn st to 0, th dvic is in a Writ Disabl stat. Th BP0 and BP1 (Block Protct) bits dtrmin which blocks ar currntly writ protctd. Thy ar st by th usr with th WRSR command and ar non volatil. Th usr is allowd to protct a quartr, on half or th ntir mmory, by stting ths bits according to Tabl 11. Th protctd blocks thn bcom rad only. 5
Tabl 10. STTUS REGISTER 7 6 5 4 3 2 1 0 WPEN 0 0 0 BP1 BP0 WEL RDY Tabl 11. BLOCK PROTECTION BITS BP1 Status Rgistr Bits BP0 rray ddrss Protctd 0 0 Non No Protction 0 1 25080: 0300 03FF 25160: 0600 07FF Protction Quartr rray Protction 1 0 25080: 0200 03FF 25160: 0400 07FF 1 1 25080: 0000 03FF 25160: 0000 07FF Half rray Protction Full rray Protction Tabl 12. WRITE PROTECT CONDITIONS WPEN WP WEL Protctd Blocks Unprotctd Blocks Status Rgistr 0 X 0 Protctd Protctd Protctd 0 X 1 Protctd Writabl Writabl 1 Low 0 Protctd Protctd Protctd 1 Low 1 Protctd Writabl Protctd X High 0 Protctd Protctd Protctd X High 1 Protctd Writabl Writabl 6
WRITE OPERTIONS Th CT25080/160 dvic powrs up into a writ disabl stat. Th dvic contains a Writ Enabl Latch (WEL) which must b st bfor attmpting to writ to th mmory array or to th status rgistr. In addition, th addrss of th mmory location(s) to b writtn must b outsid th protctd ara, as dfind by BP0 and BP1 bits from th status rgistr. Writ Enabl and Writ Disabl Th intrnal Writ Enabl Latch and th corrsponding Status Rgistr WEL bit ar st by snding th WREN instruction to th CT25080/160. Car must b takn to tak th input high aftr th WREN instruction, as othrwis th Writ Enabl Latch will not b proprly st. WREN timing is illustratd in Figur 3. Th WREN instruction must b snt prior to any WRITE or WRSR instruction. Th intrnal writ nabl latch is rst by snding th WRDI instruction as shown in Figur 4. Disabling writ oprations by rstting th WEL bit, will protct th dvic against inadvrtnt writs. 0 0 0 0 0 1 1 0 Dashd Lin = mod (1, 1) HIGH IMPEDNCE Figur 3. WREN Timing 0 0 0 0 0 1 0 0 Dashd Lin = mod (1, 1) HIGH IMPEDNCE Figur 4. WRDI Timing 7
Byt Writ Onc th WEL bit is st, th usr may xcut a writ squnc, by snding a WRITE instruction, a 16 bit addrss and data as shown in Figur 5. Only 10 significant addrss bits ar usd by th CT25080 and 11 by th CT25160. Th rst ar don t car bits, as shown in Tabl 13. Intrnal programming will start aftr th low to high transition. During an intrnal writ cycl, all commands, xcpt for RDSR (Rad Status Rgistr) will b ignord. Th RDY bit will indicat if th intrnal writ cycl is in progrss (RDY high), or th dvic is rady to accpt commands (RDY low). Pag Writ ftr snding th first data byt to th CT25080/160, th host may continu snding data, up to a total of 32 byts, according to timing shown in Figur 6. ftr ach data byt, th lowr ordr addrss bits ar automatically incrmntd, whil th highr ordr addrss bits (pag addrss) rmain unchangd. If during this procss th nd of pag is xcdd, thn loading will roll ovr to th first byt in th pag, thus possibly ovrwriting prviously loadd data. Following compltion of th writ cycl, th CT25080/160 is automatically rturnd to th writ disabl stat. Tabl 13. BYTE DDRESS Dvic ddrss Significant Bits ddrss Don t Car Bits # ddrss Clock Puls CT25080 9 0 15 10 16 CT25160 10 0 15 11 16 0 1 2 3 4 5 6 7 8 21 22 23 24 25 26 27 28 29 30 31 OPCODE BYTE DDRESS* DT IN 0 0 0 0 0 0 1 0 N 0 D7 D6 D5 D4 D3 D2 D1 D0 Dashd Lin = mod (1, 1) HIGH IMPEDNCE Figur 5. Byt WRITE Timing * Plas chck th Byt ddrss Tabl (Tabl 13) 0 1 2 3 4 5 6 7 8 21 22 23 24 31 32 39 24+(N 1)x8 1.. 24+(N 1)x8 24+Nx8 1 OPCODE 0 0 0 0 0 0 1 0 Dashd Lin = mod (1, 1) BYTE DDRESS* N 0 Data Data Data Byt 1 Byt 2 Byt 3 HIGH IMPEDNCE Figur 6. Pag WRITE Timing DT IN Data Byt N 7..1 0 * Plas chck th Byt ddrss Tabl (Tabl 13) 8
Writ Status Rgistr Th Status Rgistr is writtn by snding a WRSR instruction according to timing shown in Figur 7. Only bits 2, 3 and 7 can b writtn using th WRSR command. Writ Protction Th Writ Protct (WP) pin can b usd to protct th Block Protct bits BP0 and BP1 against bing inadvrtntly altrd. Whn WP is low and th WPEN bit is st to 1, writ oprations to th Status Rgistr ar inhibitd. WP going low whil is still low will intrrupt a writ to th status rgistr. If th intrnal writ cycl has alrady bn initiatd, WP going low will hav no ffct on any writ opration to th Status Rgistr. Th WP pin function is blockd whn th WPEN bit is st to 0. Th WP input timing is shown in Figur 8. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OPCODE DT IN 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 Dashd Lin = mod (1, 1) HIGH IMPEDNCE MSB Figur 7. WRSR Timing t WPS t WPH WP WP Dashd Lin = mod (1, 1) Figur 8. WP Timing 9
RED OPERTIONS Rad from Mmory rray To rad from mmory, th host snds a RED instruction followd by a 16 bit addrss (s Tabl 13 for th numbr of significant addrss bits). ftr rciving th last addrss bit, th CT25080/160 will rspond by shifting out data on th pin (as shown in Figur 9). Squntially stord data can b rad out by simply continuing to run th clock. Th intrnal addrss pointr is automatically incrmntd to th nxt highr addrss as data is shiftd out. ftr raching th highst mmory addrss, th addrss countr rolls ovr to th lowst mmory addrss, and th rad cycl can b continud indfinitly. Th rad opration is trminatd by taking high. Rad Status Rgistr To rad th status rgistr, th host simply snds a RDSR command. ftr rciving th last bit of th command, th CT25080/160 will shift out th contnts of th status rgistr on th pin (Figur 10). Th status rgistr may b rad at any tim, including during an intrnal writ cycl. Whil th intrnal writ cycl is in progrss, th RDSR command will output th full contnt of th status rgistr (Nw product, Rv. D) or th RDY (Rady) bit only (i.., data out = FFh) for prvious product rvision C (Matur product). For asy dtction of th intrnal writ cycl compltion, both during writing to th mmory array and to th status rgistr, w rcommnd sampling th RDY bit only through th polling routin. ftr dtcting th RDY bit 0, th nxt RDSR instruction will always output th xpctd contnt of th status rgistr. 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 OPCODE BYTE DDRESS* 0 0 0 0 0 0 1 1 N 0 HIGH IMPEDNCE Dashd Lin = mod (1, 1) * Plas chck th Byt ddrss Tabl (Tabl 13) Figur 9. RED Timing DT OUT 7 6 5 4 3 2 1 0 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OPCODE 0 0 0 0 0 1 0 1 DT OUT HIGH IMPEDNCE 7 6 5 4 3 2 1 0 Dashd Lin = mod (1, 1) MSB Figur 10. RDSR Timing 10
Hold Opration Th HOLD input can b usd to paus communication btwn host and CT25080/160. To paus, HOLD must b takn low whil is low (Figur 11). During th hold condition th dvic must rmain slctd ( low). During th paus, th data output pin () is tri statd (high impdanc) and transitions ar ignord. To rsum communication, HOLD must b takn high whil is low. Dsign Considrations Th CT25080/160 dvics incorporat Powr On Rst (POR) circuitry which protcts th intrnal logic against powring up in th wrong stat. Th dvic will powr up into Standby mod aftr V CC xcds th POR triggr lvl and will powr down into Rst mod whn V CC drops blow th POR triggr lvl. This bi dirctional POR bhavior protcts th dvic against brown out failur following a tmporary loss of powr. Th CT25080/160 dvic powrs up in a writ disabl stat and in a low powr standby mod. WREN instruction must b issud prior to any writs to th dvic. ftr powr up, th pin must b brought low to ntr a rady stat and rciv an instruction. ftr a succssful byt/pag writ or status rgistr writ, th dvic gos into a writ disabl mod. Th input must b st high aftr th propr numbr of clock cycls to start th intrnal writ cycl. ccss to th mmory array during an intrnal writ cycl is ignord and programming is continud. ny invalid op cod will b ignord and th srial output pin () will rmain in th high impdanc stat. t CD t CD t HD HOLD t HD t HZ HIGH IMPEDNCE Dashd Lin = mod (1, 1) t LZ Figur 11. HOLD Timing 11
PCKGE DIMENONS PDIP 8, 300 mils CSE 646 01 ISSUE SYMBOL MIN NOM MX PIN # 1 IDENTIFICTION D E1 5.33 1 2 b b2 c D 0.38 2.92 0.36 1.14 0.20 9.02 3.30 0.46 1.52 0.25 9.27 4.95 0.56 1.78 0.36 10.16 E 7.62 7.87 8.25 E1 B 6.10 7.87 6.35 2.54 BSC 7.11 10.92 L 2.92 3.30 3.80 TOP VIEW E 2 1 L b2 c b B DE VIEW END VIEW Nots: (1) ll dimnsions ar in millimtrs. (2) Complis with JEDEC MS-001. 12
PCKGE DIMENONS IC 8, 150 mils CSE 751BD 01 ISSUE O SYMBOL MIN NOM MX 1.35 1.75 1 0.10 0.25 b 0.33 0.51 E1 E c D 0.19 4.80 0.25 5.00 E 5.80 6.20 E1 3.80 4.00 1.27 BSC h 0.25 0.50 PIN # 1 IDENTIFICTION L 0.40 1.27 θ 0º 8º TOP VIEW D h 1 θ c b L DE VIEW END VIEW Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) Complis with JEDEC MS-012. 13
PCKGE DIMENONS b TSP8, 4.4x3 CSE 948L 01 ISSUE O SYMBOL MIN NOM MX 1.20 1 0.05 0.15 2 0.80 0.90 1.05 b 0.19 0.30 E1 E c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.65 BSC L 1.00 REF L1 θ 0.50 0.60 0.75 0º 8º TOP VIEW D 2 1 c DE VIEW 1 L1 END VIEW L Nots: (1) ll dimnsions ar in millimtrs. ngls in dgrs. (2) Complis with JEDEC MO-153. 14
PCKGE DIMENONS TDFN8, 2x3 CSE 511K 01 ISSUE D b E E2 PIN#1 IDENTIFICTION PIN#1 INDEX RE 1 D2 L TOP VIEW DE VIEW BOTTOM VIEW SYMBOL MIN NOM MX 0.70 0.75 0.80 1 0.00 0.02 0.05 2 0.45 0.55 0.65 2 3 0.20 REF b 0.20 0.25 0.30 3 D 1.90 2.00 2.10 D2 1.30 1.40 1.50 FRONT VIEW E 2.90 3.00 3.10 E2 1.20 1.30 1.40 0.50 TYP L 0.20 0.30 0.40 Nots: (1) ll dimnsions ar in millimtrs. (2) Complis with JEDEC MO-229. 15
D PCKGE DIMENONS UDFN8, 2x2 CSE 517W 01 ISSUE O D2 DETIL E E2 PIN #1 IDENTIFICTION PIN #1 INDEX RE 1 TOP VIEW DE VIEW BOTTOM VIEW SYMBOL MIN NOM MX 0.45 0.50 0.55 1 0.00 0.02 0.05 b 0.18 0.25 0.30 D 1.90 2.00 2.10 D2 1.50 1.60 1.70 E 1.90 2.00 2.10 E2 0.80 0.90 1.00 0.50 BSC L 0.20 0.30 0.45 L b DETIL Nots: (1) ll dimnsions ar in millimtrs. (2) Complis with JEDEC MO-229. 16
PCKGE DIMENONS UDFN8, 2x3 EXTENDED PD CSE 517Z 01 ISSUE O D b L DP ZE 1.8 x 1.8 E E2 PIN #1 IDENTIFICTION PIN #1 INDEX RE 1 D2 TOP VIEW DE VIEW BOTTOM VIEW SYMBOL MIN NOM MX 0.45 0.50 0.55 1 0.00 0.02 0.05 3 0.127 REF b 0.20 0.25 0.30 0.065 REF DETIL 3 D 1.95 2.00 2.05 D2 1.35 1.40 1.45 FRONT VIEW E 2.95 3.00 3.05 E2 1.25 1.30 1.35 0.50 REF L 0.25 0.30 0.35 Nots: (1) ll dimnsions ar in millimtrs. (2) Rfr JEDEC MO-236/MO-252. 3 0.0-0.05 DETIL 0.065 REF Coppr Exposd 17
ORDERING INFORMTION (Nots 13 16) Dvic Ordr Numbr Spcific Dvic Marking* Packag Typ Tmpratur Rang Lad Finish CT25080HU2I-GT3 S3 UDFN8 I = Industrial ( 40 C to +85 C) NiPdu CT25080HU2E-GT3 S3 UDFN8 E = Extndd ( 40 C to +125 C) NiPdu CT25080HU4I-GT3 S3U UDFN8 EP I = Industrial ( 40 C to +85 C) NiPdu CT25080HU4E-GT3 S3U UDFN8 EP E = Extndd ( 40 C to +125 C) NiPdu CT25080LI-G 25080D PDIP 8 I = Industrial ( 40 C to +85 C) NiPdu CT25080LE-G 25080D PDIP 8 E = Extndd ( 40 C to +125 C) NiPdu CT25080VI-GT3 25080D IC 8, JEDEC I = Industrial ( 40 C to +85 C) NiPdu CT25080VE-GT3 25080D IC 8, JEDEC E = Extndd ( 40 C to +125 C) NiPdu CT25080VP2I-GT3 (Not 17) CT25080VP2E-GT3 (Not 17) S3T TDFN 8 I = Industrial ( 40 C to +85 C) NiPdu S3T TDFN 8 E = Extndd ( 40 C to +125 C) NiPdu Shipping (Not 18) Tap & Rl, 3,000 Units / Rl Tub, 50 Units / Tub Tap & Rl, 3,000 Units / Rl CT25080YI-GT3 S08D TSP 8 I = Industrial ( 40 C to +85 C) NiPdu CT25080YE-GT3 S08D TSP 8 E = Extndd ( 40 C to +125 C) NiPdu CT25160HU2I-GT3 S4 UDFN8 I = Industrial ( 40 C to +85 C) NiPdu CT25160HU2E-GT3 S4 UDFN8 E = Extndd ( 40 C to +125 C) NiPdu CT25160HU4I-GT3 S4U UDFN8 EP I = Industrial ( 40 C to +85 C) NiPdu CT25160HU4E-GT3 S4U UDFN8 EP E = Extndd ( 40 C to +125 C) NiPdu CT25160LI-G 25160D PDIP 8 I = Industrial ( 40 C to +85 C) NiPdu CT25160LE-G 25160D PDIP 8 E = Extndd ( 40 C to +125 C) NiPdu CT25160VI-GT3 25160D IC 8, JEDEC I = Industrial ( 40 C to +85 C) NiPdu CT25160VE-GT3 25160D IC 8, JEDEC E = Extndd ( 40 C to +125 C) NiPdu CT25160VP2I-GT3 (Not 17) CT25160VP2E-GT3 (Not 17) S4T TDFN 8 I = Industrial ( 40 C to +85 C) NiPdu S4T TDFN 8 E = Extndd ( 40 C to +125 C) NiPdu Tap & Rl, 3,000 Units / Rl Tub, 50 Units / Tub Tap & Rl, 3,000 Units / Rl CT25160YI-GT3 S16D TSP 8 I = Industrial ( 40 C to +85 C) NiPdu CT25160YE-GT3 S16D TSP 8 E = Extndd ( 40 C to +125 C) NiPdu 13.ll packags ar RoHS compliant (Lad fr, Halogn fr). 14.Th standard lad finish is NiPdu. 15.For dtaild information and a brakdown of dvic nomnclatur and numbring systms, plas s th ON Smiconductor Dvic Nomnclatur documnt, TND310/D, availabl at www.onsmi.com 16.For additional packag and tmpratur options, plas contact your narst ON Smiconductor Sals offic. 17.Not rcommndd for nw dsign 18.For information on tap and rl spcifications, including part orintation and tap sizs, plas rfr to our Tap and Rl Packaging Spcifications Brochur, BRD8011/D. * Marking for Nw Product (Rv D) 18
ON Smiconductor and ar rgistrd tradmarks of Smiconductor Componnts Industris, LLC (SCILLC). SCILLC owns th rights to a numbr of patnts, tradmarks, copyrights, trad scrts, and othr intllctual proprty. listing of SCILLC s product/patnt covrag may b accssd at www.onsmi.com/sit/pdf/patnt Marking.pdf. SCILLC rsrvs th right to mak changs without furthr notic to any products hrin. SCILLC maks no warranty, rprsntation or guarant rgarding th suitability of its products for any particular purpos, nor dos SCILLC assum any liability arising out of th application or us of any product or circuit, and spcifically disclaims any and all liability, including without limitation spcial, consquntial or incidntal damags. Typical paramtrs which may b providd in SCILLC data shts and/or spcifications can and do vary in diffrnt applications and actual prformanc may vary ovr tim. ll oprating paramtrs, including Typicals must b validatd for ach customr application by customr s tchnical xprts. SCILLC dos not convy any licns undr its patnt rights nor th rights of othrs. SCILLC products ar not dsignd, intndd, or authorizd for us as componnts in systms intndd for surgical implant into th body, or othr applications intndd to support or sustain lif, or for any othr application in which th failur of th SCILLC product could crat a situation whr prsonal injury or dath may occur. Should Buyr purchas or us SCILLC products for any such unintndd or unauthorizd application, Buyr shall indmnify and hold SCILLC and its officrs, mploys, subsidiaris, affiliats, and distributors harmlss against all claims, costs, damags, and xpnss, and rasonabl attorny fs arising out of, dirctly or indirctly, any claim of prsonal injury or dath associatd with such unintndd or unauthorizd us, vn if such claim allgs that SCILLC was nglignt rgarding th dsign or manufactur of th part. SCILLC is an Equal Opportunity/ffirmativ ction Employr. This litratur is subjct to all applicabl copyright laws and is not for rsal in any mannr. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Litratur Distribution Cntr for ON Smiconductor P.O. Box 5163, Dnvr, Colorado 80217 US Phon: 303 675 2175 or 800 344 3860 Toll Fr US/Canada Fax: 303 675 2176 or 800 344 3867 Toll Fr US/Canada Email: ordrlit@onsmi.com N. mrican Tchnical Support: 800 282 9855 Toll Fr US/Canada Europ, Middl East and frica Tchnical Support: Phon: 421 33 790 2910 Japan Customr Focus Cntr Phon: 81 3 5817 1050 19 ON Smiconductor Wbsit: www.onsmi.com Ordr Litratur: http://www.onsmi.com/ordrlit For additional information, plas contact your local Sals Rprsntativ CT25080/D