INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC0 74HC/HCT/HCU/HCMOS Logic Family Specificatio The IC0 74HC/HCT/HCU/HCMOS Logic Package Information The IC0 74HC/HCT/HCU/HCMOS Logic Package Outlines Dual JK flip-flop with reset; negative-edge trigger File under Integrated Circuits, IC0 December 90
FEATURES Output capability: standard I CC category: flip-flops GENERAL DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (ncp) and reset (nr) inputs; also complementary Q and Q outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock traition for predictable operation. The reset (nr) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; T amb = 25 C; t r = t f = TYPICAL SYMBOL PARAMETER CONDITIONS HC HCT UNIT 1 1 C L = pf; 1 18 V CC = 5 V nr to nq, nq 1 17 f max maximum clock frequency 78 7 MHz C I input capacitance.5.5 pf C PD power dissipation capacitance per flip-flop notes 1 and 2 0 0 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in MHz f o = output frequency in MHz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V 2. For HC the condition is V I = GND to V CC For HCT the condition is V I = GND to V CC 1.5 V. ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 90 2
PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 8, 4, 11 1J, 2J, 1K, 2K synchronous inputs; flip-flops 1 and 2 2, 1Q, 2Q complement flip-flop outputs, 5 1Q, 2Q true flip-flop outputs 7 GND ground (0 V) 12, 9 1CP, 2CP clock input (HIGH-to-LOW, edge-triggered) 1, 10 1R, 2R asynchronous reset inputs (active LOW) 14 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig. IEC logic symbol. December 90
Fig.4 Functional diagram. Fig.5 Logic diagram (one flip-flop). FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE nr ncp J K Q Q asynchronous reset L X X X L H toggle H h h q q load 0 (reset) H I h L H load 1 (set) H h I H L hold no change H I I q q Note 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP traition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP traition q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP traition X = don t care = HIGH-to-LOW CP traition December 90 4
DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specificatio. Output capability: standard I CC category: flip-flops AC CHARACTERISTICS FOR 74HC GND = 0 V; t r = t f = ; C L = 50 pf T amb ( C) TEST CONDITIONS SYMBOL PARAMETER 74HC +25 40 to +85 40 to +125 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t THL / t TLH t rem t su t h f max nr to nq, nq output traition time clock pulse width HIGH or LOW reset pulse width LOW removal time nr to ncp set-up time hold time maximum clock pulse frequency 80 1 14 80 1 14 0 12 10 100 17 0 5 52 52 52 7 8 8 7 8 2 2 2 70 85 10 2 27 10 2 27 5 1 2 75 1 100 17 100 17 75 1 125 25 21 4.8 28 0 40 4 0 40 4 5 9 95 1 1 1 90 18 0 0 2 4.0 0 48 41 0 48 41 25 47 40 110 MHz December 90 5
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specificatio. Output capability: standard I CC category: flip-flops Note to HCT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specificatio. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT nk nr ncp, nj UNIT LOAD COEFFICIENT 0.0 0.5 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; t f = t f = ; C L = 50 pf T amb ( C) TEST CONDITIONS 74HCT SYMBOL PARAMETER UNIT V +25 40 to +85 40 to +125 CC (V) WAVEFORMS min. typ. max. min. max. min. max. 45 54 21 45 54 nr to nq, nq 8 48 57 t THL / t TLH output traition time 7 clock pulse width HIGH or LOW 1 9 reset pulse width LOW 11 25 0 t rem removal time nr to ncp 14 8 18 21 t su set-up time 7 25 0 t h hold time 5 2 5 5 f max maximum clock pulse frequency 0 MHz December 90
AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : V M = 50%; V I = GND to V CC. HCT: V M = 1. V; V I = GND to V. Waveforms showing the clock (ncp) to output (nq, nq) s, the clock pulse width, the J and K to ncp set-up and hold times, the output traition times and the maximum clock pulse frequency. (1) HC : V M = 50%; V I = GND to V CC. HCT: V M = 1. V; V I = GND to V. Waveforms showing the reset (nr) input to output (nq, nq) s, the reset pulse width and the nr to ncp removal time. PACKAGE OUTLINES See 74HC/HCT/HCU/HCMOS Logic Package Outlines. December 90 7