Computer Architecture QtSpim, a Mips simulator S. Coudert and R. Pacalet January 4, 2018.....................
Memory Mapping 0xFFFF000C 0xFFFF0008 0xFFFF0004 0xffff0000 0x90000000 0x80000000 0x7ffff4d4 Transmitter data Transmitter control Receiver data Receiver control Kernel data segment Kernel text segment Reserved Stack segment Memory mapped I/O.kdata.byte 8,22,16 data in kernel data segment.ktext add $8, $1,$2 instructions in kernel text segment.ktext 0x80000100 sub $4,$2,$6 instructions in kernel text segment at address 0x80000100.data.byte 12,48 0x10000000 0x00400000 User data segment User text segment Reserved data in user data segment.text sub $4,$2,$6 instructions in user text segment 2/16.......................... S. Coudert and R. Pacalet January 4, 2018
Memory Mapped IO Transmitter / receiver used to write to console (screen) and read from keyboard Receiver ready: a character was received Transmitter ready: ready to send a character 3/16.......................... S. Coudert and R. Pacalet January 4, 2018
Syscalls Examples: 1. data 2 s t r : 3. a s c i i z " today " 4 5. t e x t 6 7 # p r i n t s t r i n g 8 l i $v0 4 9 la $a0, str 10 s y s c a l l 11 12 # p r i n t i n t 5 13 l i $v0 1 14 l a $a0,5 15 s y s c a l l 16 17 # read i n t 18 l i $v0 5 19 s y s c a l l Warning: input syscalls and mapped IO not compatible! 4/16.......................... S. Coudert and R. Pacalet January 4, 2018
Exception Hardware Cause register: information about cause of exception 5/16.......................... S. Coudert and R. Pacalet January 4, 2018
Status Register and interrupts Status register: interrupt mask,... 0, Transmitter irq: when transmitter is ready 1, Receiver irq: when a character arrives 5, Timer irq: Relies on 2 integer registers: count, incremented at fixed rate compare, set by user Interrupt when count register = compare register 6/16.......................... S. Coudert and R. Pacalet January 4, 2018
Registers in coprocessor 0 Coprocessor 0 registers implemented by QtSpim Coprocessor 0 specific instructions mfc0: move from coprocessor0 mtc0: move to coprocessor0 Coprocessor dedicated wires Integer unit bus bus 7/16.......................... S. Coudert and R. Pacalet January 4, 2018
Pseudo instructions Example: 1. data 2 l b l : 3. a s c i i z "message to p r i n t " 4. t e x t 5 la $a0, lbl 6 l i $v0, 1 7 s y s c a l l 8/16.......................... S. Coudert and R. Pacalet January 4, 2018
A quick view of kernel memory QtSpim defaults: Contains default start code Contains default exception handler Custom code: load from file 9/16.......................... S. Coudert and R. Pacalet January 4, 2018
Default exception handler (1/5) Data for exception handling: 1. kdata 2 m1_ :. a s c i i z " Exception " 3 m2_ :. a s c i i z " occurred and ignored \ n " 4 e0_ :. a s c i i z " [ I n t e r r u p t ] " 5 e1_ :. a s c i i z " [ TLB ] " 6 e2_ :. a s c i i z " [ TLB ] " 7 e3_ :. a s c i i z " [ TLB ] " 8 e4_ :. a s c i i z " [ Address error in i n s t / data fetch ] " 9 e5_ :. a s c i i z " [ Address e r r o r i n s t o r e ] " 10 e6_ :. asciiz " [Bad instruction address ] "... 1 e29_ :. a s c i i z " " 2 e30_ :. a s c i i z " [ Cache ] " 3 e31_ :. a s c i i z " " 4 excp :. word e0_, e1_, e2_, e3_, e4_, e5_, e6_, e7_, e8_, e9_ 5. word e10_, e11_, e12_, e13_, e14_, e15_, e16_, e17_, e18_, 6. word e19_, e20_, e21_, e22_, e23_, e24_, e25_, e26_, e27_, 7. word e28_, e29_, e30_, e31_ 8 s1 :. word 0 9 s2 :. word 0 10/16.......................... S. Coudert and R. Pacalet January 4, 2018
Default exception handler (2/5) Store state and Extract exception code: 1 # This i s the exception handler code t h a t the processor runs when 2 # an exception occurs. I t only p r i n t s some i n f o r m a t i o n about the 3 # exception, but can server as a model of how to w r i t e a handler. 4 # 5 # Because we are running in the kernel, we can use $k0 / $k1 without 6 # saving t h e i r old values. 7 8 # This i s the exception v e ctor address f o r MIPS 1 (R2000 ) : 9 #. k t e x t 0x80000080 10 # This i s the exception vector address f o r MIPS32 : 11. k t e x t 0x80000180 12 # Select the a p p r o p r i a t e one f o r the mode i n which SPIM i s compiled. 13. set noat 14 move $k1 $at # Save $at 15. set at 16 sw $v0 s1 # Not re e n t r a n t and we can t t r u s t $sp 17 sw $a0 s2 # But we need to use these CPU r e g i s t e r s 18 19 mfc0 $k0 $13 # Cause r e g i s t e r 20 s r l $a0 $k0 2 # E x t r a c t ExcCode F i e l d 21 andi $a0 $a0 0 x1f 11/16.......................... S. Coudert and R. Pacalet January 4, 2018
Default exception handler (3/5) Basic default handler, just print exception information: 1 # P r i n t i n f o r m a t i o n about exception. 2 # 3 l i $v0 4 # s y s c a l l 4 ( p r i n t _ s t r ) 4 l a $a0 m1_ 5 s y s c a l l 6 7 l i $v0 1 # s y s c a l l 1 ( p r i n t _ i n t ) 8 s r l $a0 $k0 2 # E x t r a c t ExcCode F i e l d 9 andi $a0 $a0 0 x1f 10 s y s c a l l 11 12 l i $v0 4 # s y s c a l l 4 ( p r i n t _ s t r ) 13 andi $a0 $k0 0x3c 14 lw $a0 excp ( $a0 ) 15 nop 16 s y s c a l l 17 18 bne $k0 0x18 ok_pc # Bad PC exception r e q u i r e s s p e c i a l checks 19 nop 20 21 mfc0 $a0 $14 # EPC 22 andi $a0 $a0 0x3 # I s EPC word aligned? 23 beq $a0 0 ok_pc 24 nop 25 26 l i $v0 10 # E x i t on r e a l l y bad PC 27 s y s c a l l 12/16.......................... S. Coudert and R. Pacalet January 4, 2018
Default exception handler (4/5) Test interrupts and prepare EPC for return: 1 ok_pc : 2 l i $v0 4 # s y s c a l l 4 ( p r i n t _ s t r ) 3 l a $a0 m2_ 4 s y s c a l l 5 6 s r l $a0 $k0 2 # E x t r a c t ExcCode F i e l d 7 andi $a0 $a0 0 x1f 8 bne $a0 0 r e t # 0 means exception was an i n t e r r u p t 9 nop 10 11 # I n t e r r u p t s p e c i f i c code goes here! 12 # Don t skip instruction at EPC since i t has not executed. 13 14 15 ret : 16 # Return from ( non i n t e r r u p t ) exception. Skip offending i n s t r u c t i o n 17 # at EPC to avoid i n f i n i t e loop. 18 # 19 mfc0 $k0 $14 # Bump EPC register 20 addiu $k0 $k0 4 # Skip f a u l t i n g i n s t r u c t i o n 21 # ( Need to handle delayed branch case here ) 22 mtc0 $k0 $14 13/16.......................... S. Coudert and R. Pacalet January 4, 2018
Default exception handler (5/5) Restore State and return 1 # Restore CPU r e g i s t e r s and r e s e t procesor s t a t e 2 # 3 lw $v0 s1 # Restore other CPU r e g i s t e r s 4 lw $a0 s2 5 6. set noat 7 move $at $k1 # Restore $at 8. set at 9 10 mtc0 $0 $13 # Clear Cause r e g i s t e r 11 12 mfc0 $k0 $12 # Set Status r e g i s t e r 13 o r i $k0 0x1 # I n t e r r u p t s enabled 14 mtc0 $k0 $12 15 16 # Return from exception on MIPS32 : 17 e r e t 14/16.......................... S. Coudert and R. Pacalet January 4, 2018
Default Start Code Starts at address start and call label main: 1 # Standard startup code. Invoke the routine " main " with arguments : 2 # main ( argc, argv, envp ) 3 # 4. t e x t 5. g l o b l s t a r t 6 s t a r t : 7 lw $a0 0( $sp ) # argc 8 addiu $a1 $sp 4 # argv 9 addiu $a2 $a1 4 # envp 10 s l l $v0 $a0 2 11 addu $a2 $a2 $v0 12 j a l main 13 nop 14 15 l i $v0 10 16 syscall # syscall 10 ( e x i t ) 17 18. g l o b l eoth 19 eoth : Notice global labels (to be seen anywhere) 15/16.......................... S. Coudert and R. Pacalet January 4, 2018
Lab on QtSpim Code according Mips conventions and beware your stack! 16/16.......................... S. Coudert and R. Pacalet January 4, 2018