Low-oltage CMOS 6-Bit Traparent Latch With 5 Tolerant Inputs and Outputs (3 State, Non Inverting) The MC74LCX6373 is a high performance, non inverting 6 bit traparent latch operating from a 2.3 to 3.6 supply. The device is byte controlled. Each byte has separate Output Enable and Latch Enable inputs. These control pi can be tied together for full 6 bit operation. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A I specification of 5.5 allows MC74LCX6373 inputs to be safely driven from 5.0 devices. The MC74LCX6373 contai 6 type latches with 3 state 5.0 tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the n inputs enters the latches. In this condition, the latches are traparent, i.e., a latch output will change state each time its input changes. When LE is LOW, the latches store the information that was present on the inputs a setup time preceding the HIGH to LOW traition of LE. The 3 state outputs are controlled by the Output Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. Features esigned for 2.3 to 3.6 Operation 5.4 Maximum t pd 5.0 Tolerant Interface Capability With 5.0 TTL Logic Supports Live Iertion and Withdrawal I OFF Specification Guarantees High Impedance When = 0 LTTL Compatible LCMOS Compatible 24 ma Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (20 A) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 ma ES Performance: Human Body Model >2000 Machine Model >200 These evices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant A WL YY WW G T SUFFIX CASE 20 MARKING IAGRAM LCX6373G AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week = Pb Free Package ORERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 3 of this data sheet. Semiconductor Components Industries, LLC, 202 October, 202 Rev. Publication Order Number: MC74LCX6373/
OE O0 LE 2 47 0 OE LE OE2 LE2 24 25 O GN 3 46 4 45 GN 0 47 2 O0 8 36 3 O8 O2 O3 5 44 2 6 43 3 7 42 46 3 O 9 35 4 O9 O4 8 4 4 O5 GN 9 40 5 0 39 GN 2 44 5 O2 0 33 6 O0 O6 O7 O8 38 6 2 37 7 3 36 8 3 43 6 O3 32 7 O O9 GN O0 4 35 9 5 34 GN 6 33 0 4 4 8 O4 2 30 9 O2 O 7 32 8 3 O2 9 30 2 5 40 9 O5 3 29 20 O3 O3 GN O4 20 29 3 2 28 GN 22 27 4 6 38 O6 4 27 22 O4 O5 OE2 23 26 5 24 25 LE2 7 37 2 O7 5 26 23 O5 Figure. Pinout: Lead (Top iew) Figure 2. Logic iagram Table. PIN NAMES Pi OEn LEn 0 5 O0 O5 Function Output Enable Inputs Latch Enable Inputs Inputs Outputs TRUTH TABLE Inputs Outputs Inputs Outputs LE OE 0:7 O0:7 LE2 OE2 8:5 O8:5 X H X Z X H X Z H L L L H L L L H L H H H L H H L L X O0 L L X O0 H = High oltage Level L = Low oltage Level Z = High Impedance State X = High or Low oltage Level and Traitio Are Acceptable; for I CC reaso, O NOT FLOAT Inputs 2
ORERING INFORMATION MC74LCX6373TG M74LCX6373TR2G evice Package Shipping (Pb Free) (Pb Free) 39 Units / Rail 2500 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BR80/. MAXIMUM RATINGS Symbol Parameter alue Condition Units C Supply oltage 0.5 to +7.0 I C Input oltage 0.5 I +7.0 O C Output oltage 0.5 O +7.0 Output in 3 State 0.5 O + 0.5 Output in HIGH or LOW State. (Note ) I IK C Input iode Current 50 I < GN ma I OK C Output iode Current 50 O < GN ma +50 O > ma I O C Output Source/Sink Current ±50 ma I CC C Supply Current Per Supply Pin ±00 ma I GN C Ground Current Per Ground Pin ±00 ma T STG Storage Temperature Range 65 to +50 C MSL Moisture Seitivity Level Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability.. I O absolute maximum rating must be observed. RECOMMENE OPERATING CONITIONS Symbol Parameter Min Typ Max Units Supply oltage Operating ata Retention ly 2.0 2.5, 3.3 2.5, 3.3 I Input oltage 0 5.5 O I OH I OL Output oltage (HIGH or LOW State) (3 State) HIGH Level Output Current = 3.0 3.6 = 2.7 3.0 = 2.3 2.7 LOW Level Output Current = 3.0 3.6 = 2.7 3.0 = 2.3 2.7 T A Operating Free Air Temperature 55 +25 C t/ Input Traition Rise or Fall Rate, IN from 0.8 to 2.0, = 3.0 0 0 / 0 0 3.6 3.6 5.5 24 2 8 +24 +2 +8 ma ma 3
C ELECTRICAL CHARACTERISTICS Symbol Characteristic Condition T A = 55 C to +25 C IH HIGH Level Input oltage (Note 2) 2.3 2.7.7 Min 2.7 3.6 2.0 IL LOW Level Input oltage (Note 2) 2.3 2.7 0.7 Max 2.7 3.6 0.8 OH HIGH Level Output oltage 2.3 3.6 ; I OL = 00 A 0.2 = 2.3 ; I OH = 8 ma.8 = 2.7 ; I OH = 2 ma 2.2 = 3.0 ; I OH = 8 ma 2.4 = 3.0 ; I OH = 24 ma 2.2 OL LOW Level Output oltage 2.3 3.6 ; I OL = 00 A 0.2 I OZ 3 State Output Current = 3.6, IN = IH or IL, OUT = 0 to 5.5 = 2.3 ; I OL = 8 ma 0.6 = 2.7 ; I OL = 2 ma 0.4 = 3.0 ; I OL = 6 ma 0.4 = 3.0 ; I OL = 24 ma 0.55 Units ±5 A I OFF Power Off Leakage Current = 0, IN = 5.5 or OUT = 5.5 0 A I IN Input Leakage Current = 3.6, IN = 5.5 or GN ±5 A I CC uiescent Supply Current = 3.6, IN = 5.5 or GN 20 A I CC Increase in I CC per Input 2.3 3.6 ; IH = 0.6 500 A 2. These values of I are used to test C electrical characteristics only. AC CHARACTERISTICS (t R = t F = 2.5 ; C L = 50 pf; R L = 500 ) T A = 55 C to +25 C = 3.3 ± 0.3 C L = 50 pf = 2.7 C L = 50 pf = 2.5 ± 0.2 C L = 30 pf Symbol Parameter Waveform t PLH t PHL Propagation elay n to O n Min Max Min Max Min Max 5.4 5.4 5.9 5.9 Units t PLH t PHL Propagation elay 3 LE to O n 5.5 5.5 6.4 6.4 6.6 6.6 t PZH t PZL Output Enable Time to High and Low Level 2 6. 6. 7.9 7.9 t PHZ t PLZ Output isable Time From High and Low Level 2 6.0 6.0 6.3 6.3 7.2 7.2 t s Setup Time, HIGH or LOW n to LE 3 2.5 2.5 3.0 t h Hold Time, HIGH or LOW n to LE 3 2.0 t w LE Pulse Width, HIGH 3 3.0 3.0 3.5 t OSHL t OSLH Output to Output Skew (Note 3) 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (t OSHL ) or LOW to HIGH (t OSLH ); parameter guaranteed by design..0.0 4
YNAMIC SWITCHING CHARACTERISTICS Symbol Characteristic Condition OLP ynamic LOW Peak oltage (Note 4) = 3.3, C L = 50 pf, IH = 3.3, IL = 0 = 2.5, C L = 30 pf, IH = 2.5, IL = 0 T A = +25 C Min Typ Max 0.8 0.6 Units OL ynamic LOW alley oltage (Note 4) = 3.3, C L = 50 pf, IH = 3.3, IL = 0 = 2.5, C L = 30 pf, IH = 2.5, IL = 0 4. Number of outputs defined as n. Measured with n outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. CAPACITIE CHARACTERISTICS Symbol Parameter Condition Typical Units C IN Input Capacitance = 3.3, I = 0 or 7 pf C OUT Output Capacitance = 3.3, I = 0 or 8 pf C P Power issipation Capacitance 0 MHz, = 3.3, I = 0 or 20 pf 0.8 0.6 n t PHL t PLH WAEFORM PROPAGATION ELAYS t R = t F = 2.5, 0% to 90%; f = MHz; t W = 500 0 OH OL OEn n t PZH t PHZ 0 OH HZ LEn t s t w t h 0 0 t PZL t PLZ t PLH, t PHL OH LZ OL OL WAEFORM 2 OUTPUT ENABLE AN ISABLE TIMES t R = t F = 2.5, 0% to 90%; f = MHz; t W = 500 WAEFORM 3 LE to PROPAGATION ELAYS, LE MINIMUM PULSE WITH, n to LE SETUP AN HOL TIMES t R = t F = 2.5, 0% to 90%; f = MHz; t W = 500 except when noted Figure 3. AC Waveforms Table 2. AC WAEFORMS Symbol 3.3 ± 0.3 2.7 2.5 ± 0.2 / 2 / 2 HZ OL + 0.3 OL + 0.3 OL + 0.5 LZ OH 0.3 OH 0.3 OH 05 5
PULSE GENERATOR UT R 6 or 2 OPEN GN R T C L R L Figure 4. Test Circuit Table 3. TEST CIRCUIT Test t PLH, t PHL t PZL, t PLZ Switch Open 6 at = 3.3 ± 0.3 6 at = 2.5 ± 0.2 Open Collector/rain t PLH and t PHL t PZH, t PHZ 6 GN C L = 50 pf at = 3.3 ± 0.3 or equivalent (includes jig and probe capacitance) C L = 30 pf at = 2.5 ± 0.2 or equivalent (includes jig and probe capacitance) R L = R = 500 or equivalent R T = Z OUT of pulse generator (typically 50 ) 6
PACKAGE IMENSIONS S U 0.254 (0.00) M T PIN IENT. L 0.076 (0.003) T SEATING PLANE C X K REF 0.2 (0.005) M T U S S 24 A G 25 T SUFFIX CASE 20 0 ISSUE B B U H N J N ÇÇÇ ÉÉÉ J ETAIL E K K SECTION N N F ETAIL E M 0.25 (0.00) W NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, 982. 2. CONTROLLING IMENSION: MILLIMETER. 3. IMENSIONS A AN B O NOT INCLUE MOL FLASH, PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION K OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K IMENSION AT MAXIMUM MATERIAL CONITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. IMENSIONS A AN B ARE TO BE ETERMINE AT ATUM PLANE W. MILLIMETERS INCHES IM MIN MAX MIN MAX A 2.40 2.60 0.8 0.496 B 6.00 6.20 0.236 0.244 C.0 0.043 0.05 0.5 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.50 BSC 0.097 BSC H 0.37 0.05 J 0.09 0.20 0.004 0.008 J 0.09 0.6 0.004 0.006 K 0.7 0.27 0.007 0.0 K 0.7 0.23 0.007 0.009 L 7.95 8.25 0.33 0.325 M 0 8 0 8 X 0.32 RECOMMENE SOLERING FOOTPRINT X.00 8.45 0.50 PITCH IMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.oemi.com/site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 8027 USA Phone: 303 675 275 or 800 344 3860 Toll Free USA/Canada Fax: 303 675 276 or 800 344 3867 Toll Free USA/Canada Email: orderlit@oemi.com N. American Technical Support: 800 282 9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 42 33 790 290 Japan Customer Focus Center Phone: 8 3 587 050 7 ON Semiconductor Website: www.oemi.com Order Literature: http://www.oemi.com/orderlit For additional information, please contact your local Sales Representative MC74LCX6373/