The MC4532B is constructed with complementary MOS (CMOS) enhancement mode devices. The primary function of a priority encoder is to provide a binary address for the active input with the highest priority. Eight data inputs (D thru D7) and an enable input (E in) are provided. Five outputs are available, three are address outputs (Q thru Q2), one group select (GS) and one enable output (E out ). Diode Protection on All Inputs Supply Voltage Range = 3. Vdc to 8 Vdc Capable of Driving Two Low power TTL Loads or One Low Power Schottky TTL Load over the Rated Temperature Range MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) Symbol Parameter Value Unit V DD DC Supply Voltage Range.5 to +8. V V in, V out Input or Output Voltage Range (DC or Transient).5 to V DD +.5 V I in, I out P D Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) ± ma 5 mw T A Ambient Temperature Range 55 to +25 C T stg Storage Temperature Range 65 to + C T L Lead Temperature (8 Second Soldering) 26 C 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic P and D/DW Packages: 7. mw/c From 65C To 25C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range V SS (V in or V out ) V DD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must be left open. A WL, L YY, Y WW, W PDIP 6 P SUFFIX CASE 648 SOIC 6 D SUFFIX CASE 75B SOEIAJ 6 F SUFFIX CASE 966 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION MARKING DIAGRAMS Device Package Shipping MC4532BCP PDIP 6 2/Box MC4532BD SOIC 6 48/Rail MC4532BDR2 SOIC 6 25/Tape & Reel 6 6 6 MC4532BCP AWLYYWW 4532B AWLYWW MC4532B ALYW MC4532BF SOEIAJ 6 See Note. MC4532BFEL SOEIAJ 6 See Note. MC4532BFR SOEIAJ 6 See Note.. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2 August, 2 Rev. 4 Publication Order Number: MC4532B/D
PIN ASSIGNMENT Input TRUTH TABLE Output E in D7 D6 D5 D4 D3 D2 D D GS Q2 Q Q E out X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X = Don t Care 2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS ) Characteristic Output Voltage V in = V DD or Level Symbol V OL 5. V 5. Level V in = or V DD OH Input Voltage Level (V O = 4.5 or.5 Vdc) (V O = 9. or. Vdc) (V O = 3.5 or.5 Vdc) (V O =.5 or 4.5 Vdc) (V O =. or 9. Vdc) (V O =.5 or 3.5 Vdc) Level Output Drive Current (V OH = 2.5 Vdc) Source (V OH = 4.6 Vdc) (V OH = 9.5 Vdc) (V OH = 3.5 Vdc) (V OL =.4 Vdc) Sink (V OL =.5 Vdc) (V OL =.5 Vdc) V IL 5. V IH 5. I OH 5. 5. I OL 5. 55C 25C 25C V DD Vdc Min Max Min Typ (4.) Max Min Max Unit 4.95 9.95 4.95 3.5 7. 3..64.6 4.2.64.6 4.2.5.5.5.5 3. 4. 4.95 9.95 4.95 3.5 7. 2.4.5.3 3.4 5. 2.25 4.5 6.75 2.75 5.5 8.25 4.2.88 2.25 8.8.5.5.5.5 3. 4. 4.95 9.95 4.95 3.5 7..7.36.9 2.4 Input Current I in ±. ±. ±. ±. µadc Input Capacitance (V in = ).5.3 3.4.88 2.25 8.8.5.5.5 C in 5. 7.5 pf.36.9 2.4.5 3. 4. Vdc Vdc Vdc Vdc madc madc Quiescent Current (Per Package) Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (C L = 5 pf on all outputs, all buffers switching) I DD 5. I T 5. 5. 2.5.. 5. 2 I T = (.74 µa/khz) f + I DD I T = (3.65 µa/khz) f + I DD I T = (5.73 µa/khz) f + I DD 4. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 5. The formulas given are for the typical characteristics only at 25C. 6. To calculate total supply current at loads other than 5 pf: I T (C L ) = I T (5 pf) + (C L 5) Vfk where: I T is in µa (per package), C L in pf, V = (V DD V SS ) in volts, f in khz is input frequency, and k =.5. 3 6 µadc µadc 3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (7.) (C L = 5 pf, T A = 25C) Characteristic Symbol V DD Min Typ (8.) Max Unit Output Rise and Fall Time t TLH, t THL = (.5 ns/pf) C L + 25 ns t TLH, t THL = (.75 ns/pf) C L + 2.5 ns t TLH, t THL = (.55 ns/pf) C L + 9.5 ns Propagation Delay Time E in to E out t PLH, t PHL = (.7 ns/pf) C L + 2 ns t PLH, t PHL = (.66 ns/pf) C L + 77 ns t PLH, t PHL = (.5 ns/pf) C L + 55 ns Propagation Delay Time E in to GS t PLH, t PHL = (.7 ns/pf) C L + 9 ns t PLH, t PHL = (.66 ns/pf) C L 57 ns t PLH, t PHL = (.5 ns/pf) C L + 4 ns Propagation Delay Time E in to Q n t PLH, t PHL = (.7 ns/pf) C L + 95 ns t PLH, t PHL = (.66 ns/pf) C L + 7 ns t PLH, t PHL = (.5 ns/pf) C L + 75 ns Propagation Delay Time D n to Q n t PLH, t PHL = (.7 ns/pf) C L + 265 ns t PLH, t PHL = (.66 ns/pf) C L + 37 ns t PLH, t PHL = (.5 ns/pf) C L + 85 ns Propagation Delay Time D n to GS t PLH, t PHL = (.7 ns/pf) C L + 95 ns t PLH, t PHL = (.66 ns/pf) C L + 7 ns t PLH, t PHL = (.5 ns/pf) C L + 75 ns t TLH, t THL 5. t PLH, t PHL 5. t PLH, t PHL 5. t PHL, t PLH 5. t PLH, t PHL 5. t PLH, t PHL 5. 7. The formulas given are for the typical characteristics only at 25C. 8. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 5 4 25 8 75 9 65 28 4 3 7 28 4 2 8 4 22 6 35 8 3 56 28 2 6 34 22 56 28 2 ns ns ns ns ns ns V GS = V DD V GS = V DD V DS = V out V DS = V out V DD Output Sink Current Source Current Under Test D thru D7 E in D thru D6 D7 E in E out X Q X Q Q2 X X GS X µ µ Figure. Typical Sink and Source Current Characteristics Figure 2. Typical Power Dissipation Test Circuit 4
NOTE: Input rise and fall times are 2 ns Figure 3. AC Test Circuit and Waveforms 5
LOGIC DIAGRAM (Positive Logic) LOGIC EQUATIONS E out = E in D D D2 D3 D4 D5 D6 D7 Q = E in (D D2 D4 D6 + D3 D4 D6 + D5 D6 + D7) Q = E in (D2 D4 D5 + D3 D4 D5 + D6 + D7) Q2 = E in (D4 + D5 + D6 + D7) GS = E in (D + D + D2 + D3 + D4 + 5 + D6 + D7) 6
Figure 4. Two MC4532B s Cascaded for 4 Bit Output DIGITAL TO ANALOG CONVERSION The digital eight bit word to be converted is applied to the inputs of the MC452 with the most significant bit at X7 and the least significant bit at X. A clock input of up to 2.5 MHz (at V DD = V) is applied to the MC452B. A compromise between I bias for the MC7 and R between N and P channel outputs gives a value of R of 33 k ohms. In order to filter out the switching frequencies, RC should be about. ms (if R = 33 k ohms, C.3 µf). The analog 3. db bandwidth would then be dc to. khz. ANALOG TO DIGITAL CONVERSION An analog signal is applied to the analog input of the MC7. A digital eight bit word known to represent a digitized level less than the analog input is applied to the MC452 as in the D to A conversion. The word is incremented at rates sufficient to allow steady state to be reached between incrementations (i.e. 3. ms). The output of the MC7 will change when the digital input represents the first digitized level above the analog input. This word is the digital representation of the analog word. Figure 5. Digital to Analog and Analog to Digital Converter 7
PACKAGE DIMENSIONS H A G B F C S K D 6 PL PDIP 6 P SUFFIX PLASTIC DIP PACKAGE CASE 648 8 ISSUE R T J L M 8
PACKAGE DIMENSIONS T G A D 6 PL K B C SOIC 6 D SUFFIX PLASTIC SOIC PACKAGE CASE 75B 5 ISSUE J P 8 PL M R X 45 J F 9
PACKAGE DIMENSIONS e Z D b E A H E A SOEIAJ 6 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966 ISSUE O VIEW P M L E Q L DETAIL P c
Notes
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