DRAM MT4LCME1, MT4LCMB6 For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/dramds.html FEATURES Single +3.3 ±0.3 power supply Industry-standard x pinout, timing, functions, and packages 13 row, 10 column addresses (E1) or 12 row, 11 column addresses (B6) High-performance CMOS silicon-gate process All inputs, outputs and clocks are LTTLcompatible FAST PAGE MODE (FPM) access 4,096-cycle -BEFORE- (CBR) REFRESH distributed across 64ms Optional self refresh (S) for low-power data retention OPTIONS MARKING Refresh Addressing 4,096 (4K) rows B6,192 (K) rows E1 Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil) DJ TG Timing 50ns access -5 60ns access -6 Refresh Rates Standard Refresh (64ms period) None Self Refresh (12ms period) S* NOTE: 1. The Meg x base number differentiates the offerings in one place MT4LCME1. The fifth field distinguishes various options: E1 designates an K refresh and B6 designates a 4K refresh for s. 2. The # symbol indicates signal is active LOW. *Contact factory for availability Part Number Example: MT4LCME1DJ-5 KEY TIMING PARAMETERS SPEED t RC t RAC t PC t AA t CAC -5 90ns 50ns 30ns 25ns 13ns -6 110ns 60ns 35ns 30ns 15ns CC DQ0 DQ1 DQ2 DQ3 NC CC A0 A1 A2 A3 A4 A5 CC **A12 on E1 version, NC on B6 version MEG x PART NUMBERS REFRESH PART NUMBER ADDRESSING PACKAGE REFRESH MT4LCME1DJ-x K SOJ Standard MT4LCME1DJ-x S K SOJ Self MT4LCME1TG-x K TSOP Standard MT4LCME1TG-x S K TSOP Self MT4LCMB6DJ-x 4K SOJ Standard MT4LCMB6DJ-x S 4K SOJ Self MT4LCMB6TG-x 4K TSOP Standard MT4LCMB6TG-x S 4K TSOP Self x = speed PIN ASSIGNMENT (Top iew) 32-Pin SOJ 32-Pin TSOP 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 2 27 26 25 24 23 22 21 20 19 1 17 SS DQ7 DQ6 DQ5 DQ4 ss OE# NC/A12** A11 A10 A9 A A7 A6 SS CC DQ0 DQ1 DQ2 DQ3 NC CC A0 A1 A2 A3 A4 A5 CC 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 2 27 26 25 24 23 22 21 20 19 1 17 SS DQ7 DQ6 DQ5 DQ4 SS OE# NC/A12** A11 A10 A9 A A7 A6 SS GENERAL DESCRIPTION The Meg x DRAMs are high-speed CMOS, dynamic random-access memory devices containing 67,10,64 bits organized in a x configuration. The Meg x DRAMs are functionally organized as,3,60 locations containing eight bits each. The,3,60 memory locations are arranged in,192 rows by 1,024 columns for the MT4LCME1 or 4,096 rows by 2,04 columns for the MT4LCMB6. During READ or WRITE cycles, each location is uniquely addressed via the address bits. First, the row address is latched by the 1
FUNCTIONAL BLOCK DIAGRAM MT4LCME1 (13 row addresses) NO. 2 CLOCK GENERATOR CONTROL LOGIC DATA-IN BUFFER DATA-OUT BUFFER DQ0- DQ7 OE# A0- A12 10 - ADDRESS BUFFER(10) REFRESH CONTROLLER REFRESH COUNTER 10 DECODER 1,024 SENSE AMPLIFIERS I/O GATING 1,024 x 13 13 - ADDRESS BUFFERS (13) 13 DECODER,192 COMPLEMENT SELECT,192 x SELECT,192 x 1,024 x MEMORY ARRAY NO. 1 CLOCK GENERATOR DD SS FUNCTIONAL BLOCK DIAGRAM MT4LCMB6 (12 row addresses) NO. 2 CLOCK GENERATOR CONTROL LOGIC DATA-IN BUFFER DATA-OUT BUFFER DQ0- DQ7 OE# A0- A11 11 - ADDRESS BUFFER(11) REFRESH CONTROLLER REFRESH COUNTER 11 DECODER 2,04 SENSE AMPLIFIERS I/O GATING 2,04 x 12 12 - ADDRESS BUFFERS (12) 12 DECODER 4,096 COMPLEMENT SELECT 4,096 x SELECT 4,096 x 2,04 x MEMORY ARRAY NO. 1 CLOCK GENERATOR DD SS 2
GENERAL DESCRIPTION (continued) signal, then the column address by. Both devices provide FAST-PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFY-WRITE) within a given row. The MT4LCME1 and MT4LCMB6 must be refreshed periodically in order to retain stored data. FAST PAGE MODE ACCESS Each location in the DRAM is uniquely addressable as mentioned in the General Description. The data for each location is accessed via the eight I/O pins (DQ0- DQ7). The signal must be activated to execute a WRITE operation; otherwise, a READ operation will be performed. The OE# signal must be activated to enable the DQ output drivers for a read access and can be deactivated to disable output data if necessary. FAST-PAGE-MODE operations are always initiated with a row address strobed in by the signal, followed by a column address strobed in by, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling while holding LOW and entering new column addresses with each cycle. Returning HIGH terminates the FAST-PAGE-MODE operation. DRAM REFRESH The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all,192 rows (E1) or all 4,096 rows (B6) in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LCME1 internally refreshes two rows for every CBR cycle, whereas the MT4LCMB6 refreshes one row for every CBR cycle. So with either device, executing 4,096 CBR cycles covers all rows. The CBR REFRESH cycle will invoke the internal refresh counter for automatic addressing. Alternatively, -ONLY REFRESH capability is inherently provided. However, with this method only one row is refreshed at a time; so for the MT4LCME1,,192 -ONLY REFRESH cycles must be executed every 64ms to cover all rows. Some compatibility issues may become apparent. JEDEC strongly recommends the use of CBR REFRESH for this device. An optional self refresh mode is also available on the S version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding LOW for the specified t RASS. The S option allows for an extended refresh period of 12ms, or 31.25µs per row for a 4K refresh and 15.625µs per row for an K refresh when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving HIGH for a minimum time of t RPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes -ONLY or burst CBR refresh sequence, all rows must be refreshed with a refresh rate of t RC minimum prior to the resumption of normal operation. STANDBY Returning and HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the HIGH time. 3
ABSOLUTE MAXIMUM RATINGS* oltage on CC Relative to SS... -1 to +4.6 oltage on NC, Inputs or I/O Pins Relative to SS... -1 to +4.6 Operating Temperature, T A (ambient)... 0 C to +70 C Storage Temperature (plastic)... -55 C to +150 C Power Dissipation... 1W *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6) (CC = +3.3 ±0.3) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY OLTAGE CC 3 3.6 INPUT HIGH OLTAGE: alid Logic 1; All inputs, I/Os and any NC IH 2 CC + 0.3 26 INPUT LOW OLTAGE: alid Logic 0; All inputs, I/Os and any NC -0.3 0. 26 INPUT LEAKAGE CURRENT: Any input at IN (0 IN CC + 0.3); II -2 2 µa All other pins not under test = 0 OUTPUT HIGH OLTAGE: IOUT = -2mA OH 2.4 OUTPUT LOW OLTAGE: IOUT = 2mA OL 0.4 OUTPUT LEAKAGE CURRENT: Any output at OUT (0 OUT CC + 0.3); IOZ -5 5 µa DQ is disabled and in High-Z state 4
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 2, 3, 5, 6) (CC = +3.3 ±0.3) 4K K PARAMETER/CONDITION SYMBOL SPEED REFRESH REFRESH UNITS NOTES STANDBY CURRENT: TTL ICC1 ALL 1 1 ma ( = = IH) STANDBY CURRENT: CMOS ( = ž CC - 0.2; DQs may be left open; ICC2 ALL 500 500 µa Other inputs: IN CC - 0.2 or IN 0.2) OPERATING CURRENT: Random READ/WRITE ICC3-5 175 135 ma 25 Average power supply current -6 165 125 (,, address cycling: t RC = t RC [MIN]) OPERATING CURRENT: FAST PAGE MODE ICC4-5 105 105 ma 25 Average power supply current ( =, -6 95 95, address cycling: t PC = t PC [MIN]) REFRESH CURRENT: -ONLY ICC5-5 175 135 ma 22 Average power supply current -6 165 125 ( cycling, = IH: t RC = t RC [MIN]) REFRESH CURRENT: CBR ICC6-5 175 175 ma 4, 7 Average power supply current -6 165 165 (,, address cycling: t RC = t RC [MIN]) REFRESH CURRENT: Extended ( S version only) Average power supply current: = 0.2 or CBR cycling; = t RAS (MIN); = CC - 0.2; ICC7 ALL 400 400 µa 4, 7 A0-A11, OE# and DIN = CC - 0.2 or 0.2 (DIN may be left open) REFRESH CURRENT: Self ( S version only) Average power supply current: CBR with ICC ALL 400 400 µa 4, 7 t RASS (MIN) and held LOW; = CC - 0.2; A0-A11, OE# and DIN = CC - 0.2 or 0.2 (DIN may be left open) 5
CAPACITANCE (Note: 2) PARAMETER SYMBOL MAX UNITS Input Capacitance: Address pins CI1 5 pf Input Capacitance:,,, OE# CI2 7 pf Input/Output Capacitance: DQ CIO 7 pf AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7,, 9, 10, 11, 12) (CC = +3.3 ±0.3) AC CHARACTERISTICS PARAMETER NOTES Access time from column address t AA 25 30 ns Column-address hold time (referenced to ) t AR 40 45 ns Column-address setup time 0 0 ns Row-address setup time t ASR 0 0 ns Column address to delay time t AWD 4 55 ns 1 Access time from t CAC 13 15 ns Column-address hold time 10 ns pulse width 13 10,000 15 10,000 ns LOW to Don t Care during Self Refresh t CHD 15 15 ns hold time (CBR Refresh) t CHR 15 15 ns 4 to output in Low-Z t CLZ 3 3 ns precharge time (FAST PAGE MODE) 10 ns 13 Access time from precharge A 30 35 ns to precharge time t CRP 5 5 ns hold time t CSH 50 60 ns setup time (CBR Refresh) t CSR 5 5 ns 4 to delay time t CWD 36 40 ns 1 WRITE command to lead time t CWL 13 15 ns Data-in hold time t DH 10 ns 19 Data-in setup time t DS 0 0 ns 19 Output disable t OD 3 13 3 15 ns 23, 24 Output enable time t OE 13 15 ns 20 OE# hold time from during t OEH 13 15 ns 24 READ-MODIFY-WRITE cycle Output buffer turn-off delay t OFF 3 13 3 15 ns 17, 23 OE# setup prior to during t ORD 0 0 ns HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time t PC 30 35 ns FAST-PAGE-MODE READ-WRITE cycle time t PRWC 76 5 ns Access time from t RAC 50 60 ns 6
AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7,, 9, 10, 11, 12) (CC = +3.3 ±0.3) AC CHARACTERISTICS PARAMETER NOTES to column-address delay time t RAD 13 15 ns 15 Row-address hold time t RAH 10 ns pulse width t RAS 50 10,000 60 10,000 ns pulse width (FAST PAGE MODE) t RASP 50 125,000 60 125,000 ns pulse width during Self Refresh t RASS 100 100 µs Random READ or WRITE cycle time t RC 90 110 ns to delay time t RCD 1 20 ns 14 READ command hold time (referenced to ) t RCH 0 0 ns 16 READ command setup time t RCS 0 0 ns Refresh period t REF 64 64 ms 22 Refresh period (2,04 cycles) S version t REF 12 12 ms precharge time t RP 30 40 ns to precharge time t RPC 5 5 ns precharge time exiting Self Refresh t RPS 90 105 ns READ command hold time (referenced to ) t RRH 0 0 ns 16 hold time t RSH 13 15 ns READ-WRITE cycle time t RWC 131 155 ns to delay time t RWD 73 5 ns 1 WRITE command to lead time t RWL 13 15 ns Transition time (rise or fall) t T 2 50 2 50 ns WRITE command hold time t WCH 10 ns WRITE command hold time (referenced to ) t WCR 40 45 ns command setup time t WCS 0 0 ns 1 WRITE command pulse width t WP 10 ns hold time (CBR Refresh) t WRH 10 10 ns setup time (CBR Refresh) t WRP 10 10 ns 7
NOTES 1. All voltages referenced to SS. 2. This parameter is sampled. CC = +3.3; f = 1 MHz. 3. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100µs is required after powerup, followed by eight refresh cycles (- ONLY or CBR with HIGH), before proper device operation is ensured. The eight cycle wake-ups should be repeated any time the t REF refresh requirement is exceeded. 7. AC characteristics assume t T = 5ns.. IH (MIN) and (MAX) are reference levels for measuring timing of input signals. Transition times are measured between IH and (or between and IH). 9. In addition to meeting the transition rate specification, all input signals must transit between IH and (or between and IH) in a monotonic manner. 10. If = IH, data output is High-Z. 11. If =, data output may contain data from the last valid READ cycle. 12. Measured with a load equivalent to two TTL gates, 100pF and OL = 0. and OH = 2. 13. If is LOW at the falling edge of, output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, must be pulsed HIGH for. 14. The t RCD (MAX) limit is no longer specified. t RCD (MAX) was specified as a reference point only. If t RCD was greater than the specified t RCD (MAX) limit, then access time was controlled exclusively by t CAC ( t RAC [MIN] no longer applied). With or without the t RCD limit, t AA and t CAC must always be met. 15. The t RAD (MAX) limit is no longer specified. t RAD (MAX) was specified as a reference point only. If t RAD was greater than the specified t RAD (MAX) limit, then access time was controlled exclusively by t AA ( t RAC and t CAC no longer applied). With or without the t RAD (MAX) limit, t AA, t RAC and, t CAC must always be met. 16. Either t RCH or t RRH must be satisfied for a READ cycle. 17. t OFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to OH or OL. 1. t WCS, t RWD, t AWD, and t CWD are not restrictive operating parameters. t WCS applies to EARLY WRITE cycles. If t WCS > t WCS MIN, the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. t RWD, t AWD and t CWD define READ- MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. The values shown were calculated for reference allowing 10ns for the external latching of read data and application of write data. OE# held HIGH and taken LOW after goes LOW result in a LATE WRITE (OE#-controlled) cycle. t WCS, t RWD, t CWD and t AWD are not applicable in a LATE WRITE cycle. 19. These parameters are referenced to leading edge in EARLY WRITE cycles and leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not possible. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, = LOW and OE# = HIGH. 22. -ONLY REFRESH requires that all,192 rows of the MT4LCME1 or all 4,096 rows of the MT4LCMB6 be refreshed at least once every 64ms. CBR REFRESH for either device requires that at least 4,096 cycles be completed every 64ms. 23. The DQs open during READ cycles once t OD or t OFF occurs. If goes HIGH before OE#, the DQs will open regardless of the state of OE#. If stays LOW while OE# is brought HIGH, the DQs will open. If OE# is brought back LOW ( still LOW), the DQs will provide the previously read data. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both t OD and t OEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If OE# is taken back LOW while remains LOW, the DQs will remain open. 25. Column address changed once each cycle. 26. IH overshoot: IH (MAX) = CC + 2 for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. undershoot: (MIN) = -2 for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate.
READ CYCLE t RC t RAS t RP IH t CSH t RSH t RRH t CRP t RCD IH t RAD t AR tcah t ASR t RAH ADDR IH t RCS t RCH IH t AA t RAC t CAC t OFF t CLZ DQ IOH IOL ALID DATA DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 30 ns t AR 40 45 ns 0 0 ns t ASR 0 0 ns t CAC 13 15 ns 10 ns 13 10,000 15 10,000 ns t CLZ 3 3 ns t CRP 5 5 ns t CSH 50 60 ns t OD 3 13 3 15 ns t OE 13 15 ns t OFF 3 13 3 15 ns t RAC 50 60 ns t RAD 13 15 ns t RAH 10 ns t RAS 50 10,000 60 10,000 ns t RC 90 110 ns t RCD 1 20 ns t RCH 0 0 ns t RCS 0 0 ns t RP 30 40 ns t RRH 0 0 ns t RSH 13 15 ns 9
EARLY WRITE CYCLE t RC t RAS trp IH t CSH t RSH t CRP t RCD IH t AR t RAD t ASR t RAH ADDR IH t CWL t RWL t WCR t WCS t WCH t WP IH t DS t DH DQ IOH IOL ALID DATA DON T CARE UNDEFINED TIMING PARAMETERS t AR 40 45 ns 0 0 ns t ASR 0 0 ns 10 ns 13 10,000 15 10,000 ns t CRP 5 5 ns t CSH 50 60 ns t CWL 13 15 ns t DH 10 ns t DS 0 0 ns t RAD 13 15 ns t RAH 10 ns t RAS 50 10,000 60 10,000 ns t RC 90 110 ns t RCD 1 20 ns t RP 30 40 ns t RSH 13 15 ns t RWL 13 15 ns t WCH 10 ns t WCR 40 45 ns t WCS 0 0 ns t WP 10 ns 10
READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RWC t RAS trp IH t CSH t RSH t CRP t RCD IH t AR t RAD t ASR t RAH ADDR IH t RWD t CWL t RCS t CWD t AWD t RWL t WP IH t AA t RAC t CAC t DS t DH t CLZ DQ IOH IOL ALID D OUT ALID D IN t OE t OD t OEH OE# IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 30 ns t AR 40 45 ns 0 0 ns t ASR 0 0 ns t AWD 4 55 ns t CAC 13 15 ns 10 ns 13 10,000 15 10,000 ns t CLZ 3 3 ns t CRP 5 5 ns t CSH 50 60 ns t CWD 36 40 ns t CWL 13 15 ns t DH 10 ns t DS 0 0 ns t OD 3 13 3 15 ns t OE 13 15 ns t OEH 13 15 ns t RAC 50 60 ns t RAD 13 15 ns t RAH 10 ns t RAS 50 10,000 60 10,000 ns t RCD 1 20 ns t RCS 0 0 ns t RP 30 40 ns t RSH 13 15 ns t RWC 131 155 ns t RWD 73 5 ns t RWL 13 15 ns t WP 10 ns 11
FAST-PAGE-MODE READ CYCLE t RASP t RP IH t CSH t PC t RSH t CRP t RCD IH t AR t RAD t ASR t RAH ADDR IH t RCS t RCS t RRH t RCS t RCH t RCH t RCH IH t AA t AA t AA t RAC A A t CAC t OFF t CAC t OFF t CAC t OFF t CLZ t CLZ t CLZ DQ IOH IOL ALID ALID ALID DATA DATA DATA t OE t OD t OE t OD t OE t OD OE# IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 30 ns t AR 40 45 ns 0 0 ns t ASR 0 0 ns t CAC 13 15 ns 10 ns 13 10,000 15 10,000 ns t CLZ 3 3 ns 10 ns A 30 35 ns t CRP 5 5 ns t CSH 50 60 ns t OD 3 13 3 15 ns t OE 13 15 ns t OFF 3 13 3 15 ns t PC 30 35 ns t RAC 50 60 ns t RAD 13 15 ns t RAH 10 ns t RASP 50 125,000 60 125,000 ns t RCD 1 20 ns t RCH 0 0 ns t RCS 0 0 ns t RP 30 40 ns t RRH 0 0 ns t RSH 13 15 ns 12
FAST-PAGE-MODE EARLY WRITE CYCLE t RASP t RP IH t CSH t PC t RSH t CRP t RCD IH t AR t RAD t ASR t RAH ADDR IH t CWL t CWL t CWL t WCS t WCH t WCS t WCH t WCS t WCH t WP t WP t WP IH t WCR t RWL t DS t DH t DS t DH t DS t DH DQ IOH IOL ALID DATA ALID DATA ALID DATA OE# IH DON T CARE UNDEFINED TIMING PARAMETERS t AR 40 45 ns 0 0 ns t ASR 0 0 ns 10 ns 13 10,000 15 10,000 ns 10 ns t CRP 5 5 ns t CSH 50 60 ns t CWL 13 15 ns t DH 10 ns t DS 0 0 ns t RAD 13 15 ns t RAH 10 ns t RASP 50 125,000 60 125,000 ns t RCD 1 20 ns t RP 30 40 ns t RSH 13 15 ns t RWL 13 15 ns t WCH 10 ns t WCR 40 45 ns t WCS 0 0 ns t WP 10 ns t PC 30 35 ns 13
FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RASP t RP IH t CRP t CSH NOTE 1 t PC t PRWC t RCD t RSH tcp IH t AR t RAD t ASR t RAH ADDR IH t RWD t RWL t RCS t CWL t CWL t CWL t WP t AWD t WP t AWD t AWD t WP t CWD t CWD t CWD IH t AA t AA t AA t RAC t DS t DH A t DS t DH A t DS t DH t CAC t CLZ t CAC t CLZ t CAC t CLZ DQ IOH IOL ALID D OUT ALID D IN ALID D OUT ALID D IN ALID D OUT ALID D IN t OD t OD t OD t OE t OE t OE t OEH OE# IH DON T CARE TIMING PARAMETERS t AA 25 30 ns t AR 40 45 ns 0 0 ns t ASR 0 0 ns t AWD 4 55 ns t CAC 13 15 ns 10 ns 13 10,000 15 10,000 ns t CLZ 3 3 ns 10 ns A 30 35 ns t CRP 5 5 ns t CSH 50 60 ns t CWD 36 40 ns t CWL 13 15 ns t DH 10 ns t DS 0 0 ns UNDEFINED t OD 3 13 3 15 ns t OE 13 15 ns t OEH 13 15 ns t PC 30 35 ns t PRWC 76 5 ns t RAC 50 60 ns t RAD 13 15 ns t RAH 10 ns t RASP 50 125,000 60 125,000 ns t RCD 1 20 ns t RCS 0 0 ns t RP 30 40 ns t RSH 13 15 ns t RWD 73 5 ns t RWL 13 15 ns t WP 10 ns NOTE: 1. t PC is for LATE WRITE only. 14
FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP t RP IH t RSH t CSH t PC t CRP t RCD IH t AR t RAD t ASR t RAH ADDR IH t CWL t RCS t RWL t WP t WCS t WCH IH t CAC t CLZ NOTE 1 t OFF t DS t DH DQ OH OL ALID DATA ALID DATA t AA trac DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 30 ns t AR 40 45 ns 0 0 ns t ASR 0 0 ns t CAC 13 15 ns 10 ns 13 10,000 15 10,000 ns t CLZ 3 3 ns 10 ns t CRP 5 5 ns t CSH 50 60 ns t CWL 13 15 ns t DH 10 ns t DS 0 0 ns t OFF 3 13 3 15 ns t PC 30 35 ns t RAC 50 60 ns t RAD 13 15 ns t RAH 10 ns t RASP 50 125,000 60 125,000 ns t RCD 1 20 ns t RCS 0 0 ns t RP 30 40 ns t RSH 13 15 ns t RWL 13 15 ns t WCH 10 ns t WCS 0 0 ns t WP 10 ns NOTE: 1. Do not drive input data prior to output data going High-Z. 15
-ONLY REFRESH CYCLE (OE# and = DON T CARE) t RC t RAS t RP IH t CRP t RPC IH t ASR t RAH ADDR IH DQ OH OL CBR REFRESH CYCLE (Addresses and OE# = DON T CARE) t RP t RAS NOTE 1 t RP t RAS IH t RPC t CSR t CHR t RPC t CSR tchr IH DQ OH OL t WRP t WRH t WRP t WRH IH DON T CARE UNDEFINED TIMING PARAMETERS t ASR 0 0 ns t CHR 15 15 ns 10 ns t CRP 5 5 ns t CSR 5 5 ns t RAH 10 ns t RAS 50 10,000 60 10,000 ns t RC 90 110 ns t RP 30 40 ns t RPC 5 5 ns t WRH 10 10 ns t WRP 10 10 ns NOTE: 1. End of CBR REFRESH cycle. 16
HIDDEN REFRESH CYCLE 1 ( = HIGH; OE# = LOW) t RAS t RP t RAS IH t CRP t RCD t RSH t CHR IH t AR t RAD t ASR t RAH ADDR IH t AA t RAC t CAC t OFF t CLZ DQ IOH IOL ALID DATA t OE t OD OE# IH t ORD DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 30 ns t AR 40 45 ns 0 0 ns t ASR 0 0 ns t CAC 13 15 ns 10 ns t CHR 15 15 ns t CLZ 3 3 ns t CRP 5 5 ns t OD 3 13 3 15 ns t OE 13 15 ns t OFF 3 13 3 15 ns t ORD 0 0 ns t RAC 50 60 ns t RAD 13 15 ns t RAH 10 ns t RAS 50 10,000 60 10,000 ns t RCD 1 20 ns t RP 30 40 ns t RSH 13 15 ns NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, = LOW and OE# = HIGH. 17
SELF REFRESH CYCLE (Addresses and OE# = DON T CARE) t RP t RASS ( ) ( ) NOTE 1 t RPS NOTE 2 IH t RPC ( ( t RPC ( ( ) ) ) ) t CSR t CHD IH ( ) ( ) ( ) ( ) DQ OH OL IH ( ( ) ) t WRP t WRH ( ( ) ) ( ) ( ) t WRP t WRH DON T CARE UNDEFINED TIMING PARAMETERS t CHD 15 15 ns 10 ns t CSR 5 5 ns t RASS 100 100 µs t RP 30 40 ns t RPC 5 5 ns t RPS 90 105 ns t WRH 10 10 ns t WRP 10 10 ns NOTE: 1. Once t RASS (MIN) is met and remains LOW, the DRAM will enter self refresh mode. 2. Once t RPS is satisfied, a complete burst of all rows should be executed if -only or burst CBR is used. 1
32-PIN PLASTIC SOJ (400 mil).29 (21.05).23 (20.90).445 (11.31).435 (11.05).405 (10.29).399 (10.13) PIN #1 ID.050 (1.27) TYP.750 (19.05) TYP.037 (0.95) MAX DAMBAR PROTRUSION.024 (0.61).032 (0.2).026 (0.67).030 (0.76) MIN SEATING PLANE.145 (3.6).132 (3.35).095 (2.42).00 (2.03).020 (0.51).015 (0.3) R.040 (1.02).030 (0.77).30 (9.65).360 (9.14) NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is.01" per side. 19
32-PIN PLASTIC TSOP (400 mil) 1.27 TYP 20.96 ±0.0 0.95 SEE DETA A 11.76 ±0.10 10.16 ±0.0 PIN 1 ID 0.43 +0.07-0.13 0.15 +0.03-0.02 1.20 MAX 0.10 0.25 GAGE PLANE 0.10 +0.10-0.05 0.0 TYP 0.50 ±0.10 DETA A NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is.25mm per side. 000 S. Federal Way, P.O. Box 6, Boise, ID 3707-0006, Tel: 20-36-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 00-932-4992 Micron is a registered trademark of Micron Technology, Inc. 20