6.012 Microelectronic Devices and Circuits Lecture 20 DiffAmp Anal. I: Metrics, Max. Gain Outline Announcements Announcements D.P.: No Early effect in large signal analysis; just LECs. Lec. 21 foils useful; Sp 06 DP foils, too (on Stellar) Do PS #10: free points while workinn D.P. Review Differential Amplifier Basics Difference and commonmode signals: v ID v IN1 v IN 2, v IC (v IN1 v IN2 )/2 Halfcircuits: half of original with wires shorted or cut (familiar, easy analyses) Performance metrics specific to diff. amps. Difference and commonmode gains Commonmode rejection ratio Input and output voltage swings Nonlinear loads The limitation of resistive loads: Gain limited by voltage supply Nonlinear loads: High incremental resistance/small voltage drop Active loads Lee load Current mirror load Clif Fonstad, 11/19/09 Lecture 20 Slide 1
Differential Amplifiers overview of features and properties Intrinsic advantages and features: large difference mode gain small common mode gain easy to cascade stages; no coupling capacitors no emitter/source capacitors in CS/CE stages Performance metrics: difference mode voltage gain, A vd Today common mode voltage gain, A vc Today input resistance, R in output resistance, R out Lec 21 common mode input voltage range Today output voltage swing Today DC offset on output Lec 21 Power dissipation Lec 18 Clif Fonstad, 11/19/09 Lecture 20 Slide 2
Differential Amplifiers commonmode input range (V C,min v C V C,max ) We have said the output changes very little for commonmode inputs. This is true as long as the v C doesn't push the transistors out of saturation. There are a minimum and maxiumum v C : V C, max : As v C increases, v DS8 and v DS9 decrease until Q 8 and Q 9 are no longer in saturation. V C, min : As v C decreases, v DS10 decreases until Q 10 is no longer in saturation. v GS stays constant v C up v C down B The node between Q 8 /Q 9 and Q 10 moves up and down with v C. Clif Fonstad, 11/19/09 Lecture 20 Slide 3 Q 4 Q 5 Q 6 1.5 V Q 7 Q smaller 8 Q 9 v GS stays constant v DS v DS gets v c v GS vgs down v DS Q 10 v DS 1.5 V v DS gets smaller Q 8, Q 9 forced out of saturation if v C too high v C up Q 10 forced out of saturation if v c too low
Differential Amplifiers output voltage range! 0.6V v GS15 v SD12 Q 13 v SG12 Q 12 Fixed A Q 16 Q 17 1.5 V! 0.6V Q 19 v DS15 B Q 15 Fixed v GS19 v SG16! 0.6V v SD16 (V OUT,min v OUT V OUT,max ) v SD12 and v SD16 decrease as v OUT goes up, so Q 12 and/or Q 16 may be forced out of saturation if v OUT is too high As v OUT goes down, Q 15 and/or Q 19 may go out of saturation; as v OUT goes up, the same may happen to Q 12 and/or Q 16. 1.5 V! 0.6V Q 18! 0.6V v DS19 Q 20 v OUT up v OUT down Q 21 v DS15 and v DS19 decrease as v OUT goes down, so Q 15 and/or Q 19 may be forced out of saturation if v OUT is too low Clif Fonstad, 11/19/09 Lecture 20 Slide 4
Differential Amplifier Analysis incremental analysis exploiting symmetry and superposition v id a LEHC: one half of sym. LEC a LEHC: one half of sym. LEC v id v id a LEHC: one half of sym. LEC v od No voltage on common links, so incrementally they are grounded. v od v od A vd v id v ic a LEHC: one half of sym. LEC a LEHC: one half of sym. LEC v ic v ic a LEHC: one half of sym. LEC v oc No current in common links, so incrementally they are open. v oc v oc A vc v ic Clif Fonstad, 11/19/09 Lecture 20 Slide 5
Looking at the design problem circuit: Lesson Draw the difference and common mode half circuits. Difference mode half circuit: r olldm r ocmdm Q 17 Q 20 v id Q 8 Q 12 r oq16 v od R LOAD Common mode half circuit: v ic r ollcm r ocmcm Q 17 Q 20 Q 8 Q 12 2r oq10 r oq16 v oc R LOAD We have reduced the transistor count from 22 to 4, and we see that our complex amplifier is a just cascade of 4 singletransistor stages. Clif Fonstad, 11/19/09 Lecture 20 Slide 6
What's with these active, nonlinear loads? Why doesn't the design problem use resistors? V Linear Resistor Loads: the limit on maximum stage gain with linear resistor loads we must make a compromise between the voltage gain and the size of the output voltage swing. Maximum voltage gains g v in v gs s,b g m v gs MOSFET " : A v,max g m d v out s,b G SL (1/ ) v in I BIAS V Q 2 I D [ V GS #V T ] $ 2 [ I R D SL] max [ V GS #V T ] min C O v out C S Bipolar : A v,max g m qi C kt [ $ I R C SL ] max V Thermal What are [I C ] max, [I D ] max, and [V GS V T ] min? * For a MOSFET, g m (2KI D /α) 1/2 K(V GS V T )/α 2I D /(V GS V T ) Clif Fonstad, 11/19/09 Lecture 20 Slide 7
Resistor Loads: cont. What are [I D ] max, [I C ] max, and [V GS V T ] min? [I D ] max, [I C ] max : [I D ] max and [I C ] max are determined by the desired voltage swing at the output and/or by the commonmode input voltage range. The ultimate limit is the power supply. [V GS V T ] min : [V GS V T ] min is set by how close to threshold the gate can safely be biased before the strong inversion, drift model fails. We will say more about this shortly (Slide 23). v in I BIAS V V Q C O v out C S Clif Fonstad, 11/19/09 Lecture 20 Slide 8
V REF Current Source Loads: Incrementally large resistance Relatively small quiescent voltage drop transistors with a DC input voltage, i.e. set up as sources/sinks MOSFET: V REF V REF Bipolar: V REF g v gs 0 s v bs 0 b b e g! v! 0 g m v gs 0 g m v! 0 " I C I C V A g mb v bs 0 " I D I D V A d c s e d s, b, g c e, b Clif Fonstad, 11/19/09 Lecture 20 Slide 9
Current Source Loads: the limit on the maximum stage gain current source loads eliminate the need to compromise between the voltage gain and the output voltage swing Maximum voltage gains g v in v gs s,b g m v gs MOSFET " : A v,max Bipolar : A v,max with V A,eff " d I BIAS v out g sl V s,b g m g sl g m g sl V V A,Q A,SL [ V A,Q V A,SL ], V t " kt q v in [ ] 2I D V GS #V T $ I D V A,Q I D V A,SL V Q qi C kt V A,eff I C V A,Q I C V A,SL I Stage Load 2V A,eff [ V GS #V T ] min V t C O v out C S Typically V A,eff >> [I D ] max Clif Fonstad, 11/19/09 * For a MOSFET, g (2KI D /α) 1/2 K(V GS V T )/α 2I D /(V GS V T ) Lecture 20 Slide 10 m
Current Source Loads: the maximum stage gain, cont. the similarity in the results for BJT's and MOSFETs operating in strong inversion extends to MOSFETs operating subthreshold and in velocity saturation, also: Maximum voltage gains g v in v gs s,b g m v gs d v out s,b The MOSFET LEC: the same for all. g sl ( MOSFET sub threshold : i D I S,s"t e v GS "V T ) nv t, g m I D nv t A v,max g m g sl I D nv t V A,eff I D V A,Q I D V A,SL nv t * MOSFET w. velocity saturation : i D W s sat C ox A v,max g m g sl I D ( v GS "V T ), g m W s sat C ox ( v GS "V T ) I D V A,Q I D V A,SL # V A,eff ( v GS "V T ) min * I D ( ) v GS "V T with V A,eff " V A,QV A,SL [ V A,Q V A,SL ] Clif Fonstad, 11/19/09 Lecture 20 Slide 11
Current Source Loads: Example biasing a sourcecoupled pair differential amplifer stage Want: V Build: V Q 1 Q 2 Q 3 I LOAD I LOAD Q 4 v O1 v O2 Q 5 v IN1 v IN2 R 1 Q 4 v O1 v O2 Q 5 v IN1 V I BIAS Note: I LOAD I BIAS /2 Q 6 V Q 7 Note: W 1 W 2 W 3 W 7 2W 6 This is nice can we do even better? Yes, with active loads. Consider Clif Fonstad, 11/19/09 Lecture 20 Slide 12
Active Loads: Loads that don't just sit there and look pretty. First example: the current mirror load V Q 2 v I1 Q 1 Q 3 Q 4 V I BIAS, r ob v I2 v OUT Signal actively fed from left side to right side, and applied inputs to "stage load" MOSFETs. Now "single ended," i.e. only one output, but it is twice as large: v out 2v out1 Load selfadjusting; circuit forces I LOAD I BIAS /2. Clif Fonstad, 11/19/09 Lecture 20 Slide 13
Active Loads: The current mirror load, cont. Large differentialmode gain, small commonmode gain. Also provides high gain conversion from doubleended to singleended output. The circuit is no longer symmetrical, so halfcircuit techniques can not be applied. The full analysis is found in the course text. We find: i d i d Q 1 V Q 2 Q 3 Q 4 v id /2 v id /2 I BIAS, r ob V i d i d 2i d v OUT Differencemode inputs v out,d 2g m 3 ( ) v id 2 2 4 g el Clif Fonstad, 11/19/09 Lecture 20 Slide 14
Active Loads: The current mirror load V Q 2 Commonmode inputs Q 1 v out,c b 2g m2 v ic i c i c i c 0 i c With both inputs: v out 2g m3 v ic ( ) 2 4 g el Q 3 Q 4 V ( v in1 " v in 2 ) 2 I BIAS, r ob v ic " g v ob in1 v in 2 2g m2 2 ( ) v OUT Note: In D.P. the output goes to the base of two BJTs; g el 0 and can Clif Fonstad, 11/19/09 be important. Lecture 20 Slide 15
What if we want an active load and yet stay differential? Active Loads The Lee load A load for a fullydifferential stage that looks like a large resistance in differencemode and small resistance in commonmode) The conventional schematic is drawn here, but the coupling of the load and what is happening is made clearer by redrawing the circuit (next slide.) Q 1 Q 2 V Q 4 Q 3 Q 5 Q 6 v O1 v O2 v I1 I BIAS, r ob V Normal format v I2 Clif Fonstad, 11/19/09 Lecture 20 Slide 16
Active Loads Drawn as on the right we see that the load MOSFETs on each side are driven by both outputs. The result is different if the two outputs are equal and opposite (diffmode operation) or if they are equal (commonmode). The next few slides give the results for each mode. Clif Fonstad, 11/19/09 The Lee load. cont. v I1 V V Q 1 Q 3 Q 2 v O1 v O2 v O1 I BIAS, r ob v O2 Q 4 Q 5 Q 6 v O1 v O2 v I2 Drawn to highlight crosscoupling and demonstrate symmetry Lecture 20 Slide 17
V Q 4 The Lee load: analysis for differencemode inputs LEHC: differencemode Q 5 Q 6 v od v od v id Q 1 Q 3 Q 2 v od v od v od V I BIAS, r ob v od v id v id /2 v gs5 g m5 v id /2 5 g m1 v od /2 1 g m3 v od /2 3 v od /2 g el LLd Clif Fonstad, 11/19/09 Lecture 20 Slide 18
The Lee load: analysis for differencemode inputs, cont LEHC: differencemode v id /2 v gs5 5 1 g m5 v id /2 g m1 v od /2 g m3 v od /2 3 v od /2 g el v id /2 v gs5 g m5 v id /2 5 g m1 1 g m1 1 v od /2 g el g v id /2 v gs5 s,b g m5 v gs5 5 d s,b LLd v od /2 g el LLd 2 1 A vd v od v id "g m5 ( ) 5 21 g e1 Clif Fonstad, 11/19/09 Note: In D.P., the outputs go to MOSFET gates so g el 0. Lecture 20 Slide 19
V The Lee load: analysis for commonmode inputs v oc Q 1 Q 3 Q 2 LEHC: commonmode V v ic v gs5 b /2 g m5 v gs5 5 v oc v oc v oc I BIAS, r ob Q 4 Q 5 Q 6 v oc v oc g m1 v oc 1 g m3 v oc 3 v oc v oc v I2 g el Clif Fonstad, 11/19/09 LLc Lecture 20 Slide 20
The Lee load: analysis for commonmode inputs, cont LEHC: commonmode v ic v gs5 5 g m5 v gs5 g m1 1 g m1 1 b /2 v oc g el g v ic v gs5 s,b b /2 g m5 v gs5 5 s,b d LLc v oc g el LLc 2( g m1 1 ) " 2g m1 A vc v oc v ic "b [ ] # " b 2 2( g m1 1 ) g e1 4g m1 Clif Fonstad, 11/19/09 Note: In D.P., the outputs go to MOSFET gates so g el 0. Lecture 20 Slide 21
Achieving the maximum gain: Comparing linear resistors, current sources, and active loads Maximum Gains MOSFET (SI) Bipolarlike (BJT and SubV T MOS) Linear resistor loads Current source loads Active loads Difference mode [ ] max [ " I C ] max [ ] min " 2 I D v GS #V T " $ 2V A,eff v GS #V T n V t [ ] min " V A,eff 2V A,eff v GS #V T n V t [ ] min $ V A,eff n V t [ ] min Common mode $ v GS #V T $ n V t 2V A,bias V A,bias Observations: Nonlinear (current source) loads typically yield much higher gain than linear resistors, i.e. V A,eff >> [I D ] max. The bias point is not as important to BJTtype stage gain. An SI MOSFET should be biased just above threshold for highest gain. For active loads what increases A vd, decreases A vc. Clif Fonstad, 11/19/09 Lecture 20 Slide 22
Achieving the maximum gain: (v GS V T ) min? For SIMOSFETs, maximizing the voltage gain (A v or A vd ) requires minimizing (V GS V T ). What is the limit? Sub threshold : A v 1 V A n V t Strong inversion : A v V A 2 ( ) V GS "V T A v /V A is a smooth curve, so clearly (V GS V T ) min > 2nV t.? Note: n 1.25 was assumed. Clif Fonstad, 11/19/09 Lecture 20 Slide 23
6.012 Microelectronic Devices and Circuits Lecture 20 DiffAmp Analysis I Summary Performance metrics specific to diff. amps. Difference and commonmode gains: A vd v od /v id, A Commonmode rejection ratio: CMRR A vd /A vc Commonmode input range Nonlinear loads Transistors biased in their constant current regions: MOSFETs in saturation BJTs in their FAR vc v oc /v ic Active loads Current mirror load: Achieves double to singleended conversion without loss of gain Has high resistance for differencemode signals Has low resistance for commonmode signals Lee Load: Maintains differential signals Has high resistance for differencemode signals Has low resistance for commonmode signals Clif Fonstad, 11/19/09 Lecture 20 Slide 24
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