INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS Logic Family Specifications The IC6 74C/CT/CU/CMOS Logic Package Information The IC6 74C/CT/CU/CMOS Logic Package Outlines File under Integrated Circuits, IC6 December 9
FEATURES Multiplexed inputs/outputs provide improved bit density Four operating modes: shift left shift right hold (store) load data Operates with output enable or aigh-impedance OFF-state (Z) 3-state outputs drive bus lines directly Can be cascaded for n-bits word length Output capability: bus driver (parallel I/Os), standard (serial outputs) I CC category: MSI GENERAL DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The contain eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. The type of operation is determined by the mode select inputs (S and S 1 ), as shown in the mode select table. All flip-flop outputs have 3-state buffers to separate these outputs (I/O to I/O 7 ) such, that they can serve as data inputs in the parallel load mode. The serial outputs (Q and Q 7 ) are used for expansion in serial shifting of longer words. A LOW signal on the asynchronous master reset input (MR) overrides the S n and clock (CP) inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is either state, provided that the recommended set-up and hold times, relative to the rising edge of CP, are observed. A IG signal on the 3-state output enable inputs (OE 1 or OE 2 ) disables the 3-state buffers and the I/O n outputs are set to the high-impedance OFF-state. In this condition, the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by IG signals on both S and S 1, when in preparation for a parallel load operation. QUICK REFERENCE DATA GND = V; T amb =2 C; t r =t f = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS C CT UNIT t PL/ t PL C L = 1 pf; V CC = V CP to Q, Q 7 2 ns CP to I/O n 2 ns t PL MR to Q, Q 7 or I/O n 2 23 ns f max maximum clock frequency 46 Mz C I input capacitance 3. 3. pf C I/O input/output capacitance 1 1 pf C PD power dissipation capacitance per package notes 1 and 2 12 12 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V December 9 2 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1. V ORDERING INFORMATION See 74C/CT/CU/CMOS Logic Package Information.
PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, S, S 1 mode select inputs 2, 3 OE 1, OE 2 3-state output enable inputs (active LOW) 7, 13, 6, 14,, 1, 4, 16 I/O to I/O 7 parallel data inputs or 3-state parallel outputs (bus driver) 8, Q, Q 7 serial outputs (standard output) 9 MR asynchronous master reset input (active LOW) 1 GND ground ( V) 11 D SR serial data shift-right input 12 CP clock input (LOW-to-IG, edge-triggered) 18 D SL serial data shift-left input 2 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 9 3
Fig.4 Functional diagram. MODE SELECT TABLE INPUTS RESPONSE MR S 1 S CP L X X X asynchronous reset; Q Q 7 = LOW L L L L X Notes 1. = IG voltage level L = LOW voltage level X = don t care = LOW-to-IG CP transition parallel load; I/O n Q n shift right; D SR Q, Q Q 1 etc. shift left; D SL Q 7, Q 7 Q 6 etc. hold December 9 4
Fig. Logic diagram. December 9
DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS Logic Family Specifications. Output capability: bus driver (parallel I/Os) standard (serial outputs) I CC category: MSI AC CARACTERISTICS FOR 74C GND = V; t r =t f = 6 ns; C L = pf SYMBOL t PL / t PL t PL / t PL t PL / t PZ t PZL t PZ t PLZ t TL / t TL t TL / t TL t W t W PARAMETER 66 CP to Q, Q 7 24 66 CP to I/O n 24 66 MR to Q, Q 7 or I/O n 24 3-state output enable time OE n to I/O n 18 14 3-state output enable time 41 OE n to I/O n 1 12 3-state output disable time 66 OE n to I/O n 24 3-state output disable time OE n to I/O n 2 16 output transition time bus driver (I/O n ) output transition time standard (Q, Q 7 ) clock pulse width IG or LOW master reset pulse width LOW T amb ( C) 74C +2 4 to +8 4 to +12 min. typ. max. min. max. min. max. 8 16 14 8 16 14 14 4 7 6 6 7 6 2 4 34 2 4 34 2 4 34 1 31 13 22 18 37 31 1 31 6 12 1 7 1 13 1 2 1 2 2 43 2 43 2 43 39 16 28 23 46 39 39 7 1 13 9 16 12 24 2 12 24 2 3 6 1 3 6 1 3 6 1 23 47 4 39 28 6 48 23 47 4 9 18 1 11 22 UNIT TEST CONDITIONS V CC (V) ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. WAVEFORMS Fig.7 Fig.9 Fig.9 Fig.9 Fig.9 Fig.7 December 9 6
T amb ( C) TEST CONDITIONS SYMBOL PARAMETER 74C +2 4 to +8 4 to +12 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t rem f max removal time MR to CP set-up time D SR, D SL to CP set-up time S, S 1 to CP set-up time I/O n to CP hold time I/O n, D SR, D SL to CP hold time S, S 1 to CP maximum clock pulse frequency 1 2 1 2 12 2 21. 2 29 14 4 12 1 12 1 39 14 11 14 4 28 1 8 1 4 4 12 2 21 12 2 21 1 31 4. 2 24 1 3 1 3 38 32 3.4 2 ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. ns 2. 6. Mz 2. 6. Fig.7 Fig.8 Fig.8 December 9 7
DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS Logic Family Specifications. Output capability: bus driver (parallel I/Os) standard (serial outputs) I CC category: MSI Note to CT types The value of additional quiescenpply current ( I CC ) for unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT I/O n D SR, D SL CP, S MR, S 1 OE n UNIT LOAD COEFFICIENT.2.2.6.2.3 December 9 8
AC CARACTERISTICS FOR 74CT GND = V; t r =t f = 6 ns; C L = pf SYMBOL t PL / t PL t PL / t PL t PL t PZ / t PZL t PZ t PLZ t TL / t TL t TL / t TL t W t W t rem f max T amb ( C) TEST CONDITIONS 74CT PARAMETER UNIT V WAVEFORMS +2 4 to +8 4 to +12 CC (V) min. typ. max. min. max. min. max. 22 37 46 6 ns CP to Q, Q 7 22 37 46 6 ns CP to I/O n 27 46 8 69 ns Fig.7 MR to Q, Q 7 or I/O n 3-state output enable time 3 38 4 ns Fig.9 OE n to I/O n 3-state output disable time 24 37 46 6 ns Fig.9 OE n to I/O n 3-state output disable time 2 32 4 48 ns Fig.9 OE n to I/O n output transition time 12 1 18 ns bus driver (I/O n ) output transition time 7 1 22 ns standard (Q, Q 7 ) clock pulse width 2 1 2 3 ns IG or LOW master reset pulse width 2 11 2 3 ns Fig.7 LOW removal time 1 2 9 11 ns Fig.7 MR to CP set-up time 2 14 31 38 ns I/O n, D SR, D SL to CP set-up time 32 18 4 48 ns Fig.8 S, S 1 to CP hold time 11 ns I/O n, D SR, D SL to CP hold time ns Fig.8 S, S 1 to CP maximum clock pulse 2 42 2 Mz frequency December 9 9
AC WAVEFORMS handbook, full pagewidth I/O,D,D n SR SL INPUTS V M (1) 1/ f max CP INPUT V M (1) t PL t W t PL The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = %; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. I/O n,q,q 7 OUTPUTS MBA V M (1) t TL t TL Waveforms showing the clock (CP) to output (I/O n, Q, Q 7 ) s, the clock pulse width, the I/O n, D SR and D SL to CP set-up and hold times, the output transition times and the maximum clock frequency. (1) C : V M = %; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the master reset (MR) pulse width (LOW), the master reset to output (I/O n, Q, Q 7 ) s and the master reset to clock (CP) removal time. December 9 1
(1) C : V M = %; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.8 Waveforms showing the set-up and hold times from the mode control inputs (S, S 1 ) to the clock (CP). (1) C : V M = %; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.9 Waveforms showing the 3-state enable and disable times for OE n inputs. PACKAGE OUTLINES See 74C/CT/CU/CMOS Logic Package Outlines. December 9 11