Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1

Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation regions of cutoff, triode and saturation. Develop mathematical models for i-v characteristics of MOSFETs. Introduce graphical representations for output and transfer characteristic descriptions of electron devices. Define and contrast characteristics of enhancement-mode and depletion-mode FETs. Define symbols to represent FETs in circuit schematics. Investigate circuits that bias transistors into different operating regions. Learn basic structure and mask layout for MOS transistors and circuits. Explore MOS device scaling Contrast 3 and 4 terminal device behavior. Describe sources of capacitance in MOSFETs. Explore FET modeling in SPICE. 5/5/11 Chap 4-2

MOS Capacitor Structure First electrode - Gate: Consists of low-resistivity material such as metal or doped polycrystalline silicon Second electrode - Substrate or Body: n- or p-type semiconductor Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. 5/5/11 Chap 4-3

Substrate Conditions for Different Biases Accumulation Inversion Depletion Accumulation V G << V TN Depletion V G < V TN Inversion V G > V TN 5/5/11 Chap 4-4

Low-frequency C-V Characteristics for an MOS Capacitor on p-type Substrate MOS capacitance is a nonlinear function of voltage. Total capacitance in any region is dictated by the separation between capacitor plates. Total capacitance modeled as series combination of fixed oxide capacitance and voltage-dependent depletionlayer capacitance. 5/5/11 Chap 4-5

NMOS Transistor: Structure 4 device terminals: Gate(G), Drain(D), Source(S) and Body(B). Source and drain regions form pn junctions with substrate. v SB, v DS and v GS always positive during normal operation. v SB always < v DS and v GS to reverse bias pn junctions 5/5/11 Chap 4-6

NMOS Transistor: Qualitative I-V Behavior V GS << V TN : Only small leakage current flows. V GS < V TN : Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. V GS > V TN : Channel formed between source and drain. If v DS > 0, finite i D flows from drain to source. i B = 0 and i G = 0. 5/5/11 Chap 4-7

NMOS Transistor: Triode Region Characteristics i D = K n v GS V TN v DS v 2 DS for v GS V TN v DS 0 K n = K n ' W L K n ' " = µ n C ox (A/V 2 ) " C ox = ε ox T ox ε ox = oxide permittivity (F/cm) T ox = oxide thickness (cm) 5/5/11 Chap 4-8

NMOS Transistor: Triode Region Characteristics (cont.) Output characteristics appear to be linear. FET behaves like a gate-source voltage- controlled resistor between source and drain with R on = i D v DS v DS 0 1 Q Pt = 1 ' W K n ( L V V V GS TN DS) V DS 0 = 1 ' W K n ( L V V GS TN) 5/5/11 Chap 4-9

MOSFET as a Voltage-Controlled Resistor Example 1: Voltage-Controlled Attenuator v O v S = R on R on + R = 1 ( ) 1+ K n R V GG V TN If K n = 500µA/V 2, V TN = 1V, R = 2kΩ and V GG = 1.5V, then, v O v S = 1+ 500 µa V 2 To maintain triode region operation, 1 ( 2000Ω)1.5 ( 1)V = 0.667 v DS v GS V TN or v O V GG V TN 0.667v S ( 1.5 1)V or v S 0.750 V 5/5/11 Chap 4-10

MOSFET as a Voltage-Controlled Resistor (cont.) Example 2: Voltage-Controlled High-Pass Filter Voltage Transfer function, where, cut-off frequency T( s)= V O s s ω o = 1 = K n V GS V TN R on C C V S ( ) ( ) ( ) = s If K n = 500µA/V 2, V TN = 1V, C = 0.02µF and V GG = 1.5V, then, 500 µa ( 1.5 1)V f o = V 2 =1.99 khz 2π 0.02µF ( ) To maintain triode region operation, v S V GG V TN = 0.5 V s +ω o 5/5/11 Chap 4-11

NMOS Transistor: Saturation Region If v DS increases above triode region limit, the channel region disappears and is said to be pinched-off. Current saturates at constant value, independent of v DS. Saturation region operation mostly used for analog amplification. 5/5/11 Chap 4-12

NMOS Transistor: Saturation Region (cont.) i D = K ' n 2 W L v GS V TN ( ) 2 for v DS v GS V TN v DSAT = v GS V TN is termed the saturation or pinch - off voltage 5/5/11 Chap 4-13

Transconductance of an MOS Device Transconductance relates the change in drain current to a change in gate-source voltage g m = i D v v GS Q pt Taking the derivative of the expression for the drain current in saturation region, ' W g m = K ( n L V V GS TN)= 2I D V GS V TN 5/5/11 Chap 4-14

Channel-Length Modulation As v DS increases above v DSAT, the length of the depleted channel beyond the pinch-off point, L, increases and the actual L decreases. i D increases slightly with v DS instead of being constant. i D = K ' n 2 W L v GS V TN ( ) 2 1+ λv DS ( ) λ = channel length modulation parameter 5/5/11 Chap 4-15

Depletion-Mode MOSFETS NMOS transistors with V TN < 0 Ion implantation process is used to form a built-in n-type channel in the device to connect source and drain by a resistive channel Non-zero drain current for v GS = 0 Negative v GS required to turn device off. 5/5/11 Chap 4-16

Transfer Characteristics of MOSFETS Enhancement- & Depletion-Mode Devices Transfer Characteristic: Plots drain current versus gatesource voltage for a fixed drain-source voltage 5/8/11 Chap 4-17

Body Effect or Substrate Sensitivity Non-zero v SB changes threshold voltage, causing substrate sensitivity modeled by V TN = V TO +γ( v SB + 2φ F 2φ ) F where V TO = threshold voltage for v SB = 0 γ = body - effect parameter ( V) 2φ F = surface potential (V) 5/5/11 Chap 4-18

NMOS Model Summary QuickTime and a decompressor are needed to see this picture. 5/5/11 Chap 4-19

PMOS Transistors: Enhancement-Mode Structure p-type source and drain regions in an n-type substrate. v GS < 0 required to create p-type inversion layer in channel region For current flow, v GS < V TP To maintain reverse bias on source-substrate and drainsubstrate junctions, v SB < 0 and v DB < 0 Positive bulk-source potential causes V TP to become more negative 5/8/11 Chap 4-20

PMOS Transistors: Output Characteristics For v GS > V TP, transistor is off. For more negative v GS, drain current increases in magnitude. PMOS device is in the triode region for small values of V DS and in saturation for larger values. Remember V TP < 0 for an enhancement mode transistor 5/8/11 Chap 4-21

PMOS Model Summary QuickTime and a decompressor are needed to see this picture. 5/8/11 Chap 4-22

MOSFET Circuit Symbols (g) and(i) are the most commonly used symbols in VLSI logic design. MOS devices are symmetric. In NMOS, n + region at higher voltage is the drain. In PMOS p + region at lower voltage is the drain 5/8/11 Chap 4-23

Internal Capacitances in Electronic Devices Limit high-frequency performance of the electronic device they are associated with. Limit switching speed of circuits in logic applications Limit frequency at which useful amplification can be obtained in amplifiers. MOSFET capacitances depend on region of operation and are non-linear functions of voltages at device terminals. 5/8/11 Chap 4-24

NMOS Transistor Capacitances: Triode Region C GS = C GC 2 + C W = C " WL GSO ox 2 + C W GSO C GD = C GC 2 + C GDO W = C ox " WL 2 + C GDO W = Gate-channel capacitance per unit area(f/m 2 ). C GC = Total gate channel capacitance. " C ox C GS = Gate-source capacitance. C GD = Gate-drain capacitance. C GSO and C GDO = overlap capacitances (F/m). 5/8/11 Chap 4-25

NMOS Transistor Capacitances: Triode Region (cont.) C SB = C J A S + C JSW P S C DB = C J A D + C JSW P D C SB = Source-bulk capacitance. C DB = Drain-bulk capacitance. A S and A D = Junction bottom area capacitance of the source and drain regions. P S and P D = Perimeter of the source and drain junction regions. 5/8/11 Chap 4-26

NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel C GS = 2 3 C GC + C GSO W C GD = 2 3 C GDOW 5/8/11 Chap 4-27

NMOS Transistor Capacitances: Cutoff Region Conducting channel region completely gone. C GS = C GSO W C GD = C GDO W C GB = C GBO W C GB = gate-bulk capacitance C GBO = gate-bulk capacitance per unit width. 5/8/11 Chap 4-28

SPICE Model for NMOS Transistor Typical default values used by SPICE: KP = 50 or 20 µa/v 2 γ = 0 λ = 0 V TO = 1 V µ n or µ p = 500 or 200 cm 2 /V-s 2Φ F = 0.6 V C GDO = C GSO = C GBO = C JSW = 0 T ox = 100 nm 5/8/11 Chap 4-29

MOS Transistor Scaling Scale Factor α Drain current: Gate Capacitance: K n * = µ n ε ox T ox ε i * D = µ ox W α n T ox α L α * C GC W α α L α = αµ ε ox W n T ox L = αk n ( ) * W * L * = ε ox " = C ox τ * * V * = C GC * i D = τ α v GS α V TN α v DS v DS 2α 2α = i D α where τ is the circuit delay in a logic circuit. T ox W α α L α = C GC α 5/8/11 Chap 4-30

MOS Transistor Scaling Scale Factor α (cont.) Circuit and Power Densities: P * = V * DD i * D = V DD i D α α = P α 2 P * A = P* * W * L = P α 2 * W α ( )( L α) = P A extremely important result! Power-Delay Product: Cutoff Frequency: PDP * = P * τ * = P α 2 τ α = PDP α 3 ω T = g m C GC = µ n L 2 ( V GS V TN ) f T improves with square of channel length reduction 5/8/11 Chap 4-31

MOS Transistor Scaling (cont.) High Field Limitations: High electric fields arise if technology is scaled down with supply voltage constant. Causes reduction in mobility of MOS transistor, breakdown of linear relationship between mobility and electric field and carrier velocity saturation. Ultimately results in reduced long-term reliability and breakdown of gate oxide or pn junction. Drain current in saturation region is linearized to i D = C " oxw 2 ( v GS V TN )v SAT where v SAT is carrier saturation velocity 5/8/11 Chap 4-32

MOS Transistor Scaling (cont.) Sub-threshold Conduction: i D decreases exponentially for v GS < V TN. Reciprocal of the slope in mv/decade gives the turn-off rate for the MOSFET. V TN should be reduced if dimensions are scaled down. However, curve in subthreshold region shifts horizontally instead of scaling with V TN 5/8/11 Chap 4-33

Process-defining Factors Minimum Feature Size F : Width of smallest line or space that can be reliably transferred to the wafer surface using a given generation of lithographic manufacturing tools Alignment Tolerance T: Maximum misalignment that can occur between two mask levels during fabrication 5/8/11 Chap 4-34

Mask Sequence Polysilicon-Gate Transistor Mask 1: Defines active area or thin oxide region of transistor Mask 2: Defines polysilicon gate of transistor, aligns to mask 1 Mask 3: Delineates the contact window, aligns to mask 2. Mask 4: Delineates the metal pattern, aligns to mask 3. Channel region of transistor formed by intersection of first two mask layers. Source and Drain regions formed wherever mask 1 is not covered by mask 2 5/8/11 Chap 4-35

Basic Ground Rules for Layout F = 2 Λ T = F/2 = Λ Λ could be 1, 0.5, 0.25 µm, etc. W/L = 10Λ/2Λ = 5/1 Transistor Area = 120 Λ 2 5/8/11 Chap 4-36

MOSFET Biasing Bias sets the dc operating point around which the device operates. The signal is actually comprised of relatively small changes in the voltages and/or currents. Remember (Total = dc + signal): v GS = V GS + v gs and i D = I D + id 5/8/11 Chap 4-37

Bias Analysis Approach Assume an operation region (generally the saturation region) Use circuit analysis to find V GS Use V GS to calculate I D, and I D to find V DS Check validity of operation region assumptions Change assumptions and analyze again if required. NOTE: An enhancement-mode device with V DS = V GS is always in saturation 5/8/11 Chap 4-38

Four-Resistor and Two-Resistor Biasing Provide excellent bias for transistors in discrete circuits. Stabilize bias point with respect to device parameter and temperature variations using negative feedback. Use single voltage source to supply both gate-bias voltage and drain current. Generally used to bias transistors in saturation region. Two-resistor biasing uses fewer components that fourresistor biasing 5/8/11 Chap 4-39

Bias Analysis - Example 1: Constant Gate-Source Voltage Biasing Problem: Find Q-pt (I D, V DS, V GS ) Approach: Assume operating region, find Q-point, check to see if result is consistent with assumed region of operation Assumption: Transistor is saturated, I G = I B = 0 Analysis: Simplify circuit with Thévenin transformation to find V EQ and R EQ for gate-bias voltage. Find V GS and then use this to find I D. With I D, we can then calculate V DS. 5/8/11 Chap 4-40

Bias Analysis - Example 1: Constant Gate-Source Voltage Biasing (cont.) V DD = I D R D +V DS V DS =10V ( 50µA)100K ( )= 5.00 V Since I G = 0, V EQ = I G R EQ +V GS = V GS I D = K n ( 2 V GS V TN ) 2 I D = 25x10 6 2 A V 2 ( 3 1 ) 2 V 2 = 50.0 µa Check:V DS > V GS -V TN. Hence saturation region assumption is correct. Q-pt: (50.0 µa, 5.00 V) with V GS = 3.00 V Discussion: The Q-point of this circuit is quite sensitive to changes in transistor characteristics, so it is not widely used. 5/9/11 Chap 4-41

Bias Analysis - Example 2: Load Line Analysis Problem: Find Q-pt (I D, V DS, V GS ) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. V DD = I D R D +V DS Assumption: Transistor is saturated, I G = I B = 0 Analysis: For circuit values above, load line becomes 10V = I D ( 100K)+V DS Use this to find two points on the load line. 5/9/11 Chap 4-42

Bias Analysis - Example 2: Load Line Analysis (cont.) V DD = I D R D +V DS 10 =10 5 I D +V DS For V DS = 0, I D = 100 ua For I D = 0, V DS = 10 V Plotting the line on the transistor output characteristic yields Q-pt at intersection with V GS = 3V device curve. Check: The load line approach agrees with previous calculation. Q-pt: (50.0 µa, 5.00 V) with V GS = 3.00 V Discussion: Q-pt is clearly in the saturation region. Graphical load line is good visual aid to see device operating region. 5/9/11 Chap 4-43

Bias Analysis - Example 3: Constant Gate-Source Voltage Biasing with Channel-Length Modulation Problem: Find Q-pt (I D, V DS, V GS ) of previous example, given λ = 0.02 V -1. Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Assumption: Transistor is saturated, I G = I B = 0 Analysis: Simplify circuit with Thévenin transformation to find V EQ and R EQ for gate-bias voltage. Find V GS and then use this to find I D. With I D, we can then calculate V DS. 5/9/11 Chap 4-44

Bias Analysis - Example 3: Constant Gate-Source Voltage Biasing with Channel-Length Modulation (cont.) ( ) 2 ( 1+ λv DS ) I D = K n 2 V GS V TN V DS = V DD I D R D V DS =10 25x10 6 2 V DS = 4.55 V I D = 25x10 6 2 ( 10 5 )3 ( 1) 2 ( 1+ 0.02V DS ) ( 3 1) 2 [ 1+ 0.02( 4.55) ]= 54.5 µa Check: V DS > V GS - V TN. Hence the saturation region assumption is correct. Q-pt: (54.5 µa, 4.55 V) with V GS = 3.00 V Discussion: The bias levels have changed by about 10% (54.5 µa vs 50 µa). Typically, component values will vary more than this, so there is little value in including λ effects in most circuits. 5/9/11 Chap 4-45

Bias Analysis - Example 4: Four-Resistor Biasing Problem: Find Q-pt (I D, V DS ) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Assumption: Transistor is saturated, I G = I B = 0 Analysis: First, simplify circuit, split V DD into two equal-valued sources and apply Thévenin transformation to find V EQ and R EQ for gate-bias voltage 5/9/11 Chap 4-46

Bias Analysis - Example 4: Four-Resistor Biasing (cont.) R V EQ = V 1 1MΩ DD =10V R 1 + R 1 1MΩ +1.5MΩ = 4 V R EQ = R 1 R 1 =1MΩ 1.5MΩ = 600 kω Since I G = 0, V EQ = V GS + I D R S K ( ) 2 R S V EQ = V GS + K n 2 V V GS TN ( 39x10 3 )V ( GS 1) 2 4 = V GS + 25x10 6 2 V GS = 2.71 V or + 2.66 V Since V GS < V TN for V GS = 2.71 V, the MOSFET would be off. V GS = +2.66 V and I D = 34.4 µa V DS = V DD I D R D = 6.08 V V DS > V GS -V TN. Hence the saturation region assumption is correct. Q-pt: (34.4 µa, 6.08 V) with V GS = 2.66 V 5/9/11 Chap 4-47

Bias Analysis - Example 5: Four-Resistor Biasing with Body Effect Analysis with body effect using the same assumptions as in example 1: V TN = V TO +γ( v SB + 2φ F 2φ ) F V TN =1+ 0.5( v SB + 0.6 0.6) I D ' = 25x10 6 2 ( V GS V TN ) 2 Iterative solution can be found using the following steps: Estimate value of I D and use it to find V GS and V SB V GS = V EQ I D R S = 6 22000I D V SB = I D R S = +22000I D Use V SB to calculate V TN Find I D using above 2 steps If I D is not same as original I D estimate, start again. 5/9/11 Chap 4-48

Bias Analysis - Example 5: Four-Resistor Biasing (cont.) The iteration sequence leads to I D = 88.0 µa, V TN = 1.41 V, V DS = V DD I D ( R D + R S )=10 4x10 4 I D = 6.48 V V DS >V GS -V TN. Hence saturation region assumption is correct. DS GS TN Q-pt: (88.0 µa, 6.48 V) Check: V DS > V GS - V TN, therefore still in active region. Discussion: Body effect has decreased current by 12% and increased threshold voltage by 40%. 5/9/11 Chap 4-49

Bias Analysis - Example 6: Two-Resistor Feedback Biasing V GS = V DD K n ( 2 V V GS TN) 2 R D ( 10 4 )V ( GS 1) 2 V GS = 3.3 2.6x10 4 2 V GS = 0.769 V or + 2.00 V Assumption: I G = I B = 0, transistor is saturated (since V DS = V GS ) Analysis: V DS = V DD - I D R D Since V GS < V TN for V GS = -0.769 V, the MOSFET would be cut-off, V GS = +2.00 V and I D =130 µa V DS >V GS -V TN. Hence saturation region assumption is correct. Q-pt: (130 µa, 2.00 V) 5/9/11 Chap 4-50

Bias Analysis - Example 7: Biasing in Triode Region Assumption: Assume saturation Analysis: V GS = V DD = 4 V ( ) 2 = 2.5x10 4 I D = K n 2 V GS V TN I D =1.13 ma 2 ( 4 1) 2 V DS = V DD I D R D V DS = 4 ( 1.13x10 3 )1.6x10 ( 3 )= 2.19 V But V DS <V GS -V TN. Hence, saturation region operation is incorrect. Using triode region equation: I D = K n V GS V TN V DS V 2 DS 4 V DS = ( 1.6x10 3 )2.5x10 ( 4 )4 1 V DS 2 V DS = 2.30 V and I D =1.06 ma V DS >V GS -V TN, transistor is in the triode region Q-pt:(1.06 ma, 2.3 V) V DS 5/9/11 Chap 4-51

Bias Analysis - Example 8: Two-Resistor biasing for PMOS Transistor Assumption: I G = I B = 0; transistor is saturated Analysis: V GS I G R G V DS = 0 V DS = V GS V DD +V DS I D R D = 0 K ( ) 2 R D = 0 V DD +V GS K n 2 V V GS TN 15+V GS ( 2.2x10 5 ) 5x10 5 2 V GS = 0.369 V, 3.45 V ( V GS + 2) 2 = 0 Since V GS = 0.369 > V TP, V GS = 3.45 V I D = 52.5 µa and V DS = 3.45 V V DS > V GS V TP Hence saturation assumption is correct. Q-pt: (52.5 µa, -3.45 V) 5/9/11 Chap 4-52

Junction Field-Effect Transistor Structure The JFET Much lower input current and much higher input impedance than the BJT. In triode region, JFET is a voltage-controlled resistor: R ρ L CH = t W n-type semiconductor block houses the channel region in n- channel JFET. Two pn junctions form the gate. Current enters channel at the drain and exits at source. ρ = resistivity of channel L = channel length W = channel width between pn junction depletion regions t = channel depth Inherently a depletion-mode device 5/9/11 Chap 4-53

JFET with Gate-Source Bias v GS = 0, gate isolated from channel. V P < v GS < 0, W < W, and channel resistance increases; gate-source junction is reverse-biased, i G almost 0. v GS = V P < 0, channel region pinchedoff, channel resistance is infinite. 5/9/11 Chap 4-54

JFET Channel with Drain-Source Bias With constant v GS, depletion region near drain increases with v DS. At v DSP = v GS - V P, channel is totally pinched-off; i D is saturated. JFET also suffers from channellength modulation like MOSFET at larger values of v DS. 5/9/11 Chap 4-55

n-channel JFET i-v Characteristics Transfer Characteristics Output Characteristics 5/9/11 Chap 4-56

n-channel JFET i-v Characteristics (cont.) For all regions : In cutoff region: In Triode region: i G =0 for v GS 0 i D =0 for v GS V P V P <0 i D = 2I DSS v V 2 GS V P v DS P 2 v for v 0 DS GS V P and v GS V P V DS 0 In pinch-off region: i D = I DSS 1 v GS V P 2 1+λv DS for v DS v GS V P 0 5/9/11 Chap 4-57

p-channel JFET Polarities of n- and p-type regions of the n-channel JFET are reversed to get the p-channel JFET. Channel current direction and operating bias voltages are also reversed. 5/9/11 Chap 4-58

JFET Circuit Symbols JFET structures are symmetric like MOSFETs. Source and drain determined by circuit voltages. 5/9/11 Chap 4-59

JFET n-channel Model Summary QuickTime and a decompressor are needed to see this picture. 5/9/11 Chap 4-60

JFET p-channel Model Summary QuickTime and a decompressor are needed to see this picture. 5/9/11 Chap 4-61

JFET Capacitances and SPICE Modeling C GD and C GS are determined by depletionlayer capacitances of reverse-biased pn junctions forming gate and are bias dependent. Typical default values used by SPICE: V p = -2 V λ = C GD = C GD = 0 Transconductance parameter BETA BETA = I DSS /V P 2 = 100 µa/v 2 5/9/11 Chap 4-62

Example: Biasing the JFET & Depletion-Mode MOSFET N-channel JFET Depletion-mode MOSFET Assumptions: JFET is pinched-off, gate-channel junction is reversebiased, reverse leakage current of gate, I G = 0 5/9/11 Chap 4-63

Example: Biasing JFET & Depletion-Mode MOSFET (cont.) Analysis: Since I S = I D, V GS = I D R S V GS = I DSS R S 1 V GS V P 2 V GS = 1.91V, 13.1V = 5 10 3 A ( 1000Ω)1 V GS 5V 2 Since V GS = -13.1 V is less than V P = -5 V, V GS = -1.91 V, and I D = I S = 1.91 ma. Also, V DS =V DD I D (R D +R S )=12 (1.91mA)(3kΩ)= 6.27V V DS >V GS -V P. Hence pinch-off region assumption is correct and gatesource junction is reverse-biased by 1.91V. Q-pt: (1.91 ma, 6.27 V) 5/9/11 Chap 4-64

End of Chapter 4 5/9/11 Chap 4-65