BUS-CONTROLLED AUDIO MATRIX 6 Stereo Inputs 3 Stereo Ouputs Gain Control db/mute for each Output Cascadable ( different addresses) Serial Bus Controlled Very Low Noise Very Low Distorsion Fully ESD Protected Wide Audio Dynamic Range ( 3 V RMS ) SHRINK DIP4 (Shrink Plastic Package) ORDER CODE: TEA64 DESCRIPTION The TEA64 switches 6 stereo audio inputs on 3 stereo outputs. All the switching possibilities are changed through the I C BUS. SO8 (Plastic Monopackage) ORDER CODE: TEA64D Figure. PIN CONNECTIONS SDIP4 SO8 GND 8 GND 4 CAPACITANCE 7 CAPACITANCE 3 V S 3 6 ADDR V S 3 ADDR L 4 5 R L 4 R L 5 4 R L 5 R L3 6 3 R3 L3 6 9 R3 NC 7 NC L4 7 8 R4 NC 8 NC L5 8 7 R5 L4 9 R4 L6 9 6 R6 L5 9 R5 LOUT 5 ROUT3 L6 8 R6 ROUT 4 LOUT3 LOUT 7 ROUT3 LOUT 3 ROUT ROUT 3 6 LOUT3 LOUT 4 5 ROUT September 3 /
BLOCK DIAGRAM RIGHT INPUTS GAIN = db RIGHT OUTPUTS V S C SUPPLY BUS DECODER GND ADDR LEFT OUTPUTS GAIN = db LEFT INPUTS ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V CC Supply Voltage V T oper Operating Temperature, + 7 o C T stg Storage Temperature -, + 5 o C THERMAL DATA Symbol Parameter Value Unit SDIP4 75 o C/W R th (j-a) Junction - ambient Thermal Resistance SO8 75 o C/W /
ELECTRICAL CHARACTERISTICS T A = 5 o C, V S = 9 V, R L = kω, R G = 6 Ω, f = khz (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit SUPPLY V S Supply Voltage 8 V I S Supply Current 3 8 ma SVR Ripple Rejection V IN = 5mV RMS, f = khz 7 8 db MATRIX V IN Input DC Level V CC / V R I Input Resistance 3 5 kω C S Channel Separation V IN = V RMS, f = khz 8 9 db OUTPUT BUFFER V OUT Output DC Level V CC / V R OUT Output Resistance 5 Ω e NI Input Noise BW = - khz, flat 3 µv S/N Signal to Noise Ratio V IN = V OUT = V RMS db G Gain - + db d Distortion V IN = V OUT = V RMS..5 % V CL Clipping Level d =.3 %, V S = V.8 3 V RMS R L Output Load Resistance kω 3/
I C BUS CHARACTERISTICS Symbol Parameter Test Conditions Min. Max. Unit V IL Low Level Input Voltage -.3 +.5 V V IH High Level Input Voltage 3. V CC +.5 V I LI Input Leakage Current V I = to V CC - + µa f Clock Frequency khz t R Input Rise Time.5V to 3V ns t F Input Fall Time 3V to.5v 3 ns C I Input Capacitance pf V IL Low Level Input Voltage -.3 +.5 V V IH High Level Input Voltage 3. V CC +.5 V I LI Input Leakage Current V I = to V CC - + µa C I Input Capacitance pf t R Input Rise Time.5V to 3V ns t F Input Fall Time 3V to.5v 3 ns V OL Low Level Output Voltage I OL = 3mA.4 V t F Output Fall Time 3V to.5v 5 ns C L Load Capacitance 4 pf TIMING t LOW Clock Low Period 4.7 µs t HIGH Clock High Period 4. µs t SU, DAT Data Set-up Time 5 ns t HD, DAT Data Hold Time 34 ns t SU, STO Set-up Time from Clock High to Stop 4. µs t BUF Start Set-up Time following a Stop 4.7 µs t HD, STA Start Hold Time 4. µs t SU, STA Start Set-up Time following Clock Low-to High Transition 4.7 µs Figure. I²C Bus Timing t BUF t LOW t f t HD,STA t t r t t HD,DAT HIGH SU,DAT (start, stop) t SU,STA t SU,STO 4/
POWER ON RESET After power-on reset all outputs are in mute mode Symbol Parameter Conditions Min. Typ. Max. Unit Start of Reset Incr. V CC V.5 Reset Decr. V CC V 4. End of Reset Incr. V CC 4.5 V SOFTWARE SPECIFICATION. Chip address Address HEX ADDR 98 9A. Data bytes Output select X X X I I I Output Output Output 3 Input select X Q Q X X Input Input Input 3 Input 4 Input 5 Input 6 Mute X = don t care - MSB is transmitted first Example : XX connects output 3 with input 5. 5/
Figure 3. Distorsion Level versus Input Voltage dis (%). V S = V.8 f = khz T amb = 5 C.6.4. V IN (V RMS ).4.5.6.7.8.9 3. Figure 5. Clipping Level versus Supply Voltage 3.5 3.3 3..9.7.5 V clipp ( V RMS ) dis =.3% f = khz T amb = 5 C.3 V S (V). 7.5 8 8.5 9 9.5.5 Figure 4. Supply Voltage Rejection versus Frequency ( V IN = 5 mv RMS ) SVR (db) 98 95 V S= V 9 89 86 83 8 77 freq (khz) 74.5.5 5 6/
PIN CONFIGURATIONS (SDIP4 Package) Figure 6. Audio IN Figure 8. Audio OUT V CC V CC Pins 4-5-6-7-8-9 6-7-8-9-- L (R) x in x =,, 3, 4, 5, 6 5kΩ V CC / Matrix Point Pins - - 3-4-5 L (R) x out x =,, 3 Figure 7. ADDR Figure 9. Bus Inputs (, ) V CC V CC 5kΩ to CMOS Pins 3-4 V REF ESD PROT. to CMOS X4 ACKN For only Figure. TYPICAL APPLICATION (SDIP4 Package) µ F 4 3 Bus Inputs +V Left Inputs L C H Output R nf C C C3 C4 C5 C C C3 3 4 5 6 7 8 9 T E A 6 4 9 8 7 6 5 4 C6 C7 C8 C9 C C8 C7 C6 R L SW Right Inputs C H 3 Output C H Output L C4 3 C5 R C H Output 7/
PACKAGE MECHANICAL DATA 4 PINS - PLASTIC SHRINK Figure. 4-Pin Shrink Plastic Dual In Line Package E E mm inches Dim. Min Typ Max Min Typ Max A 5.8. B B e A A L A Stand-off e e A.5. A 3.5 3.3 4.57..3.8 B.36.46.56.4.8. B.76..4.3.4.45 C.3.5.38.9.9 8.5 D c E D.6.86 3..89.9.9 E 7.6 8.64.3.34 E 6. 6.4 6.86.4.5.7 4 3 F SDIP4 e3 e.5,38 Gage Plane e.778.7 e 7.6.3 e.9.43 e3.5.6 Number of Pins N 4 8/
PACKAGE MECHANICAL DATA 8 PINS - PLASTIC MICROPACKAGE Figure. 8-Pin Plastic Small Outline Package, 3-mil Width SO8 Dim. mm inches Min Typ Max Min Typ Max A.35.65.96.43 A..3.4.8 B.33.5.3. C.3.3.9.5 D 7.7 8..6969.75 E 7.4 7.6.94.99 e.7.5 H..64.394.49 h.5.74..9 K 8 L.4.7.6.5 G..4 Number of Pins N 8 9/
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