Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129
Current source Ideal goal Small signal model: Open circuit RD=
Realizing current source: MOSFET Large signal nonideality: Compliance range Looks like current source only for V DS >V eff
MOSFET I D -V DS characteristic for fixed V GS Small-signal nonideality: slope in active region
Cause: Channel length modulation
Channel length modulation
Channel length modulation
Modify small-signal model: Finite r ds current source Slope = I/ V r ds = DV DI SLOPE = DI DV = 1 r ds Ideal: zero slope fi r ds =
Caution: r DS(on) vs. r ds confusion! r DS(on) Triode region Large signal True resistance (V-I through origin) r ds Active region Small signal Models nonideality of current source
Refined MOSFET Small Signal Model Add r ds in parallel with g m v gs current source at output SAME FOR N-ch, P-ch How to relate r ds to DC operating point? Example: g m = 2I D /V eff
I D - V DS Characteristic for Different V GS "Family" of curves
I D - V DS Characteristic for Different V GS Extrapolate backward: intersect at V DS -axis
1/slope provides small signal resistance r ds Intersect at -1/l Slope: 1 r ds = I D 1 l fi r ds = 1 li D
MOSFET small signal model g m = 2I D V eff r ds = 1 li D
Increasing Gain Typical gain (resistive load) Lab 4 example: a v 2 Class example: a v 11.1 How to increase a v?
Definition Transconductance g m g m = di D dv GS
Transconductance g m Definition I D from Square law: g m in terms of W/L, V eff g m = di D dv GS di D dv GS = d dv GS È Í Í Î m n C ox 2 g m = m n C ox W 2 L 2 V eff W 2 L 2 ( ) V GS - V 14 24 tn 3 V eff 2
Summary of g m expressions All equivalent! choose whichever gives easier math Can t memorize? rederive from definition of g m g m = di D dv GS g m = m n C ox W 2 L 2 V eff g m = 2I D V eff g m = 2m n C ox W L I D
Common source circuit (Lab 4) Setting operating point: Adjusted function generator offset for DC output at midpoint of signal swing
Common source circuit (Lab 4) DC operating point Chosen for halfway between rails I D =1.25mA V eff 2.0V (depends on parameters) V OUT = V DD - I D R D V OUT = +2.5V I D = V DD - V OUT R D 5V - 2.5V = 2kW = 1.25mA
Common source circuit (Lab 4) Small signal gain magnitude = 2.5 Not impressive! g m = 2I D = 2(1.25mA) V eff 2.0V g m =1.25mA / V a v = -g m R D = -(1.25mA/ V)(2 kw) a v = -2.5
How to increase a v? Look at gain expression: a v = g m R D
Increase R D New R D = 10kΩ (5X old value) Problem: DC operating point Violates condition for active region: triode! DC operating point stuck at negative rail V OUT = V DD - I D R D V OUT = 5V - (1.25mA)(10kW) 1442 443 V OUT = -7.5V? 12.5V
Look at problem symbolically Use g m =2I D /V eff I D R D = DC drop on load Optimal bias at output: constrained to V DD / 2 g m = 2I D V eff a v = g m R D = 2I DR D V eff I D R D = V DD 2 I D, R D not involved! a v = V DD V eff Value of approximate symbolic approach vs. exact numerical results from simulation
How to increase gain (resistive load) increase V DD usually fixed by application, process decrease Veff a v = V DD V eff does increase g m but...
Problems decreasing V eff V eff, W/L g m expression: 2X increase in g m : 4X increase in size (can t increase I D R D ) Increased area: cost penalty Increased capacitance speed penalty g m = V eff < 200 mv: subthreshold region 2m n C ox W L I D Not square law: g m expressions invalid
Increase a v : Different approach Give up on resistive load... What is highest resistance?
Increasing a v : Different approach What is highest resistance? Infinite: open circuit Problem: no path for I D Any circuit element that: provides DC current, but is open circuit in small signal model?
Open in small signal model Realizing current source: MOSFET Current source!
Lab Circuit: MOSFET with active load Small signal model for M1 Thevenin equivalent looking into drain of M2 (see text sec. 3.1)
Small signal model M1 common source M2 Thevenin equivalent
Simplify small signal model Combine r ds1, r ds2 in parallel
Small signal gain v out v in = a v = -g m1 ( r ds1 r ds2 )
Current source load: Large signal considerations Output swing limits Top: M2 crash into triode Bottom: M1 crash into triode
Common Source with Active Load DC Sweep Schematic
Active Load Simulation Result (DC Sweep)
Determining DC Operating Point Set small signal v in = 0
Determining DC Operating Point Active region: V eff determines I D Correct V IN : M1, M2 agree Example: V eff1 = 1.0V I D = 100 µa
If DC bias at input is wrong? Current source "disagreement" KCL crisis at output: 2µA, nowhere to go What happens?
If DC bias at input is wrong? Capacitance at output node V out 2µA flows into cap, charges up fi V DS1 increases fi I 1 increases fi V DS2 decreases fi I 1 decreases Changes in V DS cause changes in I D until agreement is reached: I D1 = I D2
How much change in V DS? Changes in V DS cause changes in I D until agreement is reached: I D1 = I D2 BUT Active region: I D is a weak function of V DS Large change in V DS for small change in I D Output very sensitive to changes in I D : Small V eff at input fi Small I D fi Requires large V DS at output for I D agreement Good: high voltage gain Bad: tricky to get correct input bias point
Frequency Domain Considerations Ideal op-amp goals: Infinite gain Infinite bandwidth Active load helps gain What about bandwidth?
Start simple: Assume single C L at output (Ignore MOS capacitances for now ) Find transfer function v out /v in Frequency Domain Analysis
Small signal model Combine r ds1 r ds2 = r out
Simpler small signal model Combine r out C L into impedance Z L
Simplified Small Signal Model Small signal gain: v out /v in = a v = -g m Z L Frequency dependence of Z L provides frequency dependence of transfer function
Closer Look at Z L : Impedance is parallel combination of r out, 1/sC L Z L = r out 1 sc L = 1 1 + sc L r out r out Z L = 1 + sr out C L
Let s=jw Behavior of Z L over frequency: Z L = r out 1 + jwr out C L Low frequency limit:mostly r out w << 1 r out C L fi Z L = r out 1 + jwr out C L ª r out High frequency limit: mostly C L w >> 1 r out C L fi Z L = r out 1 + jwr out C L ª r out jwr out C L ª 1 jwc L
Substitute in Z L v out v in = -g m Z L = Transfer function -g m r out 1 + jwr out C L Magnitude v out v in = g m r out 1 + ( wr out C L ) 2
Bode Plot of Transfer Function Magnitude v out v in = g m r out 1 + ( wr out C L ) 2 Magnitude vs. Frequency (log-log plot) Bandwidth: w 3dB
3-dB Frequency / Bandwidth Frequency at which magnitude is 3 db down (reduced by factor 1/ 2) MAX v out v in = g m r out AT w = 0 THEN AT w 3dB, v out v in 1 = 1 2 g m r out 2 g m r out = g m r out 1+ ( w 3dB r out C L ) 2 fi w 3dB = 1 r out C L
Revisit Bode Plot: Gain, Bandwidth inversely related!
Unity Gain Frequency w T / Gain-Bandwidth Product w T : Frequency at which magnitude is 1 Use approximation w T >> 1/r out C L 1 = g m r out ( ) ª g m r out 2 ( ) fi w = g m 2 T C L 1+ w T r out C L w T r out C L Gain x Bandwidth Product a v = g m r out w 3dB = 1 fi g m r out r out C L 12 3 1 r GAIN out C 12 3 L BANDWIDTH = g m C L Independent of r out! Poorly controlled r out OK
Summary: Active Load Active load DC considerations: Output swing limited by triode crash To voltage within V eff of rail Active load good news / bad news: Good news: high gain Bad news: very sensitive to input DC bias
Massage small signal gain result Small signal gain Look at parallel combination Substitute expression for r ds a v = g m1 ( r ds1 r ds2 ) 1 r ds1 r ds2 = 1 + 1 r ds1 r ds2 1 r ds1 r ds2 = l 1 I D + l 2 I D 1 r ds1 r ds2 = ( l 1 + l 2 )I D
Massage small signal gain result Small signal gain Substitute for g m, parallel r ds I D drops out! a v = g m1 ( r ds1 r ds2 ) a v = 2I D 1 V { eff1 ( l 1 + l 2 )I 1 42 4 3 D a v = g m1 2 r ds1 r ds2 ( l 1 + l 2 )V eff1 Only l, V eff to work with
Improve Gain Reduce V eff Minimum 200 to 300mV (subthreshold) May not want to go that low (W,L too big) Reduce l 1, l 2 How? Where does l 1 come from?
Square law model with channel length mod I D = m nc ox W ( 2 L V GS - V tn ) 2 144 42 444 3 1 + l V DS - V eff I D -sat [ ( )] I D-sat term (at pinchoff) + "extra"
Square law model with channel length modulation I D = m nc ox W ( 2 L V GS - V tn ) 2 144 42 444 3 1 + l V DS - V eff I D -sat [ ( )] Fractional extra part is l(v DS -V eff ) Meaning of l: Fractional change in current I D per volt change in V DS
What causes change? Where does l come from? Change in effective channel length L One way to reduce l: longer L Change L represents smaller fraction
After some semiconductor physics... Definition of l Fractional change Semiconductor physics... (see J&M p. 26) l = DI D I D DV DS DI D I D l = 1 L = DL L DL DV DS DL DV DS = 2K S e 0 qn SUB 1 2 V DS - V eff l = 1 L 2K S e 0 1 qn SUB 2 V DS - V eff K S Silicon dielectric constant 11.8 N SUB Substrate doping units /cm 3 Sanity check: 1E+14 to 1E+17 V DS from active-triode edge to large V DS Caution: consistent length units on L, N SUB, e 0
Substrate doping NSUB parameter Needed for SPICE Extraction procedure: 1) Calculate slope from I D -V DS plot 2) r ds = 1/ slope (small signal model) 3) Calculate l 4) Calculate NSUB
Example V DS -I D data from Lab 5 for P-channel MOSFET:
1) Calculate slope from I D -V DS plot 2) r ds = 1/slope (small signal model)
3) Calculate l I D = 482 µa l = 1 I D r ds = 1 ( 482mA) 40.2kW ( ) = 1 19.4V = 0.052V -1
4) calculate NSUB l = 1 L 0.052V -1 = 2K S e 0 1 qn SUB 2 V DS -V eff 1 1E - 5m ( ) ( )( 8.85E -12F /m) N SUB = 3.32E + 22 m -3 = 3.32E +16 cm -3 V DS = 4.48 V 2 11.8 1 ( 1.6E -19coul)N SUB 2 4.48V - 0.84V For CD4007, L = 10µm = 1.0E-5m V DS, V eff for largest V DS data point
Simulation exercise Add NSUB to N-channel, P-channel models DC sweep for CS Amplifier with Active Load
Common Source with Active Load (DC) Sweep input over full range 0 to +5V
DC Sweep Around Operating Point