Semiconductor Devices and Nanoelectronics Qiliang Li Dept. of Electrical and Computer Engineering George Mason University, Fairfax, VA qli6@gmu.edu Email: qli6@gmu.edu 1
Content Outline Semiconductor materials and the carriers in semiconductors; Semiconductor fabrication and devices physics for pn junction, metal-semiconductor junction and MOS structure; MOSFET, its basic circuits (inverter, NAND and NOR logic) and memory devices (Flash, SRAM, DRAM and other NVM) Concepts in Nanoelectronics Email: qli6@gmu.edu 2
What is semiconductors? Their electrical conductivity is between that of metals (e.g., Al, Au, ) and insulators (e.g., SiO 2, Al 2 O 3 and HfO 2 ); Semiconductors are the foundation of modern electronic circuits Important concepts: pn junction, transistor (BJT and MOSFET), solar cell, Light-emitting diode, digital and analog integrated circuits Email: qli6@gmu.edu 3
The Common Semiconductors Conventional semiconductors: Silicon (Si), germanium (Ge), GaAs, GaN, SiC One dimensional semiconductor: nanowires and nanotubes Two-dimensional semiconductors, e.g., MoS 2 we are always looking for new functional semiconductor materials Email: qli6@gmu.edu 4
Chapter 1. Electrons and Holes in 1.1 Si Crystal Structure Semiconductors Unit cell of Si is cubic Each Si atom has 4 nearest neighbors 5.3 A Email: qli6@gmu.edu 5
1.2 Bond Model of electrons and holes Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Intrinsic Si Doped Si As: group V B: group III E ION = 50 mv Very low Si Si Si Si Si Si Si As Si Si B Si Si Si Si Si Si Si Email: qli6@gmu.edu 6
1.3 Energy Band Model } Empty upper bands 2p 3P 2s 3S ( conduction band) (valence band) } Filled lower bands (a) (b) The highest filled band is the valence band The lowest empty band is the conduction band Email: qli6@gmu.edu 7
1.3 Energy Band Model Conduction band E c Band gap E g E v Valence band Energy band diagram shows the bottom edge of conduction band, E c, and top edge of valence band, E v. E c and E v are separated by the band gap energy, E g. Email: qli6@gmu.edu 8
Si band structure Indirect band gap 6 minimum at <100> 1.4 Energy Band structure Email: qli6@gmu.edu 9
Ge band structure Indirect band gap 8 minimum at <111> 1.4 Energy Band structure Email: qli6@gmu.edu 10
GaAs band structure Direct band gap 1.4 Energy Band structure Email: qli6@gmu.edu 11
1.5 Calculate the band structure Common methods: Slater-Koster tight-binding method Semi Empirical extended Huckel method (using Huckel molecular orbital theory) Density functional theory (DFT) Local- Density Approximation (LDA) method Density functional theory (DFT) Generalized Gradient Approximations (GGA) method Email: qli6@gmu.edu 12
1.5 Calculate the band structure Use MoS2 monolayer as example: Email: qli6@gmu.edu 13
1.5 Calculate the band structure MoS2 band structure calculated by using DFT-GGA method Direct band gap Eg = 1.79 ev Effective mass: m l = 0.59 m0 m t = 0.50 m0 m dos = (6) 2/3 (m l m t m t ) 1/3 = 1.75 m 0 We used Virtual Nanolab ATK software to calculate it. Welcome collaboration on the research! Email: qli6@gmu.edu 14
Chapter 2. Device Fabrication and Physics 2.1 Device Fabrication Technology Email: qli6@gmu.edu 15
2.1 Device Fabrication Technology VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale Integration) GSI (Giga-Scale Integration) Variations of this versatile technology are used for flat-panel displays, micro-electromechanical systems (MEMS), and chips for DNA screening... Email: qli6@gmu.edu 16
2.1 Device Fabrication Technology Arsenic implantation (0) Wafer P-Si (4) SiO 2 SiO 2 P-Si Ion Implantation (1) Oxidation (2) Lithography SiO 2 P-Si SiO 2 UV UV Mask Positive resist SiO 2 P-Si (5) (6) SiO 2 SiO2 N + P Al SiO 2 SiO 2 N + P UV UV Mask Annealing & Diffusion Al Sputtering (3) Etching SiO 2 SiO 2 P-Si (7) Resist Al Al SiO 2 SiO 2 N + P * An example from Modern Semiconductor Devices for Integrated Circuits (C. Hu) Lithography Email: qli6@gmu.edu 17
2.1 Device Fabrication Technology Metal etching (8) (9) CVD nitride deposition (10) Lithography and etching (11) Back Side milling SiO2 SiO2 Si 3 N 4 N + P SiO 2 SiO 2 Si 3 N 4 N + P SiO 2 SiO 2 N + P Photoresist Si 3 N 4 SiO 2 SiO 2 N + P Al Al Al Al (12) (13) SiO 2 SiO 2 Si 3 N 4 N + P SiO 2 SiO 2 Au Si 3 N 4 Au N + P Al Plastic package metal leads Al Back side metallization wire Dicing, wire bonding, and packaging * An example from Modern Semiconductor Devices for Integrated Circuits (C. Hu) Email: qli6@gmu.edu 18
2.2 pn Junction Electric Field Neutral Region N Depletion Layer Neutral Region P On the P-side of the depletion layer, ρ = qn a x 0 n N x p ρ P d E dx qn = a ε s x n N qn d qn a x p P x qna qna E( x) = x + C = 1 ( x P x) ε ε s s E x x n 0 pp N x On the N-side, ρ = qn d qnd E( x) = ( x - xn) ε s Email: qli6@gmu.edu 19
Electric Field and potential φ bi E x x n 0 p N V 2.2 pn Junction P x On the P-side, qna V ( x) = ( xp x) 2 ε s Arbitrarily choose the voltage at x = x P as V = 0. 2 φ bi, built-in potential x x n pp N E c x E f E v On the N-side, qnd V ( x) = D ( x xn 2ε s qnd = φbi ( x x 2ε s N 2 ) 2 ) Email: qli6@gmu.edu 20
2.2 pn Junction Depletion layer width Neutral Region Depletion Layer Neutral Region N P V is continuous at x = 0 x 0 n x N p If N a >> N d, as in a P + N junction, x P x N = W dep P = 2ε sφbi q 1 N a + 1 N d W dep = 2ε sφbi qn d x N x = x N P N d N a 0 What about a N + P junction? W dep = 2ε s φ bi qn where 1 N = 1 N d + 1 N a lighter 1 dopant density Email: qli6@gmu.edu 21
2.2 pn Junction V + Reverse-Biased N P E c W dep = 2ε s ( φbi + Vr ) 2ε s = qn potential qn barrier E c E fn qφ bi + qv qv E fp E v Reverse biased PN junction is a capacitor. C dep = εs A W dep E v (b) reverse-biased 1/C dep 2 Capacitance data C 1 2 dep = W A 2 dep 2 2 ε s = 2( φbi + V ) 2 qnε A S Slope = 2/qNε s A 2 How to minimize the junction capacitance? φ bi Increasing reverse bias V r Email: qli6@gmu.edu 22
Peak electric field and breakdown voltage: Tunneling Breaking 2.2 pn Junction - breakdown E p 2qN E( 0) = ( φ + bi V ) ε s = r 1/ 2 V B ε 2 s crit = E 2 qn φ Impack ionization avalanche breakdown E c E fp E v original electron bi Filled States - Empty States E c electron-hole pair generation J = G e H / ε p E v E c E fn = crit E p E 10 6 V/cm Basis for tunneling FET for smaller subthreshold swing 1 1 V B = + N N Email: qli6@gmu.edu 23 a 1 N d
Email: qli6@gmu.edu 24 2.2 pn Junction forward bias Minority carrier injection 1) ( ) ( ) ( 0 0 = kt qv P P P P e n n x n x n 1) ( ) ( ) ( 0 0 = kt qv N N N N e p p x p x p ( ) P L x x kt qv P x x e e n x n n P < =, 1) ( ) ( / / 0 ( ) N L x x kt qv N x x e e p x p p N > =, 1) ( ) ( / / 0 L: diffusion length ~ 10 um, depending on N x J e n L D q p L D q x J x J kt qv P n n N p p P np N pn at all 1) ( ) ( ) ( current Total 0 0 = + = + =
2.2 pn Junction Solar Cell I sc P + 0 x N * Modern Semiconductor Devices for Integrated Circuits (C. Hu) I V oc = AJ p (0) AqL kt = ln( τ pgn q sc = Email: qli6@gmu.edu 25 p d G / n 2 i )
2.2 pn Junction LED Direct band gap Example: GaAs Direct recombination is efficient as k conservation is satisfied. Indirect band gap Example: Si Direct recombination is rare as k conservation is not satisfied LED wavelength ( µ m) = 1.24 photon energy 1.24 ( ev ) E g Email: qli6@gmu.edu 26
2.3 Metal-Semiconductor Junction Two kinds of metal-semiconductor contacts: Rectifying Schottky diodes: metal on lightly I doped silicon Reverse bias Low-resistance ohmic contacts: metal on heavily doped silicon V Forward bias Email: qli6@gmu.edu 27
2.3 Metal-Semiconductor Junction Schottky Barrier Metal qφ Bn Depletion layer Neutral region N-Si E c E f Schottky barrier height, φ B, is a function of the metal material. P-Si E v E c E f φ B is the most important parameter. The sum of qφ Bn and qφ Bp is equal to E g. qφ Bp E v Email: qli6@gmu.edu 28
2.3 Metal-Semiconductor Junction qψ M qφ Bn χ Si = 4.05 ev + Vacuum level, E 0 Ec E f E v A high density of energy states in the bandgap at the metal-semiconductor interface pins E f to a narrow range and φ Bn is typically 0.4 to 0.9 V. φ Bn + φ Bp E g Silicide-Si contact: Silicide ErSi 1.7 HfSi MoSi 2 ZrSi 2 TiSi 2 CoSi 2 WSi 2 NiSi 2 Pd 2 Si PtSi φ Bn φ Bn (V) 0.28 0.45 0.55 0.55 0.61 0.65 0.67 0.67 0.75 0.87 φ Bp φ Bp (V) 0.55 0.49 0.45 0.45 0.43 0.43 0.35 0.23 * Modern Semiconductor Devices for Integrated Circuits (C. Hu) Email: qli6@gmu.edu 29
2.4 Metal-Oxide-Semiconductor Capacitor V g metal gate V g gate SiO 2 N + SiO 2 N + Si body P-body MOS capacitor MOS transistor Email: qli6@gmu.edu 30
2.4 MOS flat-band condition χ SiO2 =0.95 ev 0 E c qψ g 3.1 ev 3.1 ev χ Si q ψ s = χ Si + (E c E f ) =4.05eV E c, E f q V fb E c E v N + -poly-si E 0 : Vacuum level E 0 E f : Work function E 0 E c : Electron affinity Si/SiO 2 energy barrier 9 ev E v SiO 2 4.8 ev P-body V E f E v The band is flat at the flat band voltage. fb =ψ ψ g s Email: qli6@gmu.edu 31
2.4 MOS surface accumulation E c, E f 3.1eV E v E 0 qv g V ox qφ s M O S E c E f E v Make V g < V fb V = V + φ + V g φ fb s ox φ s : surface potential, band bending V ox : voltage across the oxide s is negligible when the surface is in accumulation. Email: qli6@gmu.edu 32
2.4 MOS surface accumulation V g <V t Gauss s Law V ox = V g V V = Q / ox acc fb C ox Q acc = C ox ( V V ) fb g V = Q / ox s C ox Many reported nanowire / nanotube FET is actually operated in accumulation mode Email: qli6@gmu.edu 33
2.4 MOS surface depletion (V g > V fb ) qv ox E c V gate + + + + + + - - - - - - - - depletion layer charge, Q dep SiO 2 E c, E f E v qv g qφ s - - - - W dep depletion region E fev P-Si body V ox Q = C s ox Q = C dep ox = qn a C W ox dep = qn a C M O S 2ε φ a s s Vg = V fb + φs + Vox = V fb + φs + φ s C * Modern Semiconductor Devices for Integrated Circuits (C. Hu) ox ox qn s s 2ε φ Email: qli6@gmu.edu 34
2.4 MOS surface inversion Threshold of inversion: n s = N a, or (E c E f ) surface = (E f E v ) bulk, or A=B, and C = D E c, E f φ st A D qv = g qv t C =qφ Β B E c E i E f E v φ st = 2φ B = kt 2 ln q N n i a E v M O S qφ B = E 2 g ( E f E v ) bulk = kt q ln N n i v kt q ln N N v a = kt q ln N n i a At threshold: V t = V at threshold = V + 2 φ + qn 2ε 2φ a s B g fb B Cox Email: qli6@gmu.edu 35
2.4 MOS Threshold Voltage V t (V), N + gate/p-body T ox = 20nm V t (V), P + gate/n-body Body Doping Density (cm -3 ) V t = V fb ± 2 φ ± B qn sub C 2ε 2φ * Modern Semiconductor Devices for Integrated Circuits (C. Hu) ox s B + for P-body, for N-body Email: qli6@gmu.edu 36
2.4 MOS Capacitance vs. Voltage C = dq dv g g = dq dv s g Q s accumulation regime depletion regime inversion regime C ox C V fb 0 V t V g Q inv slope = C ox V fb accumulation depletion inversion V t V g Email: qli6@gmu.edu 37
2.4 MOS Capacitance vs. Voltage C ox C In the depletion regime: V fb accumulation depletion inversion V t 1 1 1 = + C C ox C dep V g 1 C = 1 C 2 ox + 2( V g qn V a ε s fb ) Email: qli6@gmu.edu 38
Capacitor and Transistor CV (or HF and LF CV) 电子有足够时间 response Email: qli6@gmu.edu 39
2.4 MOS: C-V Curve Fitting CVC is a open source software (by NCSU) for CV fitting /* Lines with '/*' as first entry are ignored */ eoxr = 3.9 /* Relative dielectric constant for insulator */ 你用的材料的介电参数, 如果不是氧化硅的要改 esr = 11.8 /* Relative dielectric constant for semiconductor */ 衬底材料的介电参数, 如果不是硅的要改 ni = 1.44e10 /* Intrinsic carrier density */ 这是硅的 intrinsic carrier density, 如果不是硅的要改 nc = 2.80e19 /* Conduction band density of states */ 这是硅的导带 carrier density, 如果不是硅的要改 nv = 1.04e19 /* Valence band density of states */ 这是硅的价带 carrier density, 如果不是硅的要改 ego = 1.17 /* Extrapolated T=0 semiconductor band gap */ 这是硅的禁带宽度 ( 温度为 0 时的带宽 ) alf1 = 4.73e-4 /* Temperature corfficient of band gap -- form eg = ego - alf1*t^2/(t + to1) */ 这是温度对能带 Eg 的影响, 材料不同而有所不同, 不过, 这是微调, 在很多情况下, 不太重要 to1 = 636. /* Coefficient for temperature dependancy of band gap */ 同上, 你可以看到, 硅和 GaAs 就有些不同 Email: qli6@gmu.edu 40
Chapter 3. Introduction of MOSFET and its applications The MOSFET (MOS Field-Effect Transistor) is the building block of Gb memory chips, GHz microprocessors, analog, and RF circuits. Match the following MOSFET characteristics with their applications: small size high speed low power high gain Email: qli6@gmu.edu 41
3.1 Introduction to the MOSFET Basic MOSFET structure and IV characteristics + + Email: qli6@gmu.edu 42
3.2 Complementary MOSFETs Technology nfet pfet When V g = V dd, the NFET is on and the PFET is off. When V g = 0, the PFET is on and the NFET is off. * Modern Semiconductor Devices for Integrated Circuits (C. Hu) Email: qli6@gmu.edu 43
Static Complementary CMOS V DD In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only F(In1,In2, InN) PUN and PDN are dual logic networks Email: qli6@gmu.edu 44
3.3 CMOS (Complementary MOS) Inverter V in PFET NFET V dd S D D S 0V 0V A CMOS inverter is made of a PFET pull-up device and a NFET pull-down device. V out =? if V in = 0 V. C: V out capacitance (of interconnect, etc.) Email: qli6@gmu.edu 45
CMOS Inverter--voltage transfer curve V o ut (V) V dd 2.0 1.5 1.0 0.5 V dd 0 0.5 1.0 1.5 2.0 V in (V) Email: qli6@gmu.edu 46
Inverter Speed propagation delay V dd... V 1 V 2 V 3 C C... To measure the speed 1 τ d ( pull down delay 2 pull up delay) + V dd 0 V 2 V 1 2τ d V 3 pull up delay pull down delay t CV 2I dd onp CV 2I dd onn τ d : propagation delay Email: qli6@gmu.edu 47
3.3 CMOS NOR Gate Try not to stack PMOS? Email: qli6@gmu.edu 48
3.3 CMOS NAND Gate Email: qli6@gmu.edu 49
3.3 CMOS NAND Gate - Timing Voltage [V] 3 2.5 2 1.5 1 0.5 0-0.5 A=B=1 0 A=1 0, B=1 A=1, B=1 0 0 100 200 300 400 time [ps] Input Data Pattern Delay (psec) A=B=0 1 69 A=1, B=0 1 62 A= 0 1, B=1 50 A=B=1 0 35 A=1, B=1 0 76 A= 1 0, B=1 57 NMOS = 0.5µm/0.25 µm PMOS = 0.75µm/0.25 µm C L = 100 ff Email: qli6@gmu.edu 50
3.4 Master-Slave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 Q D I 1 T 1 Q M I 4 T 3 CLK Email: qli6@gmu.edu 51
3.5 SRAM >Fastest among all memories. >Totally CMOS compatible. >Cost per bit is the highest-- uses 6 transistors to store one bit of data. M 5 WL V dd M 3 M 4 M 6 BL HI (LOW) LOW (HI) BLC M 1 M 2 Email: qli6@gmu.edu 52
3.6 DRAM Bit-line 1 Bit-line 2 Word-line 1 Word-line 2 DRAM capacitor can only hold the data (charge) for a limited time because of leakage current. Needs refresh. Needs ~10fF C in a small and shrinking area -- for refresh time and error rate. Email: qli6@gmu.edu 53
Flash or SONOS memory 3.7 Nonvolatile Memory Phase change memory Resistive memory (RRAM) Molecular memory The current challenge (opportunity) is to find excellent electrically accessible NVM for CPU. Email: qli6@gmu.edu 54
3.8 Concepts in MOSFET Subthreshold Current The leakage current that flows at V g <V t is called the subthreshold current. I ds (µ A/µm) V t V t Intel, T. Ghani et al., IEDM 2003 90nm technology. Gate length: 45nm V gs The current at V gs =0 and V ds =V dd is called I off. Email: qli6@gmu.edu 55
Subthreshold Leakage Current I ds ( constant V ) / kt n e qϕ kt q s / e + gs /η e qv gs /ηkt s C ox V G I ds e qv gs /ηkt C dep ϕ s η = 1 + C dep C oxe Subthreshold current changes 10x for η 60mV change in V g. Reminder: 60mV is (ln10) kt/q Subthreshold swing, S : the change in V gs corresponding to 10x change in subthreshold current. S = η 60mV, typically 80-100mV / dec Email: qli6@gmu.edu 56
Subthreshold Leakage Current Practical definition of V t : the V gs at which I ds = 100nA W/L W / => W q ( V g V t) / ηkt ( V ) I subthreshold ( na ) 100 g V t S e = 100 10 L L Log (I ds ) 100 W/L(nA) I off 1/S V ds =V dd I off (na) = 100 W L 10 V t / S is determined only by V t and subthreshold swing. V t V gs Email: qli6@gmu.edu 57
Subthreshold Swing Smaller S is desirable (lower I off for a given V t ). Minimum possible value of S is 60mV/dec. How do we reduce swing? Thinner T ox => larger C oxe Lower substrate doping => smaller C dep Lower temperature Limitations Thinner T ox oxide breakdown reliability or oxide leakage current Lower substrate doping doping is not a free parameter but set by V t. Effect of Interface States S = 60mV C S 60mV 1 + C = oxe Cdep + dq 1+ C oxe dep Email: qli6@gmu.edu 58 int / dφs
3.9 Major Challenges in MOSFET Threshold Voltage (V t ) Roll-off V t roll-off: V t decreases with decreasing L g. It determines the minimum acceptable L g because I off is too large if V t becomes too small. * K. Goto et al., (Fujitsu) IEDM 2003 Vt Roll-off (V) 0.00-0.05-0.10-0.15-0.20 Question: Why data is plotted against L g, not L? Sym bols: TCAD Lines: M odel Vds = 50mV Vds = 1.0V -0.25 0.01 0.1 1 Lg (um ) 65nm technology. EOT=1.2nm, V dd =1V Answer: L is difficult to measure. L g is. Also, L g is the quantity that manufacturing engineers can control directly. Email: qli6@gmu.edu 59
Energy-Band Diagram from Source to Drain L dependence source/channel barrier long channel V ds dependence V ds =0 long channel V ds =0 short channel V ds short channel V ds =V dd V ds =V dd log(i ds ) DIBL: Drain Induced Barrier Lowering V ds V gs GIDL: gate induced drain leakage Email: qli6@gmu.edu 60
V t Roll-off Simple Capacitance Model T ox n+ X j W dep V gs C oxe V ds P-Sub C d V ds helps V gs to invert the surface, therefore V t V t = Vt long t long V ds C C d oxe ( V + 0. ) = V 4 ds C C oxe Due to built-in potential between N - channel and N + drain & source d As the channel length is reduced, drain to channel distance is reduced C d increases 2-D Poisson Eq. solution shows that C d is an exponential function of L. V t = V where t long l d 3 ( V + 0.4) That is why we need to shrink T ox, body thickness, junction depth! We need 2D materials like graphene and MoS 2 T dep L / l Email: qli6@gmu.edu 61 ds ox W X e j d
Chapter 4. Concepts in Nanoelectronic Materials and Devices International Technology Roadmap for Semiconductors Year of Shipment 2003 2005 2007 2010 2013 Technology Node (nm) 90 65 45 32 22 Lg (nm) (HP/LSTP) 37/65 26/45 22/37 16/25 13/20 EOT e (nm) (HP/LSTP) 1.9/2.8 1.8/2.5 1.2/1.9 0.9/1.6 0.9/1.4 VDD (HP/LSTP) 1.2/1.2 1.1/1.1 1.0/1.1 1.0/1.0 0.9/0.9 Ion,HP (µa/µm) 1100 1210 1500 1820 2200 Ioff,HP (µa/µm) 0.15 0.34 0.61 0.84 0.37 Ion,LSTP (µa/µm) 440 465 540 540 540 Ioff,LSTP (µa/µm) 1e-5 1e-5 3e-5 3e-5 2e-5 Strained Silicon High-k/Metal-Gate Wet Lithography New Structure V dd is reduced at each node to contain power consumption T ox is reduced to raise I on and retain good transistor behaviors HP: High performance; LSTP: Low stand-by power Email: qli6@gmu.edu 62
4.1 Strained Silicon: example of innovations Mechanical strain Gate Trenches filled with epitaxial SiGe S D N-type Si The electron and hole mobility can be raised by carefully designed mechanical strain. Strained Si technology has been used in microprocessor. Email: qli6@gmu.edu 63
4.2 MOSFET with Metal Source/Drain To unleash the potentials of Schottky S/D MOSFET, a low- Schottky φ Bn junction is needed for NFETs and low- for PFET. φ Bp Email: qli6@gmu.edu 64
4.3 Single-Electron Transistor Adding gate control on a Coulomb-Blockade structure single-electron tunneling transistor or simply single-electron transistor (SET) Vg > 0 will depress the Fermi level, Ef Vg < 0 will raise Ef Above, below and lie up with Ef of right/left side Email: qli6@gmu.edu 65
* Fundamentals of Nanoelectronics (G. Hanson) Email: qli6@gmu.edu 66
The net charge on the island: * Fundamentals of Nanoelectronics (G. Hanson) Email: qli6@gmu.edu 67
Solved: Email: qli6@gmu.edu 68
An electron tunnel into the island from b, the change of stored energy is Email: qli6@gmu.edu 69
Similarly for an electron from island to Junction a: Email: qli6@gmu.edu 70
Assume initially island is charge neutral (n=0), an electron tunnels into the island through junction b I > 0 * Fundamentals of Nanoelectronics (G. Hanson) Email: qli6@gmu.edu 71
Now the island is has one electron (n=1), the electron tunnels off from the island into junction a: I > 0 * Fundamentals of Nanoelectronics (G. Hanson) Email: qli6@gmu.edu 72
To observe a current from junction b to a, both condition need to be met: Current > 0 * Fundamentals of Nanoelectronics (G. Hanson) Email: qli6@gmu.edu 73
Coulomb diamonds Charge stability diagram Shaded regions: no tunneling is allowed * Fundamentals of Nanoelectronics (G. Hanson) Email: qli6@gmu.edu 74
Other SET and FET structures Carbon nanotube FET Email: qli6@gmu.edu 75
Other concepts in nanoelectronics Tunneling theory: with a focus on resonant tunneling Coulomb blockade (basis for SET) Ballistic transport Spin transport and spintronics Topological insulator 2D materials: graphene and MoS 2 Email: qli6@gmu.edu 76