The MC10107 is a triple input exclusive OR/NOR gate. P D = 0 mw typ/gate (No Load) t pd =. ns typ t r, t f =. ns typ (0% 0%) LOGIC DIAGRAM MARKING DIAGRAMS CDIP 16 L SUFFIX CASE 60 16 1 MC10107L AWLYYWW DIP PIN ASSIGNMENT PDIP 16 P SUFFIX CASE 6 PLCC 0 FN SUFFIX CASE 77 16 1 MC10107P AWLYYWW 1 10107 AWLYYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week ORDERING INFORMATION Device Package Shipping MC10107L CDIP 16 Units / Rail MC10107P PDIP 16 Units / Rail *NC = No Connection MC10107FN PLCC 0 6 Units / Rail Pin assignment is for Dual in Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 1 of the ON Semiconductor MECL Data Book (DL1/D). Semiconductor Components Industries, LLC, 00 January, 00 Rev. 7 1 Publication Order Number: MC10107/D
ELECTRICAL CHARACTERISTICS Characteristic Symbol Test Limits Pin Under 0 C + C + C Test Min Max Min Typ Max Min Max Unit Power Supply Drain Current I E 1 1 madc Input Current I inh, 9, 1 Output Voltage Logic 1 V OH Output Voltage Logic 0 V OL Threshold Voltage Logic 1 V OHA Threshold Voltage Logic 0 V OLA 0 6 0 6 0 µadc I inl * 0. 0. 0. µadc 1.060 1.060 1.060 1.060 1.90 1.90 1.90 1.90 1.00 1.00 1.00 1.00 0.90 0.90 0.90 0.90 1.67 1.67 1.67 1.67 1.6 1.6 1.6 1.6 0.960 0.960 0.960 0.960 1.0 1.0 1.0 1.0 0.90 0.90 0.90 0.90 0.10 0.10 0.10 0.10 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 0.90 0.90 0.90 0.90 1. 1. 1. 1. 0.910 0.910 0.910 0.910 0.700 0.700 0.700 0.700 1.61 1.61 1.61 1.61 1.9 1.9 1.9 1.9 Switching Times (0Ω Load) Min Typ Max ns Propagation Delay t++ t+ t + t t++ t+ t + t Inputs,9 or 1 to either Output Inputs,7 or 1 to either Output Rise Time (0 to 0%) t+ **.... Fall Time (0 to 0%) t **.... * Individually test each input applying V IH or V IL to input under test. ** Any Output..........0.0.0.0.....7.7.7.7.7.7.7.7 Vdc Vdc Vdc Vdc
ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic @ Test Temperature V IHmax V ILmin V IHAmin V ILAmax V EE Symbol 0 C 0.90 1.90 1.0 1.00. + C 0.10 1.0 0 1.7. + C 0.700 1. 1.0 1.0. Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW Under (V CC ) Test V IHmax V ILmin V IHAmin V ILAmax V EE Gnd Power Supply Drain Current I E Input Current I inh, 9, 1 Output Voltage Logic 1 V OH Output Voltage Logic 0 V OL Threshold Voltage Logic 1 V OHA Threshold Voltage Logic 0 V OLA * * I inl * *,, Switching Times (0Ω Load) +V Pulse In Pulse Out. V +.0 V Propagation Delay t++ t+ t + t t++ t+ t + t Inputs,9 or 1 to either Output Inputs,7 or 1 to either Output, 9, 1, 9, 1, 9, 1, 9, 1 Input, 9 or 1 Input, 7 or 1 Corresponding XOR/XNOR Outputs Corresponding XOR/XNOR Outputs Rise Time (0 to 0%) t+ **, 9, 1 Any Input Corresponding Fall Time (0 to 0%) t **, 9, 1 Any Input XOR/XNOR Outputs * Individually test each input applying V IH or V IL to input under test. ** Any Output. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 00 linear fpm is maintained. Outputs are terminated through a 0-ohm resistor to.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
PACKAGE DIMENSIONS PLCC 0 FN SUFFIX PLASTIC PLCC PACKAGE CASE 77 0 ISSUE C B N Y BRK U D L M Z W D X G1 V VIEW D D Z A R K1 H C G G1 E J T VIEW S VIEW S K F
PACKAGE DIMENSIONS T F A E G D 16 PL B C N CDIP 16 L SUFFIX CERAMIC DIP PACKAGE CASE 60 10 ISSUE T K L M J 16 PL H A G B F C S K D 16 PL T PDIP 16 P SUFFIX PLASTIC DIP PACKAGE CASE 6 0 ISSUE R J L M
Notes 6
Notes 7
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