PACS 85.0.Tv Impact of sidewall spacer on ate leakae behavior of nano-scale MOSFETs Ashwani K. Rana 1, Narottam Chand, Vinod Kapoor 1 1 Department of Electronics and Communication, National Institute of Technoloy, Hamirpur Hamirpur (H.P)-177005, India E-mail: ashwani_paper@yahoo.com; kapoor@nitham.ac.in Department of Computer Science and Enineerin, National Institute of Technoloy, Hamirpur Hamirpur(H.P.)-177005, India E-mail: nar@nitham.ac.in Abstract. Semiconductor devices with a low ate leakae current are preferred for low power application. As the devices are scaled down, sidewall spacer for CMOS transistor in nano-domain becomes increasinly critical and plays an important role in device performance evaluation. In this work, ate tunnelin currents have been modeled for a nano-scale MOSFET havin different hih-k dielectric spacer such as SiO, Si N 4, Al O, HfO. The proposed model is compared and contrasted with Santaurus simulation results and reported experimental result to verify the accuracy of the model. The areement found was ood, thus validatin the developed analytical model. It is observed in the results that ate leakae current decreases with the increase of dielectric constant of the device spacer. Further, it is also reported that the spacer materials impact the threshold voltae, on current, off current, drain induced barrier lowerin and subthreshold slope of the device. Keywords: MOSFET, spacer, leakae current. Manuscript received 0.09.10; accepted for publication 16.0.11; published online 0.06.11. 1. Introduction To improve the performances of electronic devices, the size of their active components is scaled down accordin to the International Technoloy Roadmap for Semiconductors (ITRS) [1]. As we approach the nanoreime, a whole new set of problems reardin the device performance arises []. The control of leakae power is one of the most important issues for scalin MOSFET towards nano-reime []. For nano-scale MOSFET, ate leakae current is considered as a dominant leakae component as compared to subthreshold leakae [4], as ate ide thickness approaches its manufacturin and physically limitin value of less than nm []. Hence, accurate estimation of the ate leakae current is essential to appreciate the total offstate power dissipation. Numerous models have been developed numerically [5-7] in the past for calculatin the tunnelin current, but this approach is not always practical and is time consumin. Schueraf et al. [8, 9] have derived a simple analytical formula to represent direct tunnelin throuh a trapezoidal barrier. However, this model suffers from various limitations such as (i) ate current does not approach to zero as ate voltae oes to zero and does not fit experimental data at sub-1-v ate bias rane, (ii) the assumption of constant effective mass for all eneries is not accurate, (iii) nonconsideration of quantum effects. Lee and Hu [10, 11] proposed a semi-empirical model by introducin the correction function to Schueraf s analytical model to take care of above-mentioned secondary effect. However, this model has not considered the ede direct tunnelin current (EDT). In [1], direct tunnelin current expressions have been developed both for channel ate tunnelin current and EDT includin polydepletion effect and quantization effect with four adjustable parameters. This model does not include: (i) the nonuniform dopant profile in polyate in vertical direction resulted due to low enery ion implantation, (ii) additional depletion layer at the ate edes due to ate lenth scalin down, and (iii) ate ide barrier 0
lowerin due to imae chares across the Si/SiO interface. These nano-scale effects (NSE) are inevitable for nano-scale devices operatin into deep sub-50-nm reime. Therefore, it is mandatory to include these NSE effects in nano-scale MOSFET to achieve an accurate estimation of the ate tunnelin current. In this work, an effective model has been developed for analyzin the ate tunnelin current of nano-scale NMOSFET by considerin the NSE effect that are difficult to inore at nano-scale reime. This work mainly focuses on the impact of device spacer on ate leakae current and other device parameters. The rest of the paper is oranized as follows. In Section, modelin of the ate tunnelin current is developed. The device structure and desin used for simulation of set up is presented in Section. The results obtained are discussed in Section 4. Finally, concludin remarks are offered in Section 5.. Theoretical model In ultra short-channel MOSFETs, in addition to ate to channel direct tunnelin current, the source/drain extensions (overlap reions) direct tunnelin current known as ede direct tunnelin current (EDT) has been identified as the principal source of off-state power dissipation in VLSI chips because source/drain extensions (overlap reions) under poly-silicon ate represent a sinificant fraction of the device, as they do not scale at the same rate as the ate lenth. Therefore, the evaluation of EDT is critical for state of the art MOSFETs. Modelin of the direct tunnelin current analytically has been larely based on the WKB apprimation [8]. The discrepancies that were present in the oriinal WKB apprimation [8] have been rectified in [10, 11] by introducin few adjustin parameters but they nelected the nano-scale effects. In our work, we adopt this model to evaluate the direct tunnelin current from channel and overlap reion in the nano-scale reime by takin the nano-scale effect into account. In this scheme, the value of fittin parameter α( ch, for channel and overlap reion has been used as 0.6 and 0.45, respectively, with ide spacer to match the overall best fit with Santaurus simulation and also with the experimental results reported in [1]. The T refers to the physical ide thickness and effective mass of the carrier in the ide has been used as 0.40 m o throuh this work. The total ate leakae current is iven by I = I + I + I, (1) c I c so do I so where is the ate-to-channel tunnelin current, is the ate-to-source overlap reion ate tunnelin current, and I do is the ate-to-drain overlap reion tunnelin current. Since drain to source Vds is taken to be zero for simplification, so I can be modified as below I = I + I ; I = I. () c ov ov so The channel current I c and EDT current I ov per micrometer can be written as: I c = J ch L eff ; I ov = J ov L ov. L eff = L L ov, where L is the total ate lenth, L ov is the overlap ate lenth, and L eff is the effective ate lenth. The channel current density J ch and overlap current density J ov are modeled as follows: J = AC T, () ( ch, F ( ch, WKB( ch, A = q C 8πφb _ eff ε F ( ch, T( ch, where, is the correction term incorporated in [10, 11] and is the modified WKB transmission probability and are modified for channel and overlap reion. ε is the permittivity of the ate ide and φ b _ eff is the effective barrier heiht, calculated as below, φb _ eff = φb Δφ, (4) 4 qe i qvi q Neff φb _ eff Δφ = = =. (5) 4πε 4πε 16 i iti π εi Δ φ is the reduction in the barrier heiht at the hih-k/si interface from φ b, so that the barrier heiht becomes. This reduction in barrier heiht is due to φ b _ eff imae chares across the interface. This barrier reduction is of reat interest, since it modulates the ate tunnelin current. c = ( chov, ) α( chov, ) 0 V ( chov, ) φb _ eff_ V( chov, ) 1 1 V exp N (, ), b_ eff b_ eff b_ eff DTC chov + = φ φ φ T. T WKB ( ch, ov ) N DTC ( ch ) 8π = exp m V ( _ 1 φb eff 1 φb hq E 1 ( ch, ε n acc v t ln 1 + exp t i for V < 0 = ε n ln 1 + exp inv v t t i for V > 0 ch, _ eff ( V V ) ( V V ) n n acc inv v ( V ) ε n acc v t ln 1 + exp t i n acc v t for V < 0 N DTC ( ov ) = ε ( V ) e n ln 1 + exp inv v t t i n inv v t for V > 0 v t FB t th, 04
Where α ( ch, is the fittin parameter dependin upon channel or source/drain overlap tunnelin, n inv and nacc are the swin parameters, VFB represents the flat band voltae, denotes the density of carrier N DTC ( ch, in channel/overlap reion dependin upon MOSFET biasin condition, and V e is the effective ate voltae excludin polyate non-uniformity and ate lenth effect and is equal to V V poly, where V poly is the voltae drop due to polydepletion in the polyate. The default values of ninv and nacc are S / vt (S is the sub-threshold swin and v t is the thermal voltae) and 1, respectively. The correction factor C F ( ch, ov ) and transmission probability T WKB( ch, are different for channel and source/drain overlap reion, because both channel and overlap components have different values of V ( ch, and N DTC ( ch,. It is because of the fact that overlap reion has almost zero flat band voltae, as both SDE reion and overlyin polyate Si are heavily doped n + reions. N DTC( ch, has been iven differently for both reion as in (1) and (1). The ate ide voltae V for the channel and SDE overlap are calculated as follows. Case (i): when V > 0. In this biasin condition for MOSFET device, there is a depletion layer in the polyate thereby causin an additional potential drop across the ate. The SDE reion enters into accumulation and substrate reion enters into the week inversion below V th and stron inversion beyond V th. Therefore, both the channel and EDT component are present and are comparable. Case (ii): when V FB < V < 0. Here, ate tunnelin current is dominated by the EDT where electric field is such that electron are directed from the accumulated polyate into the overlap reion. On the other hand, substrate is in depletion/weak inversion and constitutes a neliible tunnelin current. This reion of biasin is primarily responsible for offstate power dissipation. Thus, EDT plays an important role in the evaluation of off-state power dissipation. Case (iii): when V < V FB. In this reion of operation, substrate oes into accumulation. As a result, both current components become comparable. The voltae across the ate ide for different reion of operation is as follows: ( V φs VFB ) for V < 0 V = (6) V φ V for V > 0 ( ) e s FB Where φ s is the surface band bendin of the substrate and are calculated for channel and overlap reion dependin upon the biasin condition of the MOSFET device includin the poly-non-uniformity, ate lenth effects and imae force barrier lowerin. The ate effective voltae in the ate is derived as follows: ( qε N T ) ) 1. 05 V e si = ( V ε poly FB + φ so ΔV ε 1 + p1 ΔV ( V qε si p V N ) + φ FB poly T so (7) This equation includes the non-uniformity in the ate dopant profile throuh the term and frinin ΔV p1 field effect, i.e. ate lenth effect throuh a term Δ V p. φ so is surface band bendin of the substrate by takin the quantization effect into account. The potential drop Δ V p1 due to non-uniform dopant profile in poly-si ate, caused by low enery implantation, is calculated as below kt N poly top ΔV p = ln.(8) 1 q N poly bottom N and N are the dopin poly top poly bottom concentration at the top and bottom of the poly-silicon ate. The potential drop Δ V p due to the ate lenth effect, caused by very short ate lenths, is iven below: Q qan d Δ V Δ = V (9) C d p ε = δ C d spacer π L C d ( ), cm T F T i cos π ln T F, T F T i 1 + π T F (10) where A denotes the trianular area of the additional chare, L is the ate lenth, C d is the depletion capacitance in the sidewalls [1], ε i is the permittivity of the device spacer, T F is the thickness of the device spacer, T i is the thickness of the ate insulator, and δ is the fittin parameter normally equal to 0.95.. Simulation set up Fi. 1 shows the device structure used for simulation in Santaurus simulator. The deep S/D reion is composed of a heavily doped silicon and a silicide contact. Dopin the silicon S/D reion is assumed to be very hih, 1 10 0 cm, which is close to the solid solubility limit and introduces neliible silicon resistance. The dimension of the silicon S/D reion is taken as 50 nm lon and 0 nm hih. This ives a lare contact area resultin in a small contact resistance. The heavily doped silicon called deep S/D reion extends into the silicon film at both ends and constitutes the extended S/D for the device (labelled by S 1 and D 1 in Fi. 1). The dopin concentration of the acceptors in the silicon channel reion is assumed to be raded due to diffusion of dopant ions from heavily doped S/D reion with a peak value of 1 10 18 cm and
Gate Tunnelin Current (A/um) 1E-6 1E-7 1E-8 Santaurus Simulation Our Model with NSE Model without NSE Fi. 1. NMOSFET device structure used in simulation. 1 10 17 cm near the channel. The dopin concentration in the poly-silicon ate is 1 10 cm at the top and 1 10 0 cm at the bottom of poly-silicon ate, i.e. interface of ide and silicon. The halo implantation made around S/D also reduces short-channel effects, such as the punch-throuh current, drain induced barrier lowerin (DIBL), and threshold voltae roll-off for different non-overlap lenths. The MOSFET has a 50-nm-thick n + poly-si ate with the metallurical ate lenth of 5 nm and a 1-nm ate ide. The MOSFET with L met of 5 nm was desined to have a V T of 0. V with SiO as spacer. We determined V T by usin a linear extrapolation of the linear portion of the I DS VGS curve at low drain voltaes. The operatin voltae for the devices is 1 V. The simulation study has been conducted in two dimensions, hence all the results are in the units of per unit channel width. The simulation of the device is performed by usin Santaurus desin suite [14, 15] with drift-diffusion, density radient quantum correction and advanced physical model bein turned on. 4. Results and discussion In this section, computation of ate tunnelin currents for a n-channel nano-scale MOSFET havin different sidewall spacer such as SiO (k =.9), Si N 4 (k = 7.5), Al O (k = 9.0) and HfO (k = ) have been carried out. This model is computationally efficient and easy-torealize. This model calculates the ate tunnelin current by usin α (ch/ as fittin parameters. Thus, this model is applicable to many alternate hih-k nano-mosfet simply by adjustin the fittin parameter. Variation of the total ate tunnelin current with a ate bias for a iven values of ate insulator thickness has been presented for possible alternative sidewall spacer such as SiO, Si N 4, Al O and HfO. The impact of sidewall spacer on the device threshold voltae, off current, on current, DIBL and sub-threshold slope (SS) is also reported in results. 1E-9 0.0 0. 0.4 0.6 0.8 1.0 Gate Bias (V) Fi. Comparison of model with simulated data for ate ide thickness of T = 1.0 nm with ide spacer, metallurical ate lenth of L met = 5 nm and S/D overlap lenth of L ov = 10 nm in nano-scale reime. The comparison between the simulated data and the model value for the ate tunnelin current is presented in Fi. for the value L met = 5 nm, L ov = 10 nm, T = 1.0 nm. The model value while considerin the nano-scale effect shows ood areement with the simulated value over the entire positive ate bias rane, certifyin the hih accuracy of the proposed analytical modellin. Model also shows ood areement with simulated data for various sidewall spacers but with different values of the fittin parameter as listed in Table 1. It is also shown that the model value without any nano-scale effect does not show ood areement with the simulated value, emphasizin the need to include nano-scale effect. Similarly, the model is also verified in Fi. with experimental data published in [1] for value L = 0.17 µm, L ov = 10 nm, T = 1.85 nm and W = 10 µm. The substrate dopin and poly-silicon ate dopin have been taken to be 10 17 4.1 cm and 0 5 10 cm, respectively. The model value also shows ood areement with the experimental data over the entire ate bias rane, certifyin the hih accuracy of the proposed analytical modellin. Fi. 4 shows the variation of the ate tunnelin current and off current of the NMOS device with S/D overlap lenth for optimization of the latter at a iven ate bias of 0.6 V and ate ide thickness of 1.0 nm. It is observed that off current for a device under consideration is slihtly less at S/D overlap lenth of 5 nm. Therefore, S/D overlap lenth of 5.0 nm is considered in further results. Table 1. Fittin parameter for calculation of the ate tunnelin current throuh different sidewall spacers. Parameter SiO Si N 4 Al O HfO α ch 0.6 0.6 0.71 0.78 α 0.45 0.49 0.5 0.55 ov 06
1E-7 1E-8 Experimental Data Model Data 1E-7 Gate Tunnelin Current (A/um) 1E-9 1E-10 1E-11 1E-1 Gate Tunnelin Current (A/um) 1E-8 1E-9 SiO Si N 4 Al O HfO T=1.0 nm 1E-1-1.5-1.0-0.5 0.0 0.5 1.0 1.5 Gate Bias (V) Fi.. Comparison of the model with experimental data for N sub = 4.1 10 17 cm and N poly = 5 10 19 cm with ide spacer. 0.0 0. 0.4 0.6 0.8 1.0 Fi. 5. Gate tunnelin current vs ate bias for different sidewall spacer in nano-scale reime at L met = 5 nm and L ov = 5.0 nm. Current (A/um) 0.0000008 0.0000006 0.0000004 0.000000 Gate Tunnelin Current (A/um) Off Current (A/um) x T=1.0 nm Threshold Voltae (V) 0.4 0. 0. 0.1 0.0 0.19 0.18 0.17 0.16 0.0000000 4 5 6 7 8 9 10 S/D Overlap Lenth (nm) 0.15 SiO SiN4 AlO HfO MOSFET with increasin Dielectric Constant(K) Fi. 4. Gate tunnelin current and off current vs S/D overlap lenth for T = 1.0 nm, L met = 5 nm. Fi. 6. Device threshold voltae vs sidewall spacer with L met = 5 nm and L ov = 5.0 nm. Fi. 5 shows variation of the ate tunnelin current with the ate bias for various sidewall spacers at ate ide thickness of 1.0 nm. It is observed that ate leakae current improves with the introduction of sidewall spacer of increasin dielectric constant K. The application of hih-k spacer enhances the frinin electric field thereby reducin the effective ate voltae. This reduction lowers the transverse electric field responsible for carrier tunnelin throuh ate ide. Consequently, the ate leakae current reduces as dielectric constant of the sidewall spacer increases. In Fi. 6, variation of the device threshold voltae with sidewall spacer is presented. As the dielectric constant of the sidewall spacer increases, the frinin field increases. These field lines finally induce an electric field from the source-to-channel thereby reducin the source-to-channel barrier heiht. Since the threshold voltae of the device is controlled by the injection of electrons over this potential barrier, it decreases with increasin dielectric constant of the sidewall spacer. Thus, sidewall spacers with a larer dielectric permittivity reduce the threshold voltae owin to the enhanced value of frinin electric field. DIBL (mv/v) 80 75 70 65 60 Drain Induced Barrier Lowerin(DIBL) Subthreshold Slope(SS) SiO SiN4 AlO HfO MOSFET s with increasin K Fi. 7. Drain induced barrier lowerin (DIBL) and subthreshold slope (SS) vs sidewall spacer with L met = 5 nm and L ov = 5.0 nm. Fi. 7 shows that DIBL increases with increase in dielectric constant of the sidewall spacer. It is due to the fact that the increased effect of frinin field on channel by the application of hih-k sidewall spacer weakens the ate control over the channel reion of a MOSFET. Due to this decrease in ate control, the drain electrode is tihtly coupled to the channel, and the lateral electric 95 90 85 80 SS (mv)/dec) 07
Current (A/um) 0.1 0.01 1E- 1E-4 1E-5 1E-6 On Current (I on ) Off Current (I off ) SiO SiN4 AlO HfO MOSFET s with increasin K Fi. 8. On and off currents vs sidewall spacer with L met = 5 nm and L ov = 5.0 nm. field from the drain reaches a larer distance into the channel. Consequently, this electrically closer primity of drain to source ives rise to hiher drain-induced barrier lowerin in MOS transistors. It is also shown in Fi. 7 that sub-threshold characteristics derade due to decrease in the threshold voltae. As shown in Fi. 8, on current (I on ) and off current (I off ) derade slihtly due to a decrease in the threshold voltae as well as due to the deraded sub-threshold characteristics. 5. Conclusion The impact of sidewall spacer on ate leakae current and other device parameters is studied usin the ate tunnel model and extensive device simulations. A hih-k sidewall spacer lowers the ate leakae current while increases the sub-threshold slope with drain induced barrier lowerin. Sidewall spacers with a larer dielectric permittivity reduce the threshold voltae owin to the enhanced value of frinin electric field. It is found that the use of hih-k sidewall spacers also derades the on and off current marinally. References 1. Online. Available: http://www.itrs.net/reports.html. C.H. Choi, K.Y. Nam, Z. Yu, and R.W. Dutton, Impact of ate direct tunnelin current on circuit performance: A simulation study // IEEE Trans. Electron Devices, 48, p. 8-89 (Dec. 001).. F. Rana, S. Tiwari, and D. Buchanan, Selfconsistent modelin of accumulation layers and tunnelin currents throuh very thin ides // Appl. Phys. Lett., 69, p. 1104-1106 (1996). 4. S.-H. Lo, D.A. Buchanan, Y. Taur, and W. Wan, Quantum-mechanical modelin of electron tunnelin current from the inversion layer of ultrathin-ide nmosfets // IEEE Electron Device Lett., 18, p. 09-11 (May 1997). 5. W.K. Shih et al., Modelin ate leakae current in nmos structures due to tunnelin throuh an ultrathin ide // Solid State Electron., 4, p. 997-1006 (June 1998). 6. K. Roy, S. Mukhopadhyay, and H. Mahmoodi- Meimand, Leakae current mechanisms and leakae reduction techniques in deepsubmicrometer CMOS circuits // Proc. IEEE, 91(), p. 05-7 (Feb. 00). 7. Y. Ando and T. Itoh, Calculation of transmission tunnelin current across arbitrary potential barriers // J. Appl. Phys., 61(4), p. 1497 (1987). 8. K.F. Schueraf, C.C. Kin, and C. Hu, Ultra-thin silicon diide leakae current and scalin limit // Symposium on VLSI Technoloy Diest of Technical Papers, p. 18-19 (199). 9. K.F. Schueraf and C. Hu, Hole injection SiO breakdown model for very low voltae lifetime extrapolation // IEEE Trans. on Electron Devices, 41(5), 1994. 10. W.C. Lee and C. Hu, Modelin ate and substrate currents due to conduction- and valence-band electron and hole tunnelin // Symposium on VLSI Technoloy Diest of Technical Papers, p. 198 (000). 11. W.C. Lee and C. Hu, Modelin CMOS tunnelin currents throuh ultrathin ate ide due to conduction- and valence-band electron and hole tunnelin // IEEE Trans. Electron Devices, 48(7), (001). 1. Xin (Ben) Gu, Ten-Lon Chen, Gennady Gildenblat,, Glenn O. Workman, Surya Veerarahavan, Shye Shapira, and Kevin Stiles, A surface potential-based compact model of n- MOSFET ate-tunnelin current // IEEE Trans. Electron Devices, 51(1), (004). 1. Steve Shao-Shiun Chun and Tun-Chi Li // IEEE Trans. Electron Devices, 9(), (199). 14. ISE TCAD: Synopsys Santaurus Device User Manual, 1995-005, Synopsys, Mountain View, CA. 15. ISE TCAD: Synopsys Santaurus Device simulator. 08