Solutions to Assignment No 5 Digital Techniques Fall 2007

Solutions to Assignment No 5 Digital Techniques Fall 2007 André Deutz October 19, 2007 1 Simplifying and Manipulating Boolean Expressions 1. Simplification (a) Simplify each of the following expressions, using one of the basic theorems: i. (AB + CD)(AB + E) AB + CDE (distributivity) ii. A + BC + DE(A + BC) A + BC (absorption) iii. A + BC + (DE + F )(A + BC) A + BC + DE + F (elimination of complement) Alternatively (due to typo): A + BC + (DE + F )(A + BC) A + BC (absorption) (b) Simplify the following expressions using the postulates and theorems stated in the table of Assignment No 4. i. X + Y + XY + (X + Y )XY X + Y + XY (absorption) X + Y + (X + Y ) (DeMorgan) 1 (complement) Alternatively: X + Y + XY + (X + Y )XY X + Y + (X + Y ) + (X + Y )XY (DeMorgan) 1 + (X + Y )XY (complement) 1 (one theorem) ii. XY Z + XY Z + XY Z + XY Z XY (Z + Z) + XY Z + XY Z (distributivity) XY 1 + XY Z + XY Z (complement) XY + XY Z + XY Z (identity) XY + XZ(Y + Y ) (distributivity) 1

XY + XZ1 (complement) XY + XZ (identity) iii. X Y X Z X Y + X Z(DeMorgan) X Y + X Z(Involution (twice)) iv. (X + Y )(X + Z)(Y + Z) X(X + Z)(Y + Z) + Y (X + Z)(Y + Z) (distributivity) XZ(Y + Z) + Y (X + Z)(Y + Z) (elimination of complement) XY Z + Y (X + Z)(Y + Z) (elimination of complement) XY Z + Y Z(X + Z) (elimination of complement) XY Z + X Y Z (elimination of complement) Alternatively: (X + Y )(X + Z)(Y + Z) (XX + XZ + X Y + Y Z)(Y + Z) (distributivity) (0 + XZ + X Y + Y Z)(Y + Z)(complement) (XZ + X Y + Y Z)(Y + Z)(identity) (XZ + X Y )(Y + Z)(consensus) XY Z + X Y Y + XZZ + X Y Z(distributivity) XY Z + 0 + 0 + X Y Z(complement and zero theorem) XY Z + X Y Z(identity) v. (W + X + Y Z)(W + X)(X + Y ) (X + (W + Y Z)W )(X + Y ) (distributivity) (X + W Y Z)(X + Y ) (elimination of complement) X(X + W Y Z) + Y (X + W Y Z) (distributivity) X W Y Z + Y (X + W Y Z) (elimination of complement) X W Y Z + XY + W Y Z) (distributivity) XY + W Y Z (absorption) Alternatively: Before embarking on the alternative solution, we first prove a simple consequence of the consensus theorem: (A + B)(A + C) = AC + AB Proof: (A + B)(A + C) = AC + AB AA + AC + BA + BC(distributivity) 0 + AC + BA + BC(complement) AC + BA + BC(identity) AC + BA (consensus) Next we resume with the alternative approach: (W + X + Y Z)(W + X)(X + Y ) (W + X + Y Z)(XY + X W ) ( by (A + B)(A + C) = AC + AB ) W XY +W X W +XXY +XX W +Y ZXY +Y ZXW (distributivity) W XY + XXY + Y ZXY + Y ZXW (complement and identity) W XY + XY + ZXY + Y ZXW (idempotence) XY (W + 1 + Z) + Y ZXW (distributivity) XY + Y ZXW (one theorem) 2

Y (X + W XZ))(distributivity) Y (X + W Z))(elimination of complement) Y X + Y W Z (distributivity) vi. W XZ + XY Z + W XY + XY Z + W Y Z Y Z(X + X) + W XZ + W XY + W Y Z (distributivity) Y Z(1) + W XZ + W XY + W Y Z (complement) Y Z + W XZ + W XY + W Y Z (identity) Y Z + W XZ + W XY (absorption) (Y + W XZ + W XY )(Z + W XZ + W XY ) (distributivity (Y + W XZ + W X)(Z + W XZ + W XY ) (elimination of complement) (Y + W X)(Z + W XZ + W XY ) (absorption) (Y + W X)(Z + W X + W XY ) (elimination of complement) (Y + W X)(Z + W X) (absorption) W X + Y Z (distributivity) Alternative solution: W XZ + XY Z + W XY + XY Z + W Y Z W XZ + W XY + Y Z(X + X + W ) (distributivity and commutativity) W XZ + W XY + Y Z(1 + W ) (complement) W XZ + W XY + Y Z (one theorem) W X(Z + Y ) + Y Z(distributivity) W X(Z + Y ) + Y Z(involution) W XZ Y + Y Z (DeMorgan) W X + Y Z (elimination of complement) vii. W XZ + W Z + XY Z + W XY (W + W XZ + XY Z + W XY )(Z + W XZ + XY Z + W XY ) (distributivity) (W + XZ + XY Z + W XY )(Z + W XZ + XY Z + W XY ) (elimination of complement) (W + XZ + XY Z + XY )(Z + W XZ + XY Z + W XY ) (elimination of complement) (W + XZ + XY )(Z + W XZ + XY Z + W XY ) (absorption) (W + XZ + XY )(Z + XY Z + W XY ) (absorption) (W +XZ +XY )(Z +XY +W XY ) (elimination of complement) (W + XZ + XY )(Z + XY ) (absorption) XY + (W + XZ)Z (distributivity) XY + W Z + XZZ (distributivity) XY + W Z + XZ (idempotence) Alternative solution: W XZ + W Z + XY Z + W XY Z(W X + W ) + XY Z + W XY (distributiviteit) Z(X + W ) + XY Z + W XY (elimination of complement) 3

ZX + ZW + XY Z + W XY (distributivity) X(Z + Y Z) + ZW + W XY (distributivity) X(Z + Y ) + ZW + W XY (elimination of complement) XZ + XY + ZW + W XY (distributivity) XZ + XY (1 + W ) + ZW (distributivity) XZ + XY 1 + ZW (one theorem) XZ + XY + ZW (identity) viii. (X + Y + Z)(X + Y + Z)(X + Y + Z) (Y + (X + Z)(X + Z))(X + Y + Z) (distributivity) Y + (X + Z)(X + Z)(X + Z) (distributivity) Y + (X + Z)(X + ZZ) (distributivity) Y + (X + Z)(X + 0) (complement) Y + (X + Z)X (identity) Y + XX + XZ (distributivity) Y + 0 + XZ (complement) Y + XZ (identity) For the alternative approach we will use two theorems: 1) (A + B)(A+C) = AC +AB, already proved above and 2) (A+B)(A+ B) = A. Proof: AA + AB + BA + BB = A + AB + BA + 0 = A(1 + B + B) = A(1 + 1) = A 1 = A Alternative approach: (X + Y + Z)(X + Y + Z)(X + Y + Z) (Y + Z)(X + Y + Z) (by (A + B)(A + B) = A) Z(X + Y ) + ZY (by (A + B)(A + C) = AC + AB) ZX + ZY + ZY (distributivity) ZX + Y (Z + Z) (distributivity) ZX + Y 1 (one theorem) ZX + Y (identity) 2. Manipulation (a) Convert AB + CD to an equivalent PoS expression. Approach 1 (we will not get the standard PoS): AB + CD (AB + C)(AB + D) (distributivity) (A + C)(B + C)(A + D)(B + D) (distributivity) Approach 2 (in this approach we will get the standard PoS as an extra): Consider F (A, B, C, D) := AB + CD 4

max term expression input combination minterm expression F(A,B,C,D) M 0 = A + B + C + D 0000 m 0 = A B C D 0 M 1 = A + B + C + D 0001 m 1 = A B CD 0 M 2 = A + B + C + D 0010 m 2 = A BC D 0 M 3 = A + B + C + D 0011 m 3 = A BCD 1 M 4 = A + B + C + D 0100 m 4 = AB C D 0 M 5 = A + B + C + D 0101 m 5 = AB CD 0 M 6 = A + B + C + D 0110 m 6 = ABCD 0 M 7 = A + B + C + D 0111 m 7 = ABCD 0 M 8 = A + B + C + D 1000 m 8 = AB C D 1 M 9 = A + B + C + D 1001 m 9 = AB CD 1 M 10 = A + B + C + D 1010 m 10 = ABC D 1 M 11 = A + B + C + D 1011 m 11 = ABCD 1 M 12 = A + B + C + D 1100 m 12 = ABC D 0 M 13 = A + B + C + D 1101 m 13 = ABCD 0 M 14 = A + B + C + D 1110 m 14 = ABCD 0 M 15 = A + B + C + D 1111 m 15 = ABCD 1 Now we proceed to answer the question What is a PoS of F?. We do this in two steps: i. First we determine a SoP of F ii. Secondly we compute the PoS of F by applying DeMorgan s law: F = F = SoP of F In more detail: From the above truth table it is very easy to determine what the canonical SoP of F is, namely the sum of all the minterms not used by F. That is, F = m 0 + m 1 + m 2 + m 4 + m 5 + m 6 + m 7 + m 12 + m 13 + m 14. From this we get: F = F = SoP of F = m 0 + m 1 + m 2 + m 4 + m 5 + m 6 + m 7 + m 12 + m 13 + m 14. By De- Morgan s Law we get F = m 0 m 1 m 2 m 4 m 5 m 6 m 7 m 12 m 13 m 14. By applying DeMorgan s Law to each of the eleven minterms we get (eleven maxterms): F = M 0 M 1 M 2 M 4 M 5 M 6 M 7 M 12 M 13 M 14 By a look-up in the above table we get the gory Answer: F = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) Remark: In order to compute a PoS you just need some SoP (not necessarily the standard = canonical SoP ) of F. But if the SoP of F is canonical, then we get the canonical PoS of F. Recall that a SoP is canonical(=standard) if each of the product terms involves contains all the variables (or their negation): Example: AB + ABCD + AD is not canonical since the first nor the third product term contains all the variables; the first does not contain C nor D (nor their negations) and the third does not contain B nor C (nor their negations). Remark: This second approach is just about the only feasible way to compute the PoS of the function in 3.2.(a) of the Proeftentamen. (b) Express XY +UV W in terms of the NAND operation by considering 5

XY + UV W and applying DeMorgan. Applying DeMorgan like the assignment tells us we get: X Y U V W There s still a negation in the formula. We can rewrite negation because X = X 1, or alternatively X = X X. So we get: X Y U V W 1 This already satisfies the constraints set by the assignment. However, if the assignment had limited us to 2 input NAND gates we d have to rewrite UV W. The easiest way to do this is to rewrite UV using NAND gates so that the output of UV is one of two inputs for the NAND gate which currently requires three inputs. One way to do this is to negate UV twice like this: X Y U V W 1 This leaves us with a number of NAND operations and a single negation. We already know how to rewrite the negation. X Y U V 1 W 1 The resulting expression only uses 2 input NAND gates. 2 Karnaugh maps 1. Explain what the main idea is behind Karnaugh maps (a.k.a. K-Maps or Karnaugh-diagrams) 2. Plot the following function on a K-map and then find a minimal-sum expression for it: Z = B C + ABD + ABCD + BC Answer: B + AD + ACD 3. Find the minimal SoP expression for the function plotted in the following K-map figure: CD 00 01 11 10 AB 00 A B C D 1 A B C D 1 AB C D 1 AB C D 01 A B CD A B CD 1 AB CD AB CD 1 11 A BCD 1 ABCD 1 ABCD 1 ABCD 1 10 A BCD 1 ABCD ABCD 1 ABCD Answer: A possible answer is BCD + ACD + AC D + BCD + A BC + A BD 3 Don t Care Conditions and Karnaugh Map Example In all the logic design problems we have encountered so far, a specific output value has been associated with each of the possible input values. Occasionally, a system exists in which a certain combination of inputs cannot happen. In such cases, the output may be defined as either true or false. After all, if a particular 6

input is impossible, the corresponding output is meaningless. Or is it? Later we shall see how we can turn these meaningless outputs to good use. To make the concept of impossible input conditions a little clearer, consider the following example. An air-conditioning system has two control inputs. One, C, is from a cold sensing thermostat, and is true if the temperature is below 15 o C, and false otherwise. The other input, H, is from a hot-sensing thermostat and is true if the temperature is above 22 o C, and false otherwise. As there are two inputs, there are four possible logical conditions as illustrated in the following table: Inputs Meaning C H 0 0 Temperature OK 0 1 Too hot 1 0 Too cold 1 1? The input condition C = 1, H = 1 has no real meaning, as it is impossible to be too hot and too cold simultaneously. Such an input condition could arise only if one of the thermostats had become faulty. Consider now the following example of an air-conditioning unit with four inputs and four outputs. The following table defines the meaning of the inputs to the controller. Input Name Meaning when input=0 Meaning when input=1 H Hot temperature < upper limit temperature > upper limit C Cold temparture > lower limit temperature < lower limit W Wet humidity < upper limit humidity > upper limit D Dry humidity > lower limit humidity < lower limit The controller has four outputs P, Q, R, and S. When P = 1 a heater is switched on, and when Q = 1 a cooler is switched on. Similarly, a humidifier is switched on by R = 1, and a dehumidifier by S = 1. In each case a logical zero switches off the appropriate device. The relationship between the inputs and outputs is as follows. If the temperature and humidity are both within limits, switch off the heater and the chiller(=cooler). The humidifier and dehumidifier are both switched off unless stated otherwise. If the humidity is within limits, switch on the heater if the temperature is too low, and switch on the cooler it the temperature is too high. If the temperature is within limits, switch on the heater if the humidity is too low, and the cooler if the humidity is too high. If the humidity is high, and the temperature low, switch on the heater. If the humidity is low, and the temperature high, switch on the cooler. If both the temperature and humidity are high, switch on the cooler and dehumidifier. If both the temperature and humidity are too low, switch on the heater and humidifier. The relationship between inputs and outputs can now be expressed in truth table (see below). 7

Inputs Outputs H C W D Condition P Q R S 0 0 0 0 OK 0 0 0 0 0 0 0 1 Dry 1 0 0 0 0 0 1 0 Wet 0 1 0 0 0 0 1 1 Impossible x x x x 0 1 0 0 Cold 1 0 0 0 0 1 0 1 Cold and Dry 1 0 1 0 0 1 1 0 Cold and wet 1 0 0 0 0 1 1 1 Impossible x x x x 1 0 0 0 Hot 0 1 0 0 1 0 0 1 Hot and dry 0 1 0 0 1 0 1 0 Hot and wet 0 1 0 1 1 0 1 1 impossible x x x x 1 1 0 0 impossible x x x x 1 1 0 1 impossible x x x x 1 1 1 0 impossible x x x x 1 1 1 1 impossible x x x x The don t care conditions are so called because the corresponding input conditions cannot occur. Of course, any real combinational logical unit (aka combinatorial digital circuit) with n-inputs must have a particular logical output for each of the 2 n input combinations. In other words, if an input (combination) which is classified as a don t- care is applied to the the circuit, it must produce either a logical one or a zero at the output. We choose the output to be a one or a zero to simplify the design of the circuit. That is, if an xcan be used to turn a group of ones into a larger group of ones on a Karnaugh map, it is taken as a logical one. Otherwise it is made a zero. Draw the Karnaugh map for each of the outputs P through S and get the simplified Boolean expression for each of them. For example, let us draw the Karnaugh map for P first: HC WD 00 01 11 10 00 H C W D H C W D 1 H C W D x H C W D 01 HC W D 1 HC W D 1 1 HCW D x x HCW D 1 11 HC W D x HC W D x HCW D x HCW D x 10 H C W D H C W D H CW D x H CW D Six of the don t-cares are used to get the following two rectangles (the don t-care in the cell pertaining to HCW D is not used): 1. the first is a square consisting of four cells pertaining to the following minterms: H C W D, H C W D, HC W D, and HCW D. The sum of these four minterms is HD (of course, this has been read off directly from the Karnaugh map. 2. the second rectangle consists of eight cells pertaining to the following minterms: HC W D, HC W D, HCW D, HCW D,HC W D, HC W D, HCW D, and HCW D. The sum of these eight minterms is C which you can read off directly from the K-map. In summary: P = C + HD 8

4 Question on Don t-cares and Karnaugh Maps For this question refer to the previous section: For each of the outputs Q, R, and S construct the Karnaugh diagram and obtain from this the simplified Boolean expression (again for Q, R, and S). Answer: Q = H + CW, R = CD en S = HW. 5 Constructing Useful CLUs In this section we will construct some useful CLUs by means of our primitives (NOT, AND, and OR gates). The CLUs we built can be used in turn to build even more sophisticated CLUs. Continuing in this fashion we get a hierarchy of CLUs. But let us first start with building the useful CLUs of this section. 1. Consider a Combinational Logic Unit (CLU) with the following functionality: the number of inputs is 3 and the number of outputs is 8; we will interpret the input combination consisting of 3 bits as a binary number; the output lines are numbered from 0 to 7, which we label Z 0, Z 1,, Z 7 ; if the binary input bit combination represents the integer i, then the i-th output line is high and the remainder of the lines is low; for instance, suppose the input combination is 101, then the 5th output line (Z 5 ) is high and the 0th through 4th output lines are low as well as the output lines numbered 6 and 7 (i.e., the output wires Z 0, Z 1, Z 2, Z 3, Z 4, Z 6, Z 7 are low). (a) Construct the 1/0-table (for each of the outputs) which specifies the above CLU. (b) Translate your 1-0 specification table for each of the outputs into a Logic Diagram (LD) using our 4-step algorithm of the lecture: that is start with 3 wires and their negations (using NOT gates), giving a total of 6 wires, introduce 3-input-AND gates appropriately, for each of the 3-input-AND gates connect its inputs appropriately with a wire or its negation. For this CLU there is no need for OR-gates. (c) Implement your Logic Diagram in Digital Works. (d) Describe some useful applications for this CLU. 2. In this Assignment we will modify the CLU we have built in 1 slightly. We introduce next to the three inputs, a fourth input wire. If the fourth input wire is low (we will call it E), then all of the output wires Z 0, Z 7 are low. If the wire E is high then the CLU works as before (see 1). Answer the same questions you answered for the CLU you have built in 1: (a) Construct the 1/0-table (for each of the outputs) which specifies the above CLU. (b) Translate your 1-0 specification table for each of the outputs into a Logic Diagram (LD) using our 4-step algorithm of the lecture: that is start with 4 wires and their negations (using NOT gates), giving a total of 8 wires, introduce 4-input-AND gates appropriately, for each of the 3-input-AND gates connect its inputs appropriately with a wire or its negation. For this CLU there is no need for OR-gates. 9

(c) Implement your Logic Diagram in Digital Works. (d) Describe some useful applications for this CLU and describe especially when it would be handy to have the E wire on hand. 3. (a) In class and in Assignment No 2 we have built 1-bit adder with Carry in and Carry out. You have also implemented in Digital Works the Carry out -part of this CLU. Complement this implementation with an implementation of the Sum part (see lecture slides for a Logic Diagram). (b) Using the Logic Diagram for this 1-bit adder construct a Logic Diagram for a 4-bit adder (that is construct a CLU with 9 inputs and 5 outputs such that 4 inputs represent the first binary number, the next 4 inputs represent the second binary number, the 9th input represents the Carry-in (this can be set to low). Four wires of the output represent the binary sum of the two input numbers and the 5th output represents the Carry-out). (c) Implement the Logic Diagram in Digital Works. For now you should do it with copying and pasting your 1-bit adder etc. If you are brave, then you can look into making a Macro for the 1-bit adder and use this to construct the 4-bit adder. 6 Miscellaneous Questions 1. Consider the 2-input-AND implementation by means of relays. (See the powerpoint slides describing the solution to Problem 3 of Assignment No 1 on the website of the course(www.liacs.nl/ deutz/dite)). Design in essentially two different ways a 3-AND gate using relays. 2. Construct a 5-bit Gray code. : Answer 3. Find out what the ball park figure is for the number of transistors per square mm. Answer: a million. 10