Vertical charge transfer and lateral transport in. graphene/germanium heterostructures

Similar documents
Lecture 6: 2D FET Electrostatics

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

Lecture 12: MOS Capacitors, transistors. Context

Lecture 11: MOS Transistor

ECE 342 Electronic Circuits. 3. MOS Transistors

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

Supplementary Figure 1 shows overall fabrication process and detailed illustrations are given

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling

Lecture 4: CMOS Transistor Theory

EECS130 Integrated Circuit Devices

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

EE105 - Fall 2006 Microelectronic Devices and Circuits

This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented.

(a) (b) Supplementary Figure 1. (a) (b) (a) Supplementary Figure 2. (a) (b) (c) (d) (e)

EE 560 MOS TRANSISTOR THEORY

MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Class 05: Device Physics II

MOS Transistor Properties Review

The Gradual Channel Approximation for the MOSFET:

Spring Semester 2012 Final Exam

Supporting information

Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor

Device Models (PN Diode, MOSFET )

Electrical Characteristics of Multilayer MoS 2 FET s

Graphene photodetectors with ultra-broadband and high responsivity at room temperature

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

GaN based transistors

EE105 - Fall 2005 Microelectronic Devices and Circuits

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Lecture 12: MOSFET Devices

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006

The Critical Role of Quantum Capacitance in Compact Modeling of Nano-Scaled and Nanoelectronic Devices

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Lecture 3: CMOS Transistor Theory

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact

Practice 3: Semiconductors

A Multi-Gate CMOS Compact Model BSIMMG

Part 4: Heterojunctions - MOS Devices. MOSFET Current Voltage Characteristics

nmosfet Schematic Four structural masks: Field, Gate, Contact, Metal. Reverse doping polarities for pmosfet in N-well.

Section 12: Intro to Devices

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor Theory

Lecture 04 Review of MOSFET

6.012 Electronic Devices and Circuits

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS

Device Models (PN Diode, MOSFET )

ECE 546 Lecture 10 MOS Transistors

V t vs. N A at Various T ox

VLSI Design and Simulation

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

A. Optimizing the growth conditions of large-scale graphene films

Semiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5

SUPPLEMENTARY INFORMATION

Electrostatic Single-walled Carbon Nanotube (CNT) Field Effect Transistor Device Modeling

MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.

Lecture 11: MOSFET Modeling

MOS Transistor Theory

ECE 340 Lecture 39 : MOS Capacitor II

Content. MIS Capacitor. Accumulation Depletion Inversion MOS CAPACITOR. A Cantoni Digital Switching

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

Microelectronics Part 1: Main CMOS circuits design rules

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Supporting Information. by Hexagonal Boron Nitride

Supporting information. Gate-optimized thermoelectric power factor in ultrathin WSe2 single crystals

NiCl2 Solution concentration. Etching Duration. Aspect ratio. Experiment Atmosphere Temperature. Length(µm) Width (nm) Ar:H2=9:1, 150Pa

FIELD-EFFECT TRANSISTORS

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Extensive reading materials on reserve, including

MOSFET. Id-Vd curve. I DS Transfer curve V G. Lec. 8. Vd=1V. Saturation region. V Th

Semiconductor Integrated Process Design (MS 635)

MOSFET Physics: The Long Channel Approximation

MENA9510 characterization course: Capacitance-voltage (CV) measurements

COMPACT GRAPHENE FIELD EFFECT TRANSISTOR MODELING WITH QUANTUM CAPACITANCE EFFECTS

ECE-305: Fall 2017 MOS Capacitors and Transistors

Prospects for Ge MOSFETs

Theory of Electrical Characterization of Semiconductors

Supplementary Figure 1: Micromechanical cleavage of graphene on oxygen plasma treated Si/SiO2. Supplementary Figure 2: Comparison of hbn yield.

The Devices: MOS Transistors

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations

Appendix 1: List of symbols

Section 12: Intro to Devices

ECE 497 JS Lecture - 12 Device Technologies

MOSFET: Introduction

EE410 vs. Advanced CMOS Structures

Graphene and new 2D materials: Opportunities for High Frequencies applications

Ferroelectric Field-Effect Transistors Based on MoS 2 and

R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6

Components Research, TMG Intel Corporation *QinetiQ. Contact:

MOS CAPACITOR AND MOSFET

Stretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa

Supplementary Figure S1. AFM images of GraNRs grown with standard growth process. Each of these pictures show GraNRs prepared independently,

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

Transcription:

Supporting Information Vertical charge transfer and lateral transport in graphene/germanium heterostructures Alireza Kazemi 1, 4, Sam Vaziri 2, Jorge Daniel Aguirre Morales 3, Sébastien Frégonèse 3, Francesca Cavallo 4, Marziyeh Zamiri 5, Noel Dawson 4, Kateryna Artyushkova,6, Ying Bing Jiang 7, Steven J. R Brueck 4, and Sanjay Krishna 1,4* 1 Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH, United States. 2 Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA. 3 Université Bordeaux 1, CNRS, UMR 5218, 33405 Talence, France. 4 Center for High Technology Materials, University of New Mexico, Albuquerque, NM, United States. University of Wisconsin-Madison, Madison, WS, United States. 6 Department of Chemical and Nuclear Engineering, University of New Mexico Albuquerque, NM, United States. 7 Center for Micro- Engineered Materials, University of New Mexico, Albuquerque, NM, United States. * Corresponding author email address: krishna.53@osu.edu 1

Figure S1 AFM images and the corresponding height profiles evaluated from statistical analysis of the AFM images, and histograms of (a-b) SiO2/p + Si, (d-e) GOI, and (g-h) Ge NM/SiO2/p + Si substrates before the graphene transfer. (c,f, i) The histogram of the height measurements along with the RMS roughness of the AFM profiles. Number of events was corrected for a linear off set. 2

Figure S2 (a) Optical micrograph of scanned area for Raman analysis. (b) Raman spectra of Gr/SiO2 and Gr/Ge obtained from different spots. (c) The 2D band intensity of the Gr/SiO2 and Gr/Ge. (d) Close-view 2D band intensity of the Gr/SiO2 and Gr/Ge. (e) The G band intensity of the Gr/SiO2 and Gr/Ge. (f) Close-view G band intensity of the Gr/ SiO2 and Gr/ Ge. 3

Figure S3 Transfer characteristics of field effect devices processed on Gr, Gr/Ge, and Ge. Source drain current (Id) versus gate voltage (Vg) recorded at different source-drain voltages and Id versus source-drain voltage (Vds) obtained at room temperature for (a, b) Gr/SiO2/p + Si or (Gr-FET) (c, d) Gr/Ge/SiO2/p + Si or (Gr/Ge-FET) (e, f) Ge/SiO2/p+Si or (Ge-FET). 4

Figure S4 (a) Optical micrograph of the TLM structure patterned on Gr/SiO2/p + Si (b) The closeview image of the TLM structure on Gr/SiO2/p + Si (c) Optical micrograph of the TLM structure patterned on Gr/Ge/SiO2/p + Si. (d) The close-view image of the TLM structure on Gr/Ge/SiO2/p + Si. 5

Figure S5 Measured TLM current and total resistance versus TLM contact distance (a, b) Gr/SiO2 (c, d) Gr/Ge 6

Solving Kirchhoff s law in the equivalent circuit for Metal Insulator Germanium Graphene (MiGeG): Applying the Kirchhoff s law to the equivalent circuit in Figure 7a, the following relationship between gate voltage, channel potential and potential variation due to Vds is established C inv C (Eq. S1) inv VCH x VCH x VCH CTOP 1 CTOP 1 VGS V x e NF 0 CGE CGE where CTOP is the equivalent top gate capacitance of the oxide and germanium stack given by C TOP 1 1 1 C C OX GE 3 e and COX is the oxide capacitance. is defined as v f 2. The charge in the Ge composed of two terms induced by insulating and inversion layers. The zeroes of this second degree polynomial can be calculated and give the channel potential solution V CH x C C 4C V V x e N 2 2 Eq Eq Eq GS F (Eq. S2) Comparing Eq. S2 to the previous model Ref [66], the COX capacitance is replaced by C Eq 1 1 1 C C OX GE C 1 C inv GE. 7

Modeling Ge-FETs in TCAD: In order to extract the Cinv parameter, the Ge-FET structure has been measured and modeled using a commercial TCAD simulator. The calibration procedure has considered the different steps such as Schottky barrier for source and drain contact, adjustment of the Germanium doping and mobility in the inversion layer. The Figure S5 presents the comparison of the measurement and simulation of the transfer characteristics of the Ge-FET. Figure S6 Drain current versus gate voltage at Vds=1 mv for the Ge-FET, measurement (symbols) and TCAD simulation (solid line). 8

Calculation of charge densities in Ge: From the TCAD simulation results, the charge in the inversion layer can be extracted as described in the Figure S6. As expected, a linear approximation of the charge is sufficient to evaluate the charge in the Germanium layer (Cinv=135 µf/m²). Figure S7. Integration of the carrier density (electron and hole) in the Germanium region of the Germanium FET. 9

Extracted electron and hole mobilities, dopings and puddle densities in Gr- and Gr/Ge- FETS: We have considered a finite DOS close to the Dirac point due to disorder from quasilocalized defects. E0 is the energy limit of the disorder beyond which the electron DOS starts to dominate over the disorder DOS (N.M.R. Peres et al. "The transport properties of graphene: An introduction", Reviews of Modern Physics ). Table S1. *The n puddle is a residual carrier density induced by the spatial inhomogeinity within the graphene layer. Instead of the traditional "V" nature of the DOS, we incorporated in the model a DOS curve as shown here below 10

Calculation of charge densities in Gr and Gr/Ge channels: I d (ma) V 1.5x10-3 ds = 1 mv Simulation: Gr Simulation: Gr/Ge 1.0x10-3 5.0x10-4 5x10-4 4x10-4 3x10-4 2x10-4 I d (ma) 0.0 V 1x10-4 Dirac = 10.05 V V Dirac = 60.65 V -100-50 0 50 100 V g (V) Figure S8. Simulated IV characteristics of the Gr-FET and Gr/Ge-FET. V CH = V GS V FB Q CH C OX = V GS V FB At Dirac point V CH = 0 V GS V FB = qn F C eq q ( q2 π(ħv f )² V CH V CH + N F ) C eq = Q C eq Calculating the difference of charge at the Dirac point between the Gr-FET and Gr/Ge-FET, VFB vanishes. Q = Q GrGe Dirac Q Gr Dirac = C eqgrge V GS,DiracGrGe C eqgr V GS,DiracGr Q GrGe Dirac = C eqgrge V GS,Dirac q GrGe Dirac = ε 0 ε r EOT V GS,DiracGrGe GrGe q = 8.85 10 12 3.9 10.05 309 10 9 1.602 10 19 q GrGe Dirac = 7.00 10 11 cm 2 Q Gr Dirac = C eqgr V GS,DiracGr q Gr Dirac = ε 0 ε r EOT V GS,DiracGr Gr q = 8.85 10 12 3.9 60.65 285 10 9 1.602 10 19 q Gr Dirac = 4.58 10 12 cm 2 11

Charge Transfer is computed to be in the order of: q Gr Dirac q GrGe Dirac = 3.88 10 12 cm 2 12