Quad 2-input NND gate FETURES Complies with JEDEC standard no. -1 ESD protection: HBM EI/JESD22-114- exceeds 2000 V MM EI/JESD22-115- exceeds 200 V Specified from 40 to +5 C and 40 to +125 C. DESCRIPTION The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7. The 74HC00/74HCT00 provide the 2-input NND function. QUICK REFERENCE DT GND = 0 V; T amb =25 C; t r =t f = 6 ns. TYPICL SYMBOL PRMETER CONDITIONS 74HC00 74HCT00 t PHL /t PLH propagation delay n, nb to ny C L = 15 pf; V CC = 5 V 7 10 ns C I input capacitance 3.5 3.5 pf C PD power dissipation capacitance per gate notes 1 and 2 22 22 pf s 1. C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+Σ(C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in Volts; N = total load switching outputs; Σ(C L V 2 CC f o ) = sum of the outputs. 2. For 74HC00 the condition is V I = GND to V CC. For 74HCT00 the condition is V I = GND to V CC 1.5 V. FUNCTION TBLE See note 1. 1. H = HIGH voltage level; L = LOW voltage level. INPUT OUTPUT n nb ny L L H L H H H L H H H L 2
Quad 2-input NND gate ORDERING INFORMTION TYPE NUMBER TEMPERTURE RNGE PCKGE PINS PCKGE MTERIL CODE 74HC00N 40 to +125 C 14 DIP14 plastic SOT27-1 74HCT00N 40 to +125 C 14 DIP14 plastic SOT27-1 74HC00D 40 to +125 C 14 SO14 plastic SOT10-1 74HCT00D 40 to +125 C 14 SO14 plastic SOT10-1 74HC00DB 40 to +125 C 14 SSOP14 plastic SOT337-1 74HCT00DB 40 to +125 C 14 SSOP14 plastic SOT337-1 74HC00PW 40 to +125 C 14 TSSOP14 plastic SOT402-1 74HCT00PW 40 to +125 C 14 TSSOP14 plastic SOT402-1 74HC00BQ 40 to +125 C 14 DHVQFN14 plastic SOT762-1 74HCT00BQ 40 to +125 C 14 DHVQFN14 plastic SOT762-1 PINNING PIN SYMBOL DESCRIPTION 1 1 data input 2 1B data input 3 1Y data output 4 2 data input 5 2B data input 6 2Y data output 7 GND ground (0 V) 3Y data output 9 3 data input 10 3B data input 11 4Y data output 12 4 data input 13 4B data input 14 V CC supply voltage handbook, halfpage Fig.1 1 1B 1Y 2 2B 2Y GND 1 2 3 4 5 6 7 00 MN210 14 13 12 11 10 V CC 4B 4 4Y 3B 3 3Y Pin configuration DIP14, SO14 and (T)SSOP14. 9 3
Quad 2-input NND gate RECOMMENDED OPERTING CONDITIONS SYMBOL PRMETER CONDITIONS 74HC00 74HCT00 MIN. TYP. MX. MIN. TYP. MX. V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V V I input voltage 0 V CC 0 V CC V V O output voltage 0 V CC 0 V CC V T amb operating ambient see DC and C 40 +25 +125 40 +25 +125 C temperature characteristics per device t r,t f input rise and fall times V CC = 2.0 V 1000 ns V CC = 4.5 V 6.0 500 6.0 500 ns V CC = 6.0 V 400 ns LIMITING VLUES In accordance with the bsolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PRMETER CONDITIONS MIN. MX. V CC supply voltage 0.5 +7.0 V I IK input diode current V I < 0.5 V or V I >V CC + 0.5 V ±20 m I OK output diode current V O < 0.5 V or V O >V CC + 0.5 V ±20 m I O output source or sink 0.5V<V O <V CC + 0.5 V ±25 m current I CC, I GND V CC or GND current ±50 m T stg storage temperature 65 +150 C P tot power dissipation T amb = 40 to +125 C; note 1 500 mw 1. For DIP14 packages: above 70 C derate linearly with 12 mw/k. For SO14 packages: above 70 C derate linearly with mw/k. For SSOP14 and TSSOP14 packages: above 60 C derate linearly with 5.5 mw/k. For DHVQFN14 packages: above 60 C derate linearly with 4.5 mw/k. 5
Quad 2-input NND gate Type 74HCT00 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL T amb = 40 to +5 C; note 1 PRMETER 1. ll typical values are measured at T amb =25 C. TEST CONDITIONS OTHER V CC (V) MIN. TYP. MX. V IH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 V V IL LOW-level input voltage 4.5 to 5.5 1.2 0. V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ 4.5 4.4 4.5 V I O = 4.0 m 4.5 3.4 4.32 V V OL LOW-level output voltage V I =V IH or V IL I O =20µ 4.5 0 0.1 V I O = 4.0 m 4.5 0.15 0.33 V I LI input leakage current V I =V CC or GND 5.5 ±1.0 µ I OZ 3-state output OFF current V I =V IH or V IL ; 5.5 ±5.0 µ V O =V CC or GND; I CC quiescent supply current V I =V CC or GND; 5.5 20 µ I CC additional supply current per input V I =V CC 2.1 V; 4.5 to 5.5 150 675 µ T amb = 40 to +125 C V IH HIGH-level input voltage 4.5 to 5.5 2.0 V V IL LOW-level input voltage 4.5 to 5.5 0. V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ 4.5 4.4 V I O = 4.0 m 4.5 3.7 V V OL LOW-level output voltage V I =V IH or V IL I O =20µ 4.5 0.1 V I O = 4.0 m 4.5 0.4 V I LI input leakage current V I =V CC or GND 5.5 ±1.0 µ I OZ 3-state output OFF current V I =V IH or V IL ; 5.5 ±10 µ V O =V CC or GND; I CC quiescent supply current V I =V CC or GND; 5.5 40 µ I CC additional supply current per input V I =V CC 2.1 V; 4.5 to 5.5 735 µ
Quad 2-input NND gate PCKGE OUTLINES DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D M E seating plane 2 L 1 Z 14 e b b 1 w M c (e ) 1 M H pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H 4.2 0.51 3.2 0.17 0.02 0.13 1.73 1.13 0.06 0.044 0.53 0.3 0.021 0.015 0.36 0.23 0.014 0.009 19.50 1.55 0.77 0.73 6.4 6.20 0.26 0.24 2.54 7.62 0.1 0.3 3.60 3.05 0.14 0.12.25 7.0 0.32 0.31 10.0.3 0.39 0.33 w 4 0.01 (1) Z max. 2.2 0.07 1. Plastic or metal protrusions of mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC JEDEC JEIT 050G04 MO-001 SC-501-14 EUROPEN PROJECTION 11
Quad 2-input NND gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT10-1 D E X c y H E v M Z 14 Q pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) mm inches max. 1.75 0.10 0.069 0.010 0.004 1 2 3 b p c D (1) E (1) e H (1) E L L p Q v w y Z 1.45 1.25 0.057 0.049 0.01 0.49 0.36 0.019 0.014 0.19 0.0100 0.0075.75.55 0.35 0.34 4.0 3. 0.16 0.15 1.27 6.2 5. 0.244 0.22 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 0.05 1.05 0.041 1.0 0.4 0.039 0.016 0.7 0.6 0.02 0.024 0.1 0.01 0.01 0.004 θ 0.7 0.3 o o 0.02 0 0.012 OUTLINE VERSION SOT10-1 REFERENCES IEC JEDEC JEIT 076E06 MS-012 EUROPEN PROJECTION 12