MM74C73 Dual J-K Flip-Flops with Clear and Preset General Description The MM74C73 dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits cotructed with N- and P-channel enhancement traistors. Each flip-flop has independent J, K, clock and clear inputs and Q and Q outputs. This flip-flop is edge seitive to the clock input and change state on the negative going traition of the clock pulse. Clear or preset is independent of the clock and is accomplished by a low level on the respective input. Features October 1987 Revised January 2004 Supply voltage range: 3 to 15 Tenth power TTL compatible: Drive 2 LPTTL loads High noise immunity: 0.45 CC (typ.) Low power: 50 nw (typ.) Medium speed operation: 10 MHz (typ.) Applicatio Automotive Data terminals Itrumentation Medical electronics Alarm systems Industrial electronics Remote metering Computers MM74C73 Dual J-K Flip-Flops with Clear and Preset Ordering Code: Order Number Package Number Package Description MM74C73N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Truth Table t n t n+1 J K Q 0 0 Q n 0 1 0 1 0 1 1 1 Q n Preset Clear Q n Q n 0 0 0 0 0 1 1 0 1 0 0 1 Note: A logic 0 on clear sets Q to logic 0. Top iew 1 1 Q n Q n (Note 1) (Note 1) t n = bit time before clock pulse t n+1 = bit time after clock pulse Note 1: No change in output from previous state 2004 Fairchild Semiconductor Corporation DS005884 www.fairchildsemi.com
MM74C73 Logic Diagrams Tramission Gate www.fairchildsemi.com 2
Absolute Maximum Ratings(Note 2) oltage at Any Pin 0.3 to CC + 0.3 Operating Temperature Range 55 C to +125 C Storage Temperature 65 C to +150 C Power Dissipation Dual-In-Line 700 mw Small Outline 500 mw Lead Temperature (Soldering, 10 seconds) 260 C Operating CC Range +3 to 15 CC (Max) 18 Note 2: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditio for actual device operation. MM74C73 DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditio Min Typ Max Units CMOS TO CMOS IN(1) Logical 1 Input oltage CC = 5 3.5 CC = 10 8 IN(0) Logical 0 Input oltage CC = 5 1.5 CC = 10 2 OUT(1) Logical 1 Output oltage CC = 5 4.5 CC = 10 9 OUT(0) Logical 0 Output oltage CC = 5 0.5 CC = 10 1 I IN(1) Logical 1 Input Current CC = 15 1 µa I IN(0) Logical 0 Input Current CC = 15 1 µa I CC Supply Current CC = 15 0.050 60 µa LOW POWER TTL TO CMOS INTERFACE IN(1) Logical 1 Input oltage CC = 4.75 CC 1.5 IN(0) Logical 0 Input oltage CC = 4.75 0.8 OUT(1) Logical 1 Output oltage CC = 4.75, I O = 360 µa 2.4 OUT(0) Logical 0 Output oltage CC = 4.75, I O = 360 µa 0.4 OUTPUT DRIE (See Family Characteristics Data Sheet) (Short Circuit Current) I SOURCE Output Source Current CC = 5, IN(0) = 0 T A = 25 C, OUT = 0 1.75 ma I SOURCE Output Source Current CC = 10, IN(0) = 0 T A = 25 C, OUT = 0 8 ma I SINK Output Sink Current CC = 5, IN(1) = 5 T A = 25 C, OUT = CC 1.75 ma I SINK Output Sink Current CC = 10, IN(1) = 10 T A = 25 C, OUT = CC 8 ma 3 www.fairchildsemi.com
MM74C73 AC Electrical Characteristics (Note 3) T A = 25 C, C L = 50 pf, unless otherwise noted Symbol Parameter Conditio Min Typ Max Units C IN Input Capacitance Any Input 5 pf t pd0, t pd1 Propagation Delay Time to a CC = 5 180 300 Logical 0 or Logical 1 from CC = 10 70 110 Clock to Q or Q t pd0 Propagation Delay Time to a CC = 5 200 300 Logical 0 from Preset or Clear CC = 10 80 130 t pd Propagation Delay Time to a CC = 5 200 300 Logical 1 from Preset or Clear CC = 10 80 130 t S Time Prior to Clock Pulse that CC = 5 110 175 Data must be Present CC = 10 45 70 t H Time after Clock Pulse that J CC = 5 40 0 and K must be Held CC = 10 20 0 t PW Minimum Clock Pulse Width CC = 5 120 190 t WL = t WH CC = 10 50 80 t PW Minimum Preset and Clear CC = 5 90 130 Pulse Width CC = 10 40 60 t MAX Maximum Toggle Frequency CC = 5 2.5 4 CC = 10 7 11 MHz t r, t f Clock Pulse Rise and Fall Time CC = 5 15 CC = 10 5 µs Note 3: AC Parameters are guaranteed by DC correlated testing. www.fairchildsemi.com 4
AC Test Circuit Switching Time Waveforms CMOS to CMOS MM74C73 Typical Applicatio t r = t f = 20 Ripple Binary Counters Shift Registers 74C Compatibility Guaranteed Noise Margin as a Function of CC 5 www.fairchildsemi.com
MM74C73 Dual J-K Flip-Flops with Clear and Preset Physical Dimeio inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com