Review EECS 150 - Components and Design Techniques for Digital Systems Lec 06 Minimizing Boolean Logic 9/16-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150 9/16/04 UCB EECS150 D. Culler Fa04 1 Combinational logic Truth Tables vs Boolean Expressions vs Gates Minimal Operators And / Or / Not, NAND, NOR New Friends XOR, EQ, Full Adder Boolean Algebra +, *, ~, assoc, comm, distr.,. Manipulating Expressions and Circuits Proofs: Term rewriting & Exhaustive Enumeration Simplifications De Morgan s Law Duality Canonical and minimal forms Sum of products Product of sums 9/16/04 UCB EECS150 D. Culler Fa04 2 Review: Relationship Among Representations * Theorem: Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AND, OR, NOT. unique? Truth Table not unique Boolean Expression [convenient for manipulation] gate representation (schematic) 9/16/04 UCB EECS150 D. Culler Fa04 3? [close to implementaton] How do we convert from one to the other? Optimizations? not unique Review: Canonical Forms Standard form for a Boolean expression - unique algebraic expression directly from a true table (TT) description. Two Types: * Sum of Products (SOP) * Product of Sums (POS) Sum of Products (disjunctive normal form, minterm expansion). Example: minterms a b c f f a b c 0 0 0 0 1 a b c 0 0 1 0 1 a bc 0 1 0 0 1 a bc 0 1 1 1 0 ab c 1 0 0 1 0 ab c 1 0 1 1 0 abc 1 1 0 1 0 abc 1 1 1 1 0 One product (and) term for each 1 in f: f = a bc + ab c + ab c +abc +abc f = a b c + a b c + a bc 9/16/04 UCB EECS150 D. Culler Fa04 4 Review: Sum of Products (cont.) Canonical Forms are usually not minimal: Our Example: f = a bc + ab c + ab c + abc +abc (xy + xy = x) = a bc + ab + ab = a bc + a (x y + x = y + x) = a + bc f = a b c + a b c + a bc = a b + a bc = a ( b + bc ) = a ( b + c ) = a b + a c 9/16/04 UCB EECS150 D. Culler Fa04 5 Review: Canonical Forms Product of Sums (conjunctive normal form, maxterm expansion). Example: maxterms a b c f f a+b+c 0 0 0 0 1 a+b+c 0 0 1 0 1 a+b +c 0 1 0 0 1 a+b +c 0 1 1 1 0 a +b+c 1 0 0 1 0 a +b+c 1 0 1 1 0 a +b +c 1 1 0 1 0 a +b +c 1 1 1 1 0 One sum (or) term for each 0 in f: f = (a+b+c)(a+b+c )(a+b +c) f = (a+b +c )(a +b+c)(a +b+c ) (a +b +c)(a+b+c ) Mapping from SOP to POS (or POS to SOP): Derive truth table then proceed. 9/16/04 UCB EECS150 D. Culler Fa04 6
ncompletely specified functions Example: binary coded decimal increment by 1 BCD digits encode decimal digits 0 9 in bit patterns 0000 1001 %&!" # # $ 9/16/04 UCB EECS150 D. Culler Fa04 Outline Review De Morgan s to transform SofP into simple 2-level forms Uniting Law to reduce SofP N-cube perspective Announcements Karnaugh Maps Examples Reduction Algorithm 9/16/04 UCB EECS150 D. Culler Fa04 8 Putting DeMorgan s to work Transformation to Simple Gates DeMorgan s Law: (a + b) = a b (a b) = a + b a + b = (a b ) (a b) = (a + b ) = = = = Sum of Products nvolution: x = (x ) push bubbles or introduce in pairs or remove pairs. = De Morgans 9/16/04 UCB EECS150 D. Culler Fa04 9 9/16/04 UCB EECS150 D. Culler Fa04 10 mplementations of Two-level Logic Sum-of-products AND gates to form product terms (minterms) OR gate to form sum Two-level Logic using NAND Gates Replace minterm AND gates with NAND gates Place compensating inversion at inputs of OR gate Product-of-sums OR gates to form sum terms (maxterms) AND gates to form product 9/16/04 UCB EECS150 D. Culler Fa04 11 9/16/04 UCB EECS150 D. Culler Fa04 12
Two-level Logic using NAND Gates OR gate with inverted inputs is a NAND gate de Morgan's: A'+ B'= (A B)' Two-level NAND-NAND network nverted inputs are not counted n a typical circuit, inversion is done once and signal distributed Two-level Logic using NOR Gates Replace maxterm OR gates with NOR gates Place compensating inversion at inputs of AND gate 9/16/04 UCB EECS150 D. Culler Fa04 13 9/16/04 UCB EECS150 D. Culler Fa04 14 Two-level Logic using NOR Gates AND gate with inverted inputs is a NOR gate de Morgan's: A' B'= (A + B)' Two-level NOR-NOR network nverted inputs are not counted n a typical circuit, inversion is done once and signal distributed The Uniting Theorem Key tool to simplification: A (B'+ B) = A Essence of simplification of two-level logic Find two element subsets of the ON-set where only one variable changes its value this single varying variable can be eliminated and a single product term used to represent both elements () * )% *& ) # ' # ' ' # 9/16/04 UCB EECS150 D. Culler Fa04 15 9/16/04 UCB EECS150 D. Culler Fa04 16 Boolean cubes Visual technique for identifying when the uniting theorem can be applied n input variables = n-dimensional "cube Neighbors address differs by one bit flip 9/16/04 UCB EECS150 D. Culler Fa04 1 Mapping truth tables onto Boolean cubes Uniting theorem combines two "faces" of a cube into a larger "face" Example: +, ) + (()# - ) ' $%& # $%& '! 9/16/04 UCB EECS150 D. Culler Fa04 18
Three variable example Binary full-adder carry-out logic Higher dimensional cubes Sub-cubes of higher dimension than 2 % *& % *& %* & # -- # %+.& ' # - /0 # (%!!&)Σ# %1!2!3!4& # 5 66!# " 66!8# # %&9 - : )** 9/16/04 UCB EECS150 D. Culler Fa04 19 9/16/04 UCB EECS150 D. Culler Fa04 20 m-dimensional cubes in a n- dimensional Boolean space n a 3-cube (three variables): 0-cube, i.e., a single node, yields a term in 3 literals 1-cube, i.e., a line of two nodes, yields a term in 2 literals 2-cube, i.e., a plane of four nodes, yields a term in 1 literal 3-cube, i.e., a cube of eight nodes, yields a constant term "1" n general, m-subcube within an n-cube (m < n) yields a term with n m literals Announcements Homework 2 due Friday Reading: 2.5-2.8 (rest of ch 2) Homework 3 posted 9/16/04 UCB EECS150 D. Culler Fa04 21 9/16/04 UCB EECS150 D. Culler Fa04 22 Karnaugh maps Flat map of Boolean cube Wrap around at edges Hard to draw and visualize for more than 4 dimensions Virtually impossible for more than 6 dimensions Alternative to truth-tables to help visualize adjacencies Guide to applying the uniting theorem On-set elements with only one variable changing value are adjacent unlike the situation in a linear truth-table ( 8 9/16/04 UCB EECS150 D. Culler Fa04 23 Karnaugh maps Numbering scheme based on Gray code e.g., 00, 01, 11, 10 2 n values of n bits where each differs from next by one bit flip» Hamiltonian circuit through n-cube Only a single bit changes in code for adjacent map cells 3 1 8 4 2 8 3 1 4 2 1 2 8 4 3 ; 8 < 9/16/04 UCB EECS150 D. Culler Fa04 24 2 1 8))=
Adjacencies in Karnaugh maps Karnaugh map examples Wrap from first to last column Wrap top row to bottom row F = Cout = f(a,b,c) = Σm(0,4,6,) = 9/16/04 UCB EECS150 D. Culler Fa04 25 # # *== *= -9 ' 9/16/04 UCB EECS150 D. Culler Fa04 26 ** More Karnaugh map examples K-map: 4-variable interactive quiz >%!!&) F(A,B,C,D) = Σm(0,2,3,5,6,,8,10,11,14,15) F = (%!!&)Σ# %!1!2!4& )*== ( # - ' ( %!!&)Σ # %!!8!3& )= *= # # 9 +, %' # ' ' # & 9/16/04 UCB EECS150 D. Culler Fa04 2 9/16/04 UCB EECS150 D. Culler Fa04 28 Karnaugh map: 4-variable example F(A,B,C,D) = Σm(0,2,3,5,6,,8,10,11,14,15) F = *= *== # # 9 +, %' # ' ' # & Karnaugh maps: don t cares f(a,b,c,d) = Σ m(1,3,5,,9) + d(6,12,13) without don't cares» f = = *== 9/16/04 UCB EECS150 D. Culler Fa04 29 9/16/04 UCB EECS150 D. Culler Fa04 30
Karnaugh maps: don t cares Design example: two-bit comparator f(a,b,c,d) = Σ m(1,3,5,,9) + d(6,12,13) f = A'D + B'C'D without don't cares f = with don't cares -9 # 9' # 9,, A: BC >: @9# D ) E A: BC >: ' 1?9 # 8 9/16/04 UCB EECS150 D. Culler Fa04 31 9/16/04 UCB EECS150 D. Culler Fa04 32 Design example: two-bit comparator?# A:?# BC?# >: Design example: two-bit comparator ' # # BC ' ' +. A: ) * * BC ) * ** = >: ) * * Canonical PofS vs minimal? )%" &F %" &, +.# # ' 8# 9 A: >: # %GG& 9/16/04 UCB EECS150 D. Culler Fa04 33 9/16/04 UCB EECS150 D. Culler Fa04 34 Design example: 2x2-bit multiplier @9# H H H1 H; H; H1 H H 1?# 1 9/16/04 UCB EECS150 D. Culler Fa04 35 Design example: 2x2-bit multiplier?# H; H;)?# H?# H1 H1) * H ) * * * 9/16/04 UCB EECS150 D. Culler Fa04 36?# H H )
Design example: BCD increment by 1 Design example: BCD increment by 1 @9# + + + 1 + ; + ; + 1 + + 1?# 1 + ; + 1 + ;)* + 1) * *= + )= = * + ) + + 9/16/04 UCB EECS150 D. Culler Fa04 3 9/16/04 UCB EECS150 D. Culler Fa04 38 Definition of terms for two-level simplification Examples to illustrate terms mplicant Single element of ON-set or DC-set or any group of these elements that can be combined to form a subcube Prime implicant mplicant that can't be combined with another to form a larger subcube Essential prime implicant Prime implicant is essential if it alone covers an element of ON-set Will participate in ALL possible covers of the ON-set DC-set used to form prime implicants but not to make implicant essential Objective: Grow implicant into prime implicants (minimize literals per term) Cover the ON-set with as few prime implicants as possible (minimize number of product terms) 9/16/04 UCB EECS150 D. Culler Fa04 39 2# # J!!!! # # # J1# 3# # J!!!!! # # # J* * 9/16/04 UCB EECS150 D. Culler Fa04 40 Algorithm for two-level simplification Algorithm: minimum sum-of-products expression from a Karnaugh map Step 1: choose an element of the ON-set Step 2: find "maximal" groupings of 1s and Xs adjacent to that element» consider top/bottom row, left/right column, and corner adjacencies» this forms prime implicants (number of elements always a power of 2) Repeat Steps 1 and 2 to find all prime implicants Step 3: revisit the 1s in the K-map» if covered by single prime implicant, it is essential, and participates in final cover» 1s covered by essential prime implicant do not need to be revisited Step 4: if there remain 1s not covered by essential prime implicants» select the smallest number of prime implicants that cover the remaining 1s 9/16/04 UCB EECS150 D. Culler Fa04 41 Algorithm for two-level simplification (example) 9/16/04 UCB EECS150 D. Culler Fa04 42
Summary Boolean Algebra provides framework for logic simplification De Morgans transforms between gate types Uniting to reduce minterms Karnaugh maps provide visual notion of simplifications Algorithm for producing reduced form. Question: are there programmable logic families that are simpler than FPGAs for the canonical forms? 9/16/04 UCB EECS150 D. Culler Fa04 43