A Unified Reversible Design of Binary and Binary Coded Decimal Adder / Subtractor

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 9, Number 22 (2014) pp. 17181-17198 Research India Publications http://www.ripublication.com A Unified Reversible Design of Binary and Binary Coded Decimal Adder / Subtractor 1 Praveena. Mand 2 Dr. Thanushkodi.K 1 Research Scholar, Anna University, Tamilnadu, India praveeias@yahoo. com 2 Director, Akshaya College of Engineering & Technology, Coimbatore, Tamilnadu, India samayamurali@gmail. com Abstract Reversible logic is one of the emerging research areas that have gained greater momentum due to the ability to produce zero power dissipation under ideal conditions. This aspect of reversible logic circuits has found its application in various disciplines like quantum computing, nanotechnology, optical technology and low power CMOS designs. This paper presents a novel reversible logic implementation of unified Binary and BCD adder/subtractor and this single circuit proposed can perform four operations namely Binary addition, Binary subtraction, BCD addition and BCD subtraction based on the input given to the circuit. The circuit is compared with different BCD adder/subtractor circuits in terms of gate count, constant inputs, garbage outputs and delay. Keywords-Reversible logic, Quantum computing, Nanotechnology, Garbage output and Constant input. 1. INTRODUCTION The highgrowth of integration of present day ICs increases power density enormously. This inturn poses serious threats in terms of heat generation and much care has to be taken to dissipate this heat. According to Landauer[1, 2], the energy dissipation of KTln2 joules occurs for every bit of information where K is Boltzmann s constant of 1. 38 10-23 J/K and T is the absolute temperature of the environment. Inthis context reversible logics emerge which have almost zero energy dissipation [3]. A reversible circuit is one which does not lose any information when compared with the irreversible logic circuit or conventional combinational logic Paper Code:27915 - IJAER

17182 Praveena. M and Dr. Thanushkodi. K circuits. In other words irreversible circuit can be converted to reversible by saving all the information which it would discard otherwise. Therefore the attention towards reversible concept has reached greater heights in recent years especially in areas of quantum computing. In computer systems, the most common numbering system that is followed isbinary numbers. However there are computers that use decimal numbering system rather than binary number system. Such systems have found its importance in commercial, financial and internet based applications. Although binary arithmetic is used in wide variety of applications there is always an assumption that decimal arithmetic is better for the financial applications. Recognizing the decimal arithmetic, the specifications of decimal floating point arithmetic is added in the draft revisionof IEEE P754 [4]. Moreover floating point numbers are represented with desired precision in decimal format rather than binary representations[5]. Inspite of its high level of accuracy the decimal arithmetic is 100 to 1000 times slower than binary arithmetic. These pros and cons have urged the hardware designers to add decimal and binary arithmetic unit in CPU to perform arithmetic calculations. At present there are number of reversible architectures which performs a single function i. e. BCD addition[6, 7, 8, 9, 10], BCD subtraction [11], Binary addition[12] and Binary subtraction[13] and there are architectures which perform two functions i. e. BCD addition /subtraction[14, 15, 16, 17] whereas our proposed design performs four different operations in a single circuit. Thereforea narrative design for unified binary and BCD addition/ subtraction is proposed in this paper. 2. Prior Works There are several research works attempted for BCD addition and subtraction. In [14]design on BCD adder / subtractor used 9's complement circuit and reversible BCD full adder. However the circuit is prone to error when subtrahend is greater than the minuend. To realize the correct decimal output, the actual output has to be again 9's complemented which is realized at the last stage and this produces incorrect values in case of addition operation. In [15] design of BCD adder/subtractor using reversible logic used Nines Complement Gate (NCG) for nines complement conversion of the subtrahend. The advantage of [15]design is that it produces no garbage output and requires no constant input. In addition a novel BSCL gate is proposed for decimal correction. Though the BCD adder/subtractor proposed by [15] require minimum number of gates and produces no garbage output it suffers from the drawback that an extension for n bit addition/subtraction is not possible. Particularlyfor n>4 with carry=1, the BSCL gate adds1 to both the 4 bit numbers and produces error at the output. In a design of unified architecture for BCD addition/subtraction [16] used FG to realize nines complement of binary input and HNG to realize 4 bit addition operation. The complementer circuit is designed using 4 FG. The addition/subtraction output of the inputs are realized using reversible 2:1 multiplexers constructed using TKS gates. The novelty of the design is that it can be extended for n digit decimal addition/subtraction with ease.

A Unified Reversible Design of Binary and Binary Coded Decimal 17183 In [17] design for BCD addition/subtraction the NCG gate is used to obtain nines complement of the subtrahend. The advantage of this design is that it is optimized interms of all the parameters and can be extended to n bit BCD addition /subtraction. Therefore though there are different architectures for addition and subtraction there arises a urge for a unified architecture of binary and BCD addition/subtraction in ALU s which is attempted in this paper. 3. BACKGROUND OF REVERSIBLE LOGIC GATES USED IN THE PROPOSED DESIGN The logic representation and operation of the reversible gates used in proposed arithmetic units are briefed as follows. 3. 1. Proposed Design of theptm Gate The 3 3 reversible PTM gate as in Figure 1(a) is used for generating carry and sign bit of the output [18]. The third input (C) of PTM gate is kept constant as 1 and 0. The gate produces 2 garbage outputs along with the result. The quantum circuitof the PTM gate is implemented using 2x2 quantum gates as shown in Figure1(b) and it is found that the quantum cost of PTM gate is 11. (a) (b) Figure 1 PTM gate (a) Logic diagram (b) Quantum circuit 3. 2. HN Gate The HN gate is a 4 * 4 reversible gate [19] used to realize three bit addition. The gate width of HN gate is found to be 4. The gate requires one constant input, 2 garbage outputs and thus has a quantum cost of 6.

17184 Praveena. M and Dr. Thanushkodi. K 3. 3. BVF gate and FG The 4*4 BVFgate [20] is used in the design of 16 * 16 copying circuit to be used in the proposed binary/bcd adder/subtractor. Quantum implementation of BVF gate is shown in Figure 2. (a) (b) Figure 2 BVF gate (a) Logic diagram(b) Quantum implementation The function of FGis the same function as that of BVF gate except that it has a single XOR gate. It is seen from Figure 2 that the quantum cost of BVF gate is 2. 3. 4. R-Comp Gate and R-o/p Gate The logic representation and quantum diagram of R-comp and R-o/p gates [21] used in binary comparator are shown in Figure 3 and Figure 4 respectively. (a)

A Unified Reversible Design of Binary and Binary Coded Decimal 17185 (b) Figure 3 R-Comp gate (a) Logic representation (b) Quantum implementation (a) (b) Figure 4 R-o/p gate (a) Logic representation (b) Quantum diagram Logic representation and quantum diagram of TR gate used in R-comp and R- o/p is shown in Figure 5. (a)

17186 Praveena. M and Dr. Thanushkodi. K (b) Figure 5 TR gate (a) Logic diagram (b) Quantum representation 3. 5. SCL gate The SCL gate [22] is used for the detection of overflow of output. SCL gate produces a logic 1 if the output exceeds 9 and vice versa. Quantum representation of SCL gate is shown in Figure 6. Note that from Figure 6 the quantum cost of SCL is 7. (a) (b) Figure 6 SCL gate (a) Logic diagram (b) Quantum representation 4. PROPOSED ARCHITECTURE The proposed architecture for binary and BCD addition/subtraction consists of copying circuit, binary comparator, reversible multiplexer,two s complement circuit, 4 bit reversible adder, BCD detection & correction circuit and FG&PTM gates and is shown in Figure 7.

A Unified Reversible Design of Binary and Binary Coded Decimal 17187 Figure 7 Proposed binary/bcd adder/subtractor A brief description of the blocks used in the proposed architecture are as follows.

17188 Praveena. M and Dr. Thanushkodi. K 4. 1. Copying Circuit The proposed binary/decimal adder/subtractor consists of two copying circuits. The proposed copying circuit-1 is designed using 4*4 BVF gateand consists of 8 BVF gates to produce 3 copies of inputs A & B as shown in Figure 8. 2 copies of A and B are given as input to two multiplexers and the third copy is given as an input to reversible comparator. Figure 8 Copying circuit-1 In the next design i. e copying circuit-2 shown in Figure 9[23], two BVF gates and one FG gate are used. This circuit is used for duplicating 4 bit adder output and for copying the carry bit of the adder.

A Unified Reversible Design of Binary and Binary Coded Decimal 17189 Figure 9 Copying circuit-2 4. 2. Binary comparator The binary comparator [21]used in the proposed binary/bcd adder/subtractorfor comparing two binary inputs uses three R-Comp gates and one R-o/p gate and is shown in Figure 10. For the case of 4 bit inputs A (a 3 a 2 a 1 a 0 ) and B (b 3 b 2 b 1 b 0 ), the first stage comparator does comparison of two consecutive bits using a pair of R-Comp gates. The output of the R-Comp gates is fed to another R-Comp gate at the second stage. The output of the second stage R-comp gate is fed to reversible R-op gate to produce the final result. The output of R-op gate will be 010 for a>b, 001 for a<b and 100 for a=b. Since the quantum cost of R-comp gate is 18 and reversible output circuitry is 9, the 4 bit binary comparator has a quantum cost of 63 (3*18+9).

17190 Praveena. M and Dr. Thanushkodi. K Figure 10 Binary comparator 4. 3. BCD Detection and Correction Circuit BCD detection and correction circuit used in the proposed binary/bcd adder/subtractor design consists of SCL gate, FG gate, Peres gate and HNG [19] and is shown in Figure 11. SCL gate is used for the detection of overflow and FG, PG and HNG are used to convert the output to equivalent decimal based on the control signal from SCL gate. Figure 11 BCD detection and correction circuit

A Unified Reversible Design of Binary and Binary Coded Decimal 17191 Since the quantum cost of FG, PG and HNG are 1, 4 and 6 respectively, the quantum cost of BCD detection and correction circuit counts to 18. 4. 4. Proposed ReversibleTwo s Complement Circuit The two s complement circuit used in the proposed design for binary & BCD addition/subtraction uses a 4 bit reversible adder, designed using HNG. The architecture of two s complement circuit is shown in Figure 12. Since subtraction operation is similar to adding two s complement of subtrahend with the other input, two s complement circuit is used to convert the binary bits of subtrahend to equivalent 2s complement form. To achieve this, two s complement circuit uses a NOT gate and a reversible adder. NOT gate is used to find ones complement of the input and reversible adder is used to add one to the NOT gate output to generate equivalent two s complement value. Since the quantum cost of NOT gate is 1 and HNG is 6, the quantum costoftwo s complement circuit counts to 28 (4*6+4). Figure 12 Two s complement circuit 4. 5. Reversible Multiplexer The proposed design uses four 2:1 reversible multiplexers constructed using FR gate [23]. FR gate is a 3*3 reversible gate used to perform AND and OR operations and in the construction of multiplexer. The AND-OR logic and the multiplexed output are obtained at R and at Q pins respectively. 4. 6 Principle of Operation The design uses two s complement method [24] for both binary and BCD subtraction. The main criterion to be noted is that the magnitude of subtrahend must be always smaller than the minuend. To satisfy this criterion the inputs A and B are passed through a 4 bit binary comparator block [21] to find whether A> B or A<B or A=B. The comparator output is used as the select signal for the multiplexers. The output of

17192 Praveena. M and Dr. Thanushkodi. K multiplexers will be such that the magnitude of minuend(reversible multiplexer 1 output) is greater than the subtrahend (reversible multiplexer 2 output). Table 1 shows the outputs of two reversible multiplexers based on the control input from comparator. Table 1 Output of reversible multiplexers Condition Output of Reversible Multiplexer1 Output of Reversible Multiplexer2 A>B (010) A B A<B (001) B A A=B (100) B B The output of the reversible multiplexer-2 is passed through a two s complement circuit controlled by Add/Sub output of FG. For addition operation, Add/Sub is equal to zero and the bits at the reversible multiplexer-2 output will be passed as such to the reversible adder. In case of subtraction operation, Add/Sub is equal to one and the bits at the reversible multiplexer-2 output will be two s complemented and passed to the reversible adder. The other input to the reversible adder is the output from reversible multiplexer-1. The output of the reversible adder is fed to copying circuit-2 to produce two copies. One of the outputs of copying circuit-2 is fed to a BCD detection and correction circuit to produce the decimal equivalent. The output of BCD detection and correction circuit and other output of copying circuit-2 are passed through reversible multiplexer-3. The control signal for the reversible multiplexer-3 is a BIN/BCD input. Based on the BIN/BCD input either the binary or decimal equivalent of reversible adder output will be passed out. PTM gates are used to generate the carry output. The input to one of the PTM gate is the output of BCD detection/correction circuit and Add/Sub control input, and for the second PTM gate the inputs are copying circuit output and Add/Sub control signal. To detect sign bit, a separate PTM gate is used whose input is the output of binary comparator and Add/Sub bit. The illustration of the above approach is shown through following example. A (22) : 00100010 B(19) : 00011001 Output of 8 bit Binary comparator 1: : 010 Output of Reversible Multiplexer 1 : 0010 0010 Output of Reversible Multiplexer 2 : 0001 1001 Add/Sub, Bin/BCD :1, 1 Output of 4 bit Binary comparator 2 : 001 A : 00100010 Two s complement of B : 11100111 ------------------ : 0000 1001 ------------------ Output of BCD detectionand correction circuit : 00000011 Final output : 0000 0011

A Unified Reversible Design of Binary and Binary Coded Decimal 17193 The above example results reveal that the proposed binary/bcd adder/subtractor can be extended for higher bitwidth addition/subtractionwith ease. The algorithm for the proposed binary and BCD adder/ subtractor for n = 4 is given below Let A = (A 3, A 2, A 1, A 0 ) and B = (B 3, B 2, B 1, B 0 ) be the two inputs. ControlInput bits: Add/Sub, Bin/BCD Carry bits: C, C in andc out Output bits: I(I 3, I 2, I 1, I 0 )-Intermediate output S(S 3, S 2, S 1, S 0 )and D(D 3, D 2, D 1, D 0 )-Final outputs Step 1: Compare A and B. If B is greater than A swap A and B. Step 2: If Add/Sub = 0 then B 4 B 3 B 2 B 1 = B 4 B 3 B 2 B 1 Else B 4 B 3 B 2 B 1 = ( 4 3 2 1 ) + 1 Step 3:Addition of inputs A and B For (i = 1 to 4) { S i =(A i XOR B i XOR C i-1 ) C i = (A i XOR B i ) C i-1 XOR A i B i i = i + 1 } Step 4: Carry bit computation using PTM gate If Add/Sub = 0 and C 4 = 1 then C out = 1 Else if Add/Sub = 0 and C 4 = 0 then C out = 0 Elseif Add/sub = 1 and C 4 = 0 then C out = 0 Else Add/sub = 1 and C 4 = 1 then C out = 0 Step 5: BCD overflow detection and correction If I (I 3, I 2, I 1, I 0 )>1001then S (S 3, S 2, S 1, S 0 ) = (I 3, I 2, I 1, I 0 ) + 0110 Else S (S 3, S 2, S 1, S 0 ) = I (I 3, I 2, I 1, I 0 ) Step 6: Sign bit computation IfAdd/Sub = 0 and R = 0 then S = 0 Else if Add/Sub = 0 and R = 1 then S = 0 Else if

17194 Praveena. M and Dr. Thanushkodi. K Add/Sub = 1 and R = 0 then S = 0 Else Add/Sub = 1 and R = 1 then S = 1 End 5. RESULTS AND DISCUSSION The proposed reversible binary and BCD adder/subtractor is designed using structuralvhdl to produce gate level netlist and synthesized using Xilinx software. Experimental evaluation of the proposed binary and BCD adder/subtractor design is done in terms of no. of reversible gates, no. of constant inputs, no. of garbage output and quantum costand are shown in Table 2. Note that from Table 2 that all the blocks used in the proposed design has constant inputs except reversible multiplexers.the total count of constant inputs of the proposed design is found to be 53 with copying circuit-1 contributing 30%. Also note that the garbage output of the proposed design is 55 with binary comparatorcontributing a maximum of 32. 7%., whereas copying circuit-1, copying circuit-2 and FG do not produce any garbage outputs. Quantum cost defined as the number of primitive reversible gates needed for the reversible circuit design, of the proposed design is found to be 270. Table 2 Analysis of proposed binary and BCD adder/subtractor Parameters Gate count Constant input Garbage output Quantum Cost Blocks Binary comparator 23 13 18 63 Reversible Multiplexer1, 2, 3 13-13 75 Copying Circuit 1 8 16-16 Copying Circuit 2 3 5-5 Two s complement circuit 8 7 8 28 4-bit reversible adder 4 4 8 24 BCD detection and correction 4 2 2 18 circuit PTM and FG (3+4) (3+3) (6+0) (33+4) Total 70 53 55 270 The quantum cost of reversible multiplexer is 75 and it is a significant contributor contributing about 30% of the total. An evaluation of proposed reversible binary and BCD adder/subtractor against several state-of-the-art approaches, whose design structure represent similar topologies and circuits targeted for binary and decimal arithmetic is done. Evaluation results in terms of gate count, number of constant inputs, number of garbage outputs and delay are shown in Table 3. In calculating no.ofconstant inputs and no. of garbage outputs, the constant inputs and garbage outputs of individual gates are found

A Unified Reversible Design of Binary and Binary Coded Decimal 17195 and added to find the garbage outputs and constant inputs of the design. Similarly to calculate delay, the delay of gates in the critical path are estimated and summed to give worst case delay of the entire design. Using the above approach, the delay of the proposed binary/bcd adder/subtractor is calculated asfollows. (Symbol represents unit delay). Total delay = 2 BVF + 15 (TR and FG) + FG + 4 FRG + 5 (HNG and NOT) + 4 HNG + BVF + 4 (SCL, Peres, HNG and FG)+ PTM+ 5 FRG =42 gate delays (assuming each gate has equal unitdelay). Table 3 Analysis of gate count, garbage output, constant input and delay of proposed binary/bcd adder/subtractor and previous reversible designs Reversible Designs Gate Garbage Constant Delay Applicability Count Output Input [21] 36 37 25 26 n bit BCD addition and subtraction [22] 7 9 5 7 only 4 bit BCD addition and subtraction [23] 26 12 8 24 n bit BCD addition and subtraction. Produce error at the output. [24] 24 28 24 23 n bit BCD addition and subtraction Proposed binary and 70 55 53 42 n bit binaryand BCD BCD addition and adder/subtractor subtraction A plot of delay per unit gate count of the proposed and approaches used for comparison is shown in Figure 13.

17196 Praveena. M and Dr. Thanushkodi. K Delay/gate count 1.2 1 0.8 0.6 0.4 0.2 Rajmohan et al(2011) Rashmi et al(2011) Mohammadi et al (2009) Proposed BCD adder/subtractor 0 Reversible design Proposed binary and BCD adder/subtractor Figure 13 Plot of delay per gate count of proposed binary/bcd adder/subtractor and previous appraoches It is seen from Figure 13 that the delay perunit gate count of the proposed binary/bcd adder/subtractor is significantly low compared to approaches used for comparison. This reveals that the proposed architecture optimizes delay and area significantly better. 6. CONCLUSION In this paper a novel design for unified binary and BCD adder-subtractor using reversible logic is proposed. The proposed approach uses efficient reversible 4 bit adder and BCD detection and correction circuit to realize the logic. Experimental evaluations using simulations revealed the proposed approach is able to incorporate four different logics within the same circuit and able to operate with minimal delay per total gate count. This inturn reveals the suitability of proposed approach for low power high speed quantum applications. As a further work the carry look-ahead logic can be implemented in the reversible addition stages to optimize delay further with a little expense in area. Moreover in future this architecture can stand as a base for developing reversible arithmetic and logic unit (ALU) by optimizing all the comparative parameters.

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