Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 7 Interconnections 1: wire resistance, capacitance, and inductance guntzel@inf.ufsc.br
Interconnections Introduction As CMOS technology scales down Transistors become smaller: chips become denser gate delays reduce Mean wire length increases Wire parasitic effects do not scale with the same factor as transistors: Capacitances Resistances Inductances Slide 7.2
Interconnections Consequences of Parasitics As CMOS technology scales to deep submicron, wire parasitics: Increase contribution to propagation delay Increase contribution on energy dissipation and the power distribution Introduces extra noise, affecting circuit reliability Slide 7.3
Interconnections Wire Delay vs. Gate Delay Source: E.B. Friedman, 1 st NOC Workshop, DATE 2006. Wire delays became dominant over gate delays in 0.35µm technologies Slide 7.4
Wire Geometry Line pitch = W+S Aspect Ratio: AR= H/W Old processes: AR <<1 Submicron processes: AR ~2 Interconnections W S L Current flow H t di dielectric substrate Slide 7.5
A First Glance Interconnections M6 M5 M4 Via M1 Isolation M3 M2 Transistor Slide 7.6
A First Glance Interconnections schematics physical Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.7
Interconnections Wire Models All-inclusive model Capacitance-only Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.8
Interconnections Wire Models - Simplifying All-inclusive model Capacitance-only Inductive effects can be ignored if resistance of wire is substantial enough (e.g., long aluminum wires with small cross section) A capacitance-only model can be used when wires are short, the cross section of the wire is large, or the interconnect material has low resistivity Interwire capacitance can be ignored when the separation between neighboring wire is large, or when the wires only run together for a short distance Slide 7.9
Interconnections Layer Stack AMS 0.35µm has 3 metal layers M1 used for intra-cell routing M2 and M3 used for local and global routing (each one in one direction) Contemporary (submicron) technologies have 6 to10 metal layers: M1: thin, narrow, used for high density cells Mid layers: thicker and wider (density vs. speed) Top layers: thickest, used for V DD, Gnd, Clock Slide 7.10
Wire Lenght Interconnections Some global signals, such as clocks, are distributed all over the chip and may be significantly long For die sizes between 1 cm and 2 cm, wires can reach a length of 10 cm Slide 7.11
Wire Resistance Interconnections Ohm s law + V - I R Defined by manufacturer W Material property Height (thickness) : sheet resistance, in Ω/ (ohms per square) Defined by the designer L Current flow Obs.: H R1 = R2 Slide 7.12
Wire Resistance Interconnections Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.13
Wire Resistance Interconnections W L Top view Metal Metal Polysilicon P substrate Ex: Poly-resistor : sheet resistance : head resistance Slide 7.14
Wire Resistance Interconnections Sheet resistance values for a typical 0.25µm CMOS process Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.15
Wire Resistance Interconnections Consider an aluminum wire with L=10cm and W=1µm, routed on the first aluminum layer. Assuming a sheet resistance of 0.075Ω/, calculate its total resistance. R wire = 0.075 Ω/ x (0.1 x 10 6 µm) / (1 µm) = 7.5 kω Consider that this wire were in poly, instead, which sheet resistance is175 Ω/. Which would be the wire resistance under such circumstances? R wire = 175 Ω/ x (0.1 x 10 6 µm) / (1 µm) = 17.5 MΩ Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.16
Wire Resistance Interconnections MOS Transistor with Polycide Gate Silicide Polysilicon SiO 2 n + n + Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.17
Interconnections Simulation Why using circuit simulators? Designs can be quickly evaluated without (sometimes very expensive) fabrication. After design has been evaluated you can prototype it before mass production. A circuit simulator computes the response of the circuit to a particular stimulus. The simulator formulates the circuit equations and then numerically solves them. Slide 7.18
Interconnections Simulation Types of analyses: DC/DC sweep: Both stimuli and responses do not vary with time Transient: Responses vary with time AC/Noise: also called small-signal analysis, it computes the sinusoidal steady-state response Slide 7.19
Simulation What are the input data? Interconnections Device Type (R, C, L, current sources, voltage sources, diodes, transistors) Device models/parameters/ dimensions How devices are connected Some circuit simulators: SPICE, PSPICE, HSPICE (Synopsys), Spectre (cadence), Smash, SpiceOpus (free!),. SpiceOpus Page: http://www.spiceopus.si/ Slide 7.20
Interconnections Simulation Use SpiceOpus to determine the (dc) I-V characteristic of a 1 kω resistor. I + V - R V=RI I V 0 + - r 1 Node 1 Node 0 Step 1: Create File resistortest.cir in the notepad * this is resistortest.cir file v0 1 0 dc 10V r1 1 0 1k.end Step 2: run SpiceOpus with the following commands SpiceOpus (c) 1 -> source resistortest.cir SpiceOpus (c) 2 -> dc v0-1v 1V 2mV SpiceOpus (c) 3 -> setplot dc1 SpiceOpus (c) 4 -> plot i(v0) xlabel v(1) ylabel current[a] SpiceOpus (c) 5 -> plot -1000*i(v0) xlabel v(1)[v] ylabel current[ma] Slide 7.21
Interconnections Simulation I V 0 + - Node 1 r 1 = 1 kω Node 0 Slide 7.22
Interconnections Simulation Use SpiceOpus to determine the (dc) I-V characteristic of the circuit below r 3 I V + 0 - r 1 r 2 r 1 = r 2 =1 kω r 3 = 0.5 kω 1V V 0-1V SpiceOpus (c) 5 -> source currentdivider.cir SpiceOpus (c) 6 -> dc v0-1 1 5m SpiceOpus (c) 7 -> setplot dc SpiceOpus (c) 8 -> plot 1000*i(v1) xlabel v(3)[v] ylabel current[ma] Slide 7.23
Wire Capacitance Interconnections Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.24
Interconnections Wire Capacitance The parallel plate capacitor Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV Charge separation in a parallel-plate capacitor causes an internal electric field. A polarized dielectric spacer (orange) reduces the electric field and increases the capacitance. The electric field (force) E between the plates of a parallel plate capacitor is uniform and given by E=V/d Slide 7.25
Wire Capacitance Interconnections W c int = ε di t di WL L Current flow Electrical-field lines H t di dielectric substrate In ICs, dielectric is SiO 2 : ε di = ε ox = 3.9 x ε 0 t di = t ox C ox = ε o /t ox [ff/μm2] is a technology parameter, defined by the Foundry Slide 7.26
Wire Capacitance Permittivity Interconnections : permittivity of free space Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.27
Interconnections Wire Capacitance Fringing Capacitances w=w-h/2 thick oxide c fring e H c p p W substrate c fring e c p p t di capacitance/unit length Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.28
Wire Capacitance Fringing vs. Parallel Plate Interconnections Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.29
Interconnections Wire Capacitance Interwire Capacitances Crosstalk: a signal can affect another nearby signal. Substrate noise coupling Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.30
Interconnections Wire Capacitance Wire Area and Fringe Capacitances for Typical 0.25 µm CMOS Process Bottom plate of the capacitor af/µm 2 af/µm Top plate of the capacitor Area cap. Fringe cap. Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.31
Interconnections Wire Capacitance Interwire Capacitances per unit wire length for different interconnect layers (0.25 µm CMOS Process) Layer Poly Al1 Al2 Al3 Al4 Al5 capacitance 40 95 85 85 85 115 Capacitances expressed in af/µm. Assuming minimally spaced wires. Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 7.32
Wire Capacitance Example: Interconnections Consider an aluminum wire with L=10cm and W=1µm, routed on the first aluminum layer. Calculate its total capacitance by using capacitance values given in slide 7.24. Answer: Total (ground) cap. = area (parallel plate) cap. + fringing cap. Area cap. = 0.1 x 10 6 µm 2 x 30 af/µm 2 = 3 pf Fringing cap. = 2x (0.1 x 10 6 µm) x 40 af/µm = 8 pf Total cap. = 11 pf Slide 7.33
Wire Capacitance Example: Interconnections Suppose now that a second wire is routed alongside the first one, separated by the minimum allowed distance. Determine the couple capacitance by using couple capacitance data given in slide 7.25. Answer: Cint = (0.1 x 10 6 µm) x 95 af/µm = 9.5 pf Slide 7.34
Wire Capacitance Example Cont. Interconnections Interesting to notice that moving the wire to Al4 would lead to the following results: Area cap. = 0.1 x 10 6 µm 2 x 6.5 af/µm 2 = 0.65 pf Fringing cap. = 2x (0.1 x 10 6 µm) x 14 af/µm = 2.8 pf Total (ground) cap. = 3.45 pf Cint = (0.1 x 10 6 µm) x 85 af/µm = 8.5 pf Slide 7.35
Interconnections References Rabaey J.; Chandrakasan A.; Nikolic B. Digital Integrated Circuits: a design perspective., 2 nd Edition, Prentice Hall, USA, 2003. Slide 7.36