High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to cutoff. Circuit during high-to-low transition: V IN (t > 0) = V OH + _ (p-channel MOSFET is cutoff) I Dn v OUT (t) C L = C G + C P The voltage on the load capacitor at t = 0 - was V OH ; since n-channel MOSFET is saturated initially and the input voltage is a constant, the drain current is initially I Dn(sat) for V GS = V +. The high-to-low propagation delay t PHL is (by deþnition) the time required for V OUT to reach V OH / 2: dv OUT ---------------- dt d Q L ÐI Dn( sat) = ---- --------------------- = ---------------------- dt C G + C P C G + C P
Hand Calculation of t PHL The output voltage decreases linearly over 0 < t < t PHL if we assume that the MOSFET remains saturated: v OUT (t) V OH slope = dv OUT / dt V OH / 2 0 t PHL t The high-to-low propagation delay is given by: dv OUT ---------------- dt ( V OH 2) Ð V OH = ----------------------------------------- = t PHL ÐI Dn( sat) ---------------------- C G + C P Solving for the delay: ( C G + C P )( V OH 2) t PHL = --------------------------------------------------------------------------- µ n C ox ( W 2L) n ( V OH Ð V Tn ) 2
Graphical Interpretation The n-channel driver remains saturated throughout the Þrst half of the transition from high-to-low... I D V OUT t = t PHL t = 0 + V IN = V OH V OH t = 0 V IN = 0V V OH 2 0 0 V OH 2 (a) V OH V OUT 0 0 t PHL (b) t note that the characteristics above are not for a square-law MOSFET, which would enter the triode region for V OUT < V OH - V Tn ; the error is not large enough to matter for hand calculations in any case
Low-to-High Propagation Delay t PLH For the low-to-high transition, the n-channel device is cutoff and the p-channel MOSFET is initially saturated and supplying - I Dp(sat) to charge up the gate and parasitic capacitances. V DD V SGp _ + V IN = 0 V - I Dp Therefore, ( C G + C P )( V OH 2) t PLH = ---------------------------------------------------------------------------- µ p C ox ( W 2L) p ( V OH + V Tp ) 2 In order to have identical propagation delays, the width-to-length ratio of the p- channel pull-up must be twice that of the n-channel driver, in order to compensate for the lower hole mobility in the channel.
Power Dissipation Energy from power supply needed to charge up the capacitor: E charge = V + it ()dt = V + Q = ( V + ) 2 ( C G + C P ) Energy stored in the capacitor: E store = 1 2 -- ( CG + C P )( V + ) 2 Energy lost in p-channel MOSFET during charging: 1 E diss = E charge + E store = -- 2 ( CG + C P )( V + ) 2 During discharge, the n-channel MOSFET driver dissipates an identical amount of energy. If the charge/discharge cycle is repeated f times/second, where f is the clock frequency, the dynamic power dissipation is: P = ( 2E diss ) f = ( C G + C P )( V + ) 2 f In practice, many gates donõt change state every clock cycle, which lowers the power dissipation Additional source of dissipation: power ßow from V + to ground when both transistors are saturated. Can be significant, but hard to estimate by hand. Typical number: 25% of dynamic power dissipation.
Power (cont.) Practical numbers: C L = 50 ff, f = 200 MHz, V + = 3 V, N gates = 5 x 10 5 P = 45 W! (note that the real average depends on the average number switching per clock cycle) Comparing Technologies -- the power-delay product * Logic families are often compared by considering the product of the dynamic power dissipation and the propagation delay: PDP Pt P ( C L + C p )( V + ) 2 ( C L + C p ) V + ( 2) = f -------------------------------------------- 1 -- k 2 N ( V + Ð V Tn ) 2 where V + has been substituted for V OH to achieve a more universal result. * For V + >> V Tn, ( C L + C p ) 2 V + f PDP -------------------------------------- k N
CMOS Static Logic Gates ÒStaticÓ -- logic levels remain valid so long as power is supplied NOR and NAND gates V DD M 4 A B M 3 + A M 1 B M 2 V OUT _ (a) V DD A M 3 M 4 A B B M 2 + V OUT _ M 1 (b)
CMOS NAND Gate Qualitative description Find transfer curve for case where V A = V B and both transition from 0 to 5 V Transistors M 1 and M 2 are in series and have the same current; however, they do not have the same gate-source bias V DD M 3 M 4 I D M 2 V GS1 = M 1 + V DS1 I D1 = I D2 V GS2 = V DS1 V DS (a) (b)
MOSFETs in Series Transistors M 1 and M 2 are Òin seriesó with the same gate voltage, for the case where the inputs are tied together (A = B) V OUT M 1 V A = V B M 2 ground drain current is the same through each device... what is the effective value of k P?
MOSFETs in Series (Cont.) At V A = V B =, the cross section through M 1 - M 2 is: gate M,, 1 M 2,, source (a) gate n + L 1 L 2 drain gate gate source M 1 M 2 drain L 1 L 2 (b) Transistor M 1 is in triode and M 2 is saturated. From the cross section, the drain of M 1 / source of M 2 can be eliminated without affecting anything --> the two MOSFETs can be merged into a composite transistor with L 1 + L 2 = 2 L n Solving for for the case where V A = V B (note that the two p-channel devices are in parallel and have an effective width of W 3 + W 4 = 2 W p 2k p V Tn + k ----------- ( n 2 V + V ) DD Tp = ------------------------------------------------------------------ = 2k p 1 + ----------- k n 2 V Tn 2 k p + ----- ( V k DD + V Tp ) n -------------------------------------------------------------- 1 2 k p + ----- k n where k n = µ n C ox (W n /L n ) and k p = µ p C ox (W p /L p ) We could optimize = V DD /2, but there is another switching condition to consider