1 EE 560 MOS TRANSISTOR THEORY PART
nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION REGION V S = 0 channel V G > V T0 SiO V D = V DSAT C GC C BC substrate or bulk B p depletion region pinch-off point
5 nmos TRANSISTOR IN SATURATION REGION V S = 0 channel V G > V T0 SIO V D > V DSAT C GC substrate or bulk B p C BC depletion region pinch-off point
MOSFET CURRENT - VOLTAGE CHARACTERISTICS V S = V B = 0 V G > V T0 6 V DS C GC substrate or bulk B p x C BC y y = 0 y = L y = 0 y Channel length = L y = L Channel width = Source side inversion layer (channel) dy Drain side
MOSFET CURRENT - VOLTAGE CHARACTERISTICS V S = V B = 0 V G > V T0 7 V DS C GC substrate or bulk B Boundary conditions: V CS (y = 0) = V S = 0 V CS (y = L) = V DS p x y = 0 C BC y V CS (y) y = L Assumptions: V T0 (y) = V T0 > V T0 Mobile charge in channel: V GD = - V DS > V T0 Q I (y) = C ox [ V CS (y) V T 0 ] dr = dy 1 µ n Q I (y) µ n = electron mobility = cm /Vsec [µ > U0 in SPICE]
MOSFET CURRENT - VOLTAGE CHARACTERISTICS Boundary conditions: Q I (y) = C ox [ V CS (y) V T 0 ] V CS (y = 0) = V S = 0 V CS (y = L) = V DS dr = dy 1 µ n Q I (y) 8 dv CS = dr = L dy = µ n 0 µ n Q I (y) dy Integrating along the channel 0 < y < L and 0 < V CS < V DS : i.e. V DS Q I (y) 0 dv CS = µ n C ox [( V T 0 )V DS V DS / ] = µ C n ox L [(V V )V V GS T 0 DS DS]
MOSFET CURRENT - VOLTAGE CHARACTERISTICS 9 = µ C n ox = k' L [(V V )V V GS T 0 DS DS] L [( V T 0 )V DS V DS = k [(V V )V V GS T 0 DS DS] ] k' = µ n C ox [k' -> KP in SPICE] k = k' L
MOSFET CURRENT - VOLTAGE CHARACTERISTICS 30 EXAMPLE 3.4 For an n-mos transistor with µ n = 600 cm /Vsec, C ox = 7 x 10-8 F/cm = 0 µm, L = µm, V T0 = 1.0 V, plot the relationship between and V DS,. = k [(V V )V V GS T 0 DS DS] where k = µ n C ox L F = C/V k = µ n C ox L = (600 cm /Vsec)(7x10 8 F/cm ) 0µ m = 0.4 ma/v µ m = 0.1mA/V [( 1.0) V DS V DS ] 4.0.0 0 LINEAR OR TRIODE REGION (ma) V DS = - V T0 VDS V T0 = 5V Assumptions: = 4V > V T0 V = 3V GD = V DS > V T0 V DS (V) 1.0 3.0 5.0
MOSFET CURRENT - VOLTAGE CHARACTERISTICS V DS - V T0 = V DSAT SATURATION REGION 31 = µ n C ox = µ n C ox L [(V V )V V GS T 0 DS DS] @VDS = V = V - V DSAT GS T0 L [( V T 0 )( V T 0 ) ( V T 0 ) ] (sat) = µ n C ox L ( V T 0 ) 4.0 V (ma) DS = - V T0 LINEAR SAT.0 = 5V = 4V 0 = 3V V DS (V) 1.0 3.0 5.0 (sat) V T0
MOSFET CURRENT - VOLTAGE CHARACTERISTICS CHANNEL LENGTH MODULATION Boundary conditions: V CS (y = 0) = V S = 0 V CS (y = L) = V DS Q I (y) = C ox [ V CS (y) V T 0 ] Q I (y = 0) = C ox [ V T 0 ] Q 1 (y = L) = C ox [ V DS V T 0 ] 3 V S = 0 V G > V T0 = 0 @ V DS = V DSAT V D > V DSAT substrate or bulk B p C GC C BC L' L L L' = L L effective channel length V CS (y = L') = V DSAT
MOSFET CURRENT - VOLTAGE CHARACTERISTICS V S = 0 V G > V T0 V D > V DSAT 33 substrate or bulk B p C GC C BC L' L L (sat) = µ n C ox where L L' (V T 0 ) = µ C n ox V DS V DSAT L(1 L (V V ) L ) GS T 0 emperical relation: 1 1 L = 1 + λv DS [λ -> LAMBDA in SPICE] L λ = channel length modulation coefficent (V -1 )
MOSFET CURRENT - VOLTAGE CHARACTERISTICS L' (V T 0 ) = µ C n ox (sat) = µ n C ox 1 1 L L = 1 + λ V DS (sat) = µ n C ox L(1 L (V V ) L ) GS T 0 L ( V T 0 ) (1 + λ V DS ) 34 4.0.0 0 V (ma) DS = - V T0 λ 0 λ 0 λ 0 1.0 3.0 5.0 = 5V = 4V = 3V V DS (V)
MOSFET CURRENT - VOLTAGE CHARACTERISTICS 35 SUBSTRATE BIAS EFFECT = f(, V DS, V SB )
MOSFET CURRENT - VOLTAGE CHARACTERISTICS n-mos G + n-mos = 0 D + V DS - + S for V T S - + - + - B G - - B V SB p-mos + D V SB V DS 36 > V T, V DS < - V T > V T, V DS > - V T p-mos = 0 for V T < V T, V DS > - V T < V T, V DS < - V T
MOSFET CURRENT - VOLTAGE CHARACTERISTICS MEASUREMENT OF PARAMETERS (V T0, γ, λ, k n, k p ) k n = µ n C ox k L p = µ p C ox L 37 D G S B + V SB + V DS = (sat) = k n ( V T 0 ) k n (sat) = (V V ) GS T 0 V SB = 0 V SB > 0 Gamma V T0 V T1
MOSFET CURRENT - VOLTAGE CHARACTERISTICS 38 Lambda = V T0 + 1+ G D S B + V DS > - V T0 1 V BS = 0 = V T0 + 1 (sat) = k n ( V T 0 ) (1+ λ V DS ) = V T0 + 1 V DS1 V DS V DS 1 = 1+ λv DS 1 + λ V DS1
EFFECTIVE CHANNEL LENGTH AND IDTH B S C GC C GC G D 39 substrate or pbulk B n + C BC BC n + n + n + p LD LD L L eff L M SPICE Parameters L eff = L M - LD - DL LD -> under diffusion DL -> error in photolith and etch eff = M - D SPICE Parameters D -> error in photolith and etch
MOSFET - SCALING SCALING -> refers to ordered reduction in dimensions of the MOSFET and other VLSI features Reduce Size of VLSI chips. Change operational charateristics of MOSFETs and parasitics. Phyiscal limits restrict degree of scaling that can be achieved. SCALING FACTOR = α > 1 --> S First-order "constant field" MOS scaling theory: The electric field E is kept constant, and the scaled device is obtained by applying a dimensionless scale-factor α to (such that E is unchanged): a. All dimensions, including those vertical to the surface (1/α) b. device voltages (1/α) c. the concentration densities (α). (1/α)/(1/α) = 1 <=> α(1/α) = 1 40
MOSFET - SCALING Alternative Scaling Rules: Constant Voltage Scaling, i.e. V DD is kept constant, while the process is scaled. a. All dimensions, including those vertical to the surface (1/α) b. device voltages (1) c. the concentration densities (α ). 1/(1/α) = α <=> α (1/α) = α 41 Lateral Scaling: only the gate length is scaled L = 1/α (gate-shrink). Year 1980 1983 1985 1987 1989 1991 1993 1995 Feature Size(µm) 5.0 3.5.5 1.75 1.5 1.0 0.8 0.6 Historical reduction in min feature size for typical CMOS Process
Influence of Scaling on MOS Device Performance PARAMETER SCALING MODEL Constant Field Constant Voltage Lateral 4 Length (L) 1/α 1/α 1/α idth () 1/α 1/α 1 Supply Voltage (V) 1/α 1 1 Gate Oxide thickness (t ox ) 1/α 1/α 1 Junction depth (X j ) 1/α 1/α 1 Substrate Doping (N A ) α α 1 Current (I) - (/L) (1/t ox )V 1/α α α Power Dissipation (P) - IV 1/α α α Electric Field Across Gate Oxide - V/t ox 1 α 1 Load Capacitance (C) - L (1/t ox ) 1/α 1/α 1/α Gate Delay (T) - VC/I 1/α 1/α 1/α
p B MOSFET CAPACITANCES S n + C GC C GC C BC BC n + n + G D n + 43 substrate or p bulk B LD LD L eff substrate or bulk B p L M L D L D n + n + Y
MOSFET CAPACITANCES 44 C gb D C gd C db G MOSFET (DC MODEL) B C gs C sb S C gd, C gs, C gb -> Oxide Capacitances C db, C sb -> Junction Capacitances
MOSFET CAPACITANCES 45 OXIDE Capacitances a. Overlap Caps C ox = ε ox t ox C GS (overlap) = C ox L D C GD (overlap) = C ox L D b. Gate - Channel MOSFET - Cut-off Region ALL MOSFET OPERATION REGIONS C gb = C ox L C gs = C gd = 0 p
MOSFET CAPACITANCES b. Gate - Channel MOSFET - Linear Region 46 C gb = 0 p C gs = (1/) C ox L C gd = (1/) C ox L p C gb = 0 C gs = (/3) C ox L C gd = 0
Capacitance Cut-off Linear Saturation 47 1 /3 1/ C gb (total) C gd (total) C gs (total) (C/C ox L) Cut-off C gb C ox L 0 0 0 + C ox L D 0 +C ox L D Saturation C gs 0.5C ox L + C ox L D 0.5C ox L + C ox L D Linear C gd 0 + C ox L D (/3)C L ox + C ox L D Gate -to Channel/Bulk Cap Contribution V T V T + V DS
JUNCTION Capacitances -> C db, C sb 48 x j p x d Y x j 1 5 3 n + Channel n + 4 Source Drain
JUNCTION Capacitances -> C db, C sb Y 49 1 n + Channel n + 4 [x j -> XJ in SPICE] Source Drain Junction Area Type 1 3 4 5 x j Y x j x j Y x j Y n + /p n + /p + n + /p + n + /p + n + /p 5 3 x j p - Substrate -> N A p + - Channel-stop -> 10N A
JUNCTION Capacitances -> C db, C sb 50 n +, p junctions p N A x d N D x j x d = ε Si 1 + 1 q N A N D (φ V) V = Ext bias --> V DB, V SB 0 φ 0 = kt q ln N N built-in junction A D n i potential [φ Depletion-region charge 0 -> PB in SPICE] Q j = Aq N N A D N A + N D x = A ε q N A N D d Si N A + N D (φ V) 0 C j = dq j dv = A ε Si q N A N D N A + N D 1 φ 0 V = AC j 0 1 V φ 0 1/ A = junction area [AS, AD -> Source, Drain Areas in SPICE]
C j = dq j dv = A ε q 51 Si N A N D 1 N A + N D φ 0 V = AC j 0 1 V 1/ (F) φ 0 m = grading coefficent C (F/cm j0 = ε q Si N A N D ) N m = 1/ for abrubt junction A + N 1 D φ 0 [m = MJ in SPICE] C j = C j0 when V = 0 [C j0 -> CJ in SPICE] [φ 0 -> PB in SPICE] EQUIVALENT LARGE SIGNAL CAPACTIANCE = AC j 0 φ 0 ( 1) 1 V (V V 1 )(1 m) φ 0 1 m 1 V 1 φ 0 1 m m = 1/ C eq = AC j0 K eq 0 < K eq < 1 --> Voltage Equiv Factor
n +, p + junctions (Sidewalls) 5 C j0sw = ε Si q N A (sw)n D N A (sw) + N D 1 φ 0sw (F/cm ) Since all sidewalls have depth = x j : [x j -> XJ in SPICE] C jsw = C j0sw x j (F/cm) [C jsw -> CJS in SPICE] EQUIVALENT LARGE SIGNAL CAPACTIANCE C eq (sw) = P C jsw K eq (sw) P = sidewall perimeter [PS, PD -> Source, Drain Perimeters in SPICE] K eq (sw) = φ 0sw (V V 1 ) 1 V φ 0sw 1/ 1 V 1 φ 0sw [m(sw) -> MJS in SPICE] 1/ m(sw) = 1/
EXAMPLE 3-8 Determine the total junction capacitance at the drain, i.e. C db, for the n-channel enhancement MOSFET in Fig. 1. The process parameters are Substrate doping N A = x 10 15 cm -3 Source/drain (n+) doping N D = 10 0 cm -3 Sidewall (p+) doping N A (sw) = 4 x 10 16 cm -3 Gate oxide thickness t ox = 45 nm Junction depth x j = 1.0 µm 10 µm G 53 5 µm D S n + n + Figure 1 µm Source, Drain are surrounded by p + channel-stop. The substrate is biased at 0V. Assume the drain voltage range is 0.5 V to 5.0 V.
54 where C j0 = ε Si q N A N D N A + N 1 D φ 0 C j0sw = ε Si q N A (sw)n D N A (sw) + N D 1 φ 0sw
5 µm 10 µm D S n + n + Figure 1 µm φ 0, φ 0sw φ 0 = kt q ln N N A D n i = 0.06Vln ( x1015 )10 0.1x10 0 G N A = x 10 15 cm -3 N D = 10 0 cm -3 N A (sw) = 4 x 10 16 cm -3 t ox = 45 nm x j = 1.0 µm = 0.896V φ 0sw = kt q ln N (sw)n A D n i = 0.06Vln (4x1016 )10 0.1x10 0 = 0.975V 55 C j0, C j0sw C j0 = ε Si q N A N D N A + N D 1 φ 0 = (1.04 x10 1 F/cm)(1.6x10 19 C) = 1.35x10 8 F/cm ( x10 15 )10 0 x10 15 +10 0 1 0.896V
C j0sw = ε Si q N A (sw)n D N A (sw) + N D 1 φ 0sw 56 = (1.04 x10 1 F/cm)(1.6x10 19 C) = 5.83x10 8 F/cm (4x10 16 )10 0 4x10 16 + 10 0 1 0.975V C jsw C jsw = C j0sw x j = (5.83x10 8 F/cm )(10 4 cm) = 5.83pF/cm K eq, K eq (sw) V BD1 = V B - V D1 = 0-0.5V = -0.5V V BD = V B - V D = 0-5V = -5V
57 Area, Perimeter Y n + Channel P D n + 4 Source Drain A D : n + /p junctions: 5 µm A D = (5 x 1) µm + (10 x 5) µm = 55 µm P D : n + /p + + junctions: P D = Y + = 0 µm + 5 µm = 5 µm 1 5 3 x j Figure 1 10 µm C db = A D C j 0 K eq + P D C j0sw K eq (sw) = 11.6fF G D S n + n + µm
Mobility Degradation due to Longitudinal Electric Field: VELOSITY SATURATION (very small channel lengths + high supply voltages) v Dsat velosity(v D ) slope = µ 0 E crit slope µ s µ 0 = v sat /E crit E Note µ s < µ 0 [SPICE Parameters: U0 -> µ 0, UCRIT -> E crit, VMAX -> v sat ] (sat) = v DSAT Q I = v DSAT C ox V DSAT = v DSAT C ox ( - V T ) Note: (sat) = linear f( - V T ), independent of L E y 58
Mobility Degradation due to Tranverse Electric Field: (due to gate voltage across very thin oxide-depletion layer) 59 µ n (eff) = µ n 0 1+ Θ E x µ n0 1+η( V T ) E x Short Channel Effect - V T0 (short channel) = V T0 - V T0 L eff --> x j L L S L D x j V T 0 = 1 x ds qε Si N A φ F x j L C ox x dd gate induced 1 + x ds 1 x j + 1+ x dd x j 1
60 Narrow Channel Effect - V T0 (narrow channel) = V T0 + V T0 --> x dm Thick Ox L Q NC Drain Poly Gate x dm Source Q NC Thin Ox V T 0 = 1 C ox qε Si N A φ F κ x dm
SPICE MODELING OF MOS CAPACITANCES 61 M1 4 3 5 0 NFET =4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U. m. m m. U = 10.MODEL NFET NMOS -6 cm + TOX=00E-8 F/m P = 10-1 + CGBO=00P CGSO=300P CGDO=300P + CJ=00U CJS=400P MJ=0.5 MJS=0.3 PB=0.7 V F/m F/m M1 4 3 5 0 NFET =4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U D G S B C gb = L C ox = 4 1 17 10-4 pf = 0.0068 pf
M1 4 3 5 0 NFET =4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U..MODEL NFET NMOS + TOX=00E-8 + CGBO=00P CGSO=300P CGDO=300P + CJ=00U CJS=400P MJ=0.5 MJS=0.3 PB=0.7 6 C j = Area CJ 1 + V -MJ j V - + Periphery CJS 1 + - j PB PB CJ = zero-bias junction capacitance per junction area -MJS (00 10-6 F/m = 10-4 pf/µm ) CJS = zero-bias junction capacitance per junction periphery (400 10-1 F/m = 4 10-10 pf/µm) MJ = grading coefficient of junction bottom (0.5) MJS = grading coefficient of junction side-wall (0.3) VJ = the junction potential (V sb, V db for n-channel, V bs, V bd for p-channel) PB = the built-in voltage (+0.7 V) Area = AS or AD, the area of source or drain (15 10-1 m = 15 µm ) Periphery = PS or PD, the periphery of source or drain (11.5 10-6 m = 11.5 µm)