74AVC20T General description. 2. Features and benefits

Similar documents
74AVC20T245-Q General description. 2. Features and benefits

74AVC32T General description. 2. Features and benefits

74AVC4T774PW. 4-bit dual supply translating transceiver; 3-state

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

The 74AXP1G04 is a single inverting buffer.

Octal bus transceiver; 3-state

The 74LV08 provides a quad 2-input AND function.

4-bit dual supply translating transceiver; 3-state

The 74AUP2G34 provides two low-power, low-voltage buffers.

4-bit dual-supply buffer/level translator; 3-state

74LVC1G125-Q100. Bus buffer/line driver; 3-state

8-bit dual supply translating transceiver with configurable voltage translation; 3-state

Bus buffer/line driver; 3-state

Single dual-supply translating 2-input OR with strobe

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

4-bit dual supply translating transceiver with configurable voltage translation; 3-state

Dual supply buffer/line driver; 3-state

Low-power configurable multiple function gate

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

Octal buffer/line driver; 3-state

2-input EXCLUSIVE-OR gate

Low-power configurable multiple function gate

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter.

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

Low-power triple buffer with open-drain output

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

4-bit magnitude comparator

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

4-bit dual-supply buffer/level translator; 3-state

Low-power dual Schmitt trigger inverter

Dual buffer/line driver; 3-state

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

7-stage binary ripple counter

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

74HC153-Q100; 74HCT153-Q100

74HC541; 74HCT541. Octal buffer/line driver; 3-state

74LVC8T245; 74LVCH8T245

74AVC1T General description. 2 Features and benefits. 1-to-4 fan-out buffer

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

74HC2G125; 74HCT2G125

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

74HC365; 74HCT365. Hex buffer/line driver; 3-state

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state

74AVCH16T General description. 2. Features and benefits

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

Dual buffer/line driver; 3-state

Hex inverter with open-drain outputs

74LVC8T245-Q100; 74LVCH8T245-Q100

74HC280; 74HCT bit odd/even parity generator/checker

Dual supply configurable multiple function gate

74HC30-Q100; 74HCT30-Q100

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74AVCH General description. 2. Features and benefits. 16-bit transceiver with direction pin; 3.6 V tolerant; 3-state

Dual buffer/line driver; 3-state

74ALVCH V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

74LVC07A-Q100. Hex buffer with open-drain outputs

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state

74HC126; 74HCT126. Quad buffer/line driver; 3-state

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate

The 74LVC10A provides three 3-input NAND functions.

74LVC823A-Q General description. 2. Features and benefits

Low-power dual PCB configurable multiple function gate

74HC151-Q100; 74HCT151-Q100

Octal bus transceiver; 3-state

74HC107-Q100; 74HCT107-Q100

74HC132-Q100; 74HCT132-Q100

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

74HC373-Q100; 74HCT373-Q100

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

Low-power dual supply buffer/line driver; 3-state

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger

74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.

2-input single supply translating NAND gate

Single supply translating buffer/line driver; 3-state

74AHC2G241; 74AHCT2G241

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder

74HC2G08-Q100; 74HCT2G08-Q100

74LVC541A-Q100. Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

Low-power Schmitt trigger inverter

8-bit parallel-in/serial-out shift register

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

74HC1G32-Q100; 74HCT1G32-Q100

74ALVCH General description. 2. Features and benefits. 16-bit bus transceiver and transparant D-type latch with 8 independent buffers

74LVC1G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

The 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

Low-power buffer/line driver; 3-state

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

Triple inverting Schmitt trigger with 5 V tolerant input

74HC1G02-Q100; 74HCT1G02-Q100

Transcription:

20-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 7 8 March 2012 Product data sheet 1. General description The is a 20-bit, dual supply transceiver that enables bi-directional voltage level translation. The device can be used as two 10-bit transceivers or as a single 20-bit transceiver. It features four 10-bit input-output ports (1An, 1Bn and 2An, 2Bn), two output enable inputs (noe), two direction inputs (ndir) and dual supplies (V CC(A) and V CC(B) ). V CC(A) and V CC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for bi-directional voltage level translation between any of the low voltage nodes: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The 1An and 2An ports, noe and ndir are referenced to V CC(A), the 1Bn and 2Bn ports are referenced to V CC(B). A HIGH on a 1DIR allows transmission from 1An to 1Bn and a LOW on 1DIR allows transmission from 1Bn to 1An. A HIGH on noe causes the outputs to assume a HIGH impedance OFF-state. The device is fully specified for partial power-down applications using I OFF. The I OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V CC(A) or V CC(B) are at GND level, all output ports will assume a high impedance OFF-state. 2. Features and benefits Wide supply voltage range: V CC(A) : 0.8 V to 3.6 V V CC(B) : 0.8 V to 3.6 V Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 260 Mbit/s ( 1.1 V to 3.3 V translation) 260 Mbit/s ( 1.1 V to 2.5 V translation) 210 Mbit/s ( 1.1 V to 1.8 V translation)

3. Ordering information 120 Mbit/s ( 1.1 V to 1.5 V translation) 100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Latch-up performance exceeds 100 ma per JESD 78 Class II Inputs accept voltages up to 3.6 V I OFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to+85 C and 40 C to+125 C Table 1. Type number Ordering information Package [1] Also known as TVSOP56. Temperature range Name Description Version DGG 40 C to +125 C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm DGV 40 C to +125 C TSSOP56 [1] plastic thin shrink small outline package; 56 leads; body width 4.4 mm BX 40 C to+125 C HXQFN60 plastic compatible thermal enhanced extremely thin quad flat package; no leads; 60 terminals; body 4 6 0.5 mm SOT364-1 SOT481-2 SOT1134-2 4. Functional diagram 1DIR 2DIR 1OE 2OE 1A1 2A1 1B1 2B1 V CC(A) V CC(B) V CC(A) V CC(B) to other nine channels to other nine channels 001aal240 Fig 1. Logic diagram Product data sheet Rev. 7 8 March 2012 2 of 27

2 3 5 6 8 9 10 12 13 14 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 V CC(A) V CC(B) 56 1OE 1 1DIR 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 55 54 52 51 49 48 47 45 44 43 15 16 17 19 20 21 23 24 26 27 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 V CC(A) V CC(B) 29 2OE 28 2DIR 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 42 41 40 38 37 36 34 33 31 30 001aal239 Pin numbers are shown for TSSOP56 packages only. Fig 2. Logic symbol Product data sheet Rev. 7 8 March 2012 3 of 27

5. Pinning information 5.1 Pinning 1DIR 1B1 1B2 GND 1B3 1B4 V CC(B) 1B5 1B6 1B7 GND 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 V CC(B) 2B7 2B8 GND 2B9 2B10 2DIR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 1OE 55 1A1 54 1A2 53 GND 52 1A3 51 1A4 50 V CC(A) 49 1A5 48 1A6 47 1A7 46 GND 45 1A8 44 1A9 43 1A10 42 2A1 41 2A2 40 2A3 39 GND 38 2A4 37 2A5 36 2A6 35 V CC(A) 34 2A7 33 2A8 32 GND 31 2A9 30 2A10 29 2OE 001aal241 Fig 3. Pin configuration SOT364-1 (TSSOP56) and SOT481-2 (TSSOP56) Product data sheet Rev. 7 8 March 2012 4 of 27

terminal A1 index area D1 A32 A31 A30 A29 A28 A27 D4 A1 D5 B20 B19 B18 D8 A26 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 GND (1) B17 B16 B15 B14 B13 B12 B11 A25 A24 A23 A22 A21 A20 A19 A18 A10 D6 B8 B9 B10 D7 A17 D2 A11 A12 A13 A14 A15 A16 D3 001aam129 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SOT1134-2 (HXQFN60) Product data sheet Rev. 7 8 March 2012 5 of 27

5.2 Pin description Table 2. Pin description Symbol Pin Description SOT364-1 and SOT481-2 SOT1134-2 1DIR, 2DIR 1, 28 A30, A13 direction control 1B1 to 1B10 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 B20, A31, D5, D1, B1, A2, data input or output B2, A4, B3, A5 2B1 to 2B10 15, 16, 17, 19, 20, 21, 23, 24, A6, B5, A7, B6, A9, B7, D2, data input or output 26, 27 D6, A12, B8 GND [1] 4, 11, 18, 25, 32, 39, 46, 53 A32, A3, A8, A11, A16, ground (0 V) A19, A24, A27 V CC(B) 7, 22 A1, A10 supply voltage B (nbn inputs are referenced to V CC(B) ) 1OE, 2OE 56, 29 A29, A14 output enable input (active LOW) 1A1 to 1A10 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 2A1 to 2A10 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 [1] All GND pins must be connected to ground (0 V). B18, A28, D8, D4, B17, A25, B16, A23, B15, A22 A21, B13, A20, B12, A18, B11, D3, D7, A15, B10 data input or output data input or output V CC(A) 35, 50 A17, A26 supply voltage A (nan, noe and ndir inputs are referenced to V CC(A) ) n.c. - B4, B9, B14, B19 not connected 6. Functional description Table 3. Function table [1] Supply voltage Input Input/output [2] V CC(A), V CC(B) noe [3] ndir [3] nan [3] nbn [3] 0.8 V to 3.6 V L L nan = nbn input 0.8 V to 3.6 V L H input nbn = nan 0.8 V to 3.6 V H X Z Z GND [2] X X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don t care; Z = high-impedance OFF-state. [2] If at least one of V CC(A) or V CC(B) is at GND level, the device goes into suspend mode. [3] The nan, ndir and noe input circuit is referenced to V CC(A) ; The nbn input circuit is referenced to V CC(B). Product data sheet Rev. 7 8 March 2012 6 of 27

7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC(A) supply voltage A 0.5 +4.6 V V CC(B) supply voltage B 0.5 +4.6 V I IK input clamping current V I <0V 50 - ma V I input voltage [1] 0.5 +4.6 V I OK output clamping current V O <0V 50 - ma V O output voltage Active mode [1][2][3] 0.5 V CCO +0.5 V Suspend or 3-state mode [1] 0.5 +4.6 V I O output current V O =0VtoV CCO [2] - 50 ma I CC supply current I CC(A) or I CC(B) - 100 ma I GND ground current 100 - ma T stg storage temperature 65 +150 C P tot total power dissipation T amb = 40 C to +125 C TSSOP56 package [4] - 600 mw HXQFN60 package [5] - 1000 mw [1] The minimum input and minimum output voltage ratings may be exceeded if the input and output clamping current ratings are observed. [2] V CCO is the supply voltage associated with the output port. [3] V CCO + 0.5 V should not exceed 4.6 V. [4] Above 55 C the value of P tot derates linearly with 8.0 mw/k. [5] Above 70 C the value of P tot derates linearly with 1.8 mw/k. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit V CC(A) supply voltage A 0.8 3.6 V V CC(B) supply voltage B 0.8 3.6 V V I input voltage 0 3.6 V V O output voltage Active mode [1] 0 V CCO V Suspend or 3-state mode 0 3.6 V T amb ambient temperature 40 +125 C t/ V input transition rise and fall rate V CCI = 0.8 V to 3.6 V [2] - 5 ns/v [1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the input port. Product data sheet Rev. 7 8 March 2012 7 of 27

9. Static characteristics Table 6. Typical static characteristics at T amb = 25 C [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V OH HIGH-level output voltage V I = V IH or V IL V OL LOW-level output voltage V I = V IH or V IL I I input leakage current ndir, noe input; V I = 0 V or 3.6 V; V CC(A) =V CC(B) = 0.8 V to 3.6 V I OZ OFF-state output current A or B port; V O =0 Vor V CCO ; V CC(A) =V CC(B) =3.6V [1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter I OZ includes the input leakage current. I O = 1.5 ma; V CC(A) =V CC(B) = 0.8 V - 0.69 - V I O = 1.5 ma; V CC(A) =V CC(B) = 0.8 V - 0.07 - V suspend mode A port; V O =0VorV CCO ; V CC(A) = 3.6 V; V CC(B) =0V suspend mode B port; V O =0VorV CCO ; V CC(A) =0 V; V CC(B) =3.6V I OFF power-off leakage current A port; V I or V O = 0 V to 3.6 V; V CC(A) =0V;V CC(B) = 0.8 V to 3.6 V B port; V I or V O = 0 V to 3.6 V; V CC(B) =0V;V CC(A) = 0.8 V to 3.6 V C I input capacitance ndir, noe input; V I = 0 V or 3.3 V; V CC(A) =V CC(B) =3.3V C I/O input/output capacitance A and B port; V O = 3.3 V or 0 V; V CC(A) =V CC(B) =3.3V - 0.025 0.25 A [3] - 0.5 2.5 A [3] - 0.5 2.5 A [3] - 0.5 2.5 A - 0.1 1 A - 0.1 1 A - 2.0 - pf - 4.0 - pf Table 7. Static characteristics [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Max Min Max V IH HIGH-level data input input voltage V CCI = 0.8 V 0.70V CCI - 0.70V CCI - V V CCI = 1.1 V to 1.95 V 0.65V CCI - 0.65V CCI - V V CCI = 2.3 V to 2.7 V 1.6-1.6 - V V CCI = 3.0 V to 3.6 V 2-2 - V ndir, noe input V CC(A) = 0.8 V 0.70V CC(A) - 0.70V CC(A) - V V CC(A) = 1.1 V to 1.95 V 0.65V CC(A) - 0.65V CC(A) - V V CC(A) = 2.3 V to 2.7 V 1.6-1.6 - V V CC(A) = 3.0 V to 3.6 V 2-2 - V Product data sheet Rev. 7 8 March 2012 8 of 27

Table 7. Static characteristics continued [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Max Min Max V IL LOW-level data input input voltage V CCI = 0.8 V - 0.30V CCI - 0.30V CCI V V CCI = 1.1 V to 1.95 V - 0.35V CCI - 0.35V CCI V V CCI = 2.3 V to 2.7 V - 0.7-0.7 V V CCI = 3.0 V to 3.6 V - 0.8-0.8 V ndir, noe input V CC(A) = 0.8 V - 0.30V CC(A) - 0.30V CC(A) V V CC(A) = 1.1 V to 1.95 V - 0.35V CC(A) - 0.35V CC(A) V V CC(A) = 2.3 V to 2.7 V - 0.7-0.7 V V CC(A) = 3.0 V to 3.6 V - 0.8-0.8 V V OH HIGH-level V I = V IH or V IL output voltage I O = 100 A; V CCO 0.1 - V CCO 0.1 - V V CC(A) =V CC(B) = 0.8 V to 3.6 V I O = 3 ma; 0.85-0.85 - V V CC(A) =V CC(B) =1.1V I O = 6 ma; 1.05-1.05 - V V CC(A) =V CC(B) =1.4V I O = 8 ma; 1.2-1.2 - V V CC(A) =V CC(B) =1.65V I O = 9 ma; 1.75-1.75 - V V CC(A) =V CC(B) =2.3V I O = 12 ma; V CC(A) =V CC(B) =3.0V 2.3-2.3 - V V OL LOW-level V I = V IH or V IL output voltage I O = 100 A; - 0.1-0.1 V V CC(A) =V CC(B) = 0.8 V to 3.6 V I O = 3 ma; V CC(A) =V CC(B) = 1.1 V - 0.25-0.25 V I O = 6 ma; V CC(A) =V CC(B) = 1.4 V - 0.35-0.35 V I O = 8 ma; - 0.45-0.45 V V CC(A) =V CC(B) =1.65V I O = 9 ma; V CC(A) =V CC(B) = 2.3 V - 0.55-0.55 V I O = 12 ma; - 0.7-0.7 V V CC(A) =V CC(B) =3.0V I I input leakage ndir, noe input; V I = 0 V or 3.6 V; - 1-5 A current V CC(A) =V CC(B) = 0.8 V to 3.6 V I OZ OFF-state A or B port; V O =0 Vor V CCO ; [3] - 5-30 A output current V CC(A) =V CC(B) =3.6V suspend mode A port; [3] - 5-30 A V O =0VorV CCO ; V CC(A) = 3.6 V; V CC(B) =0V suspend mode B port; V O =0VorV CCO ; V CC(A) =0 V; V CC(B) =3.6V [3] - 5-30 A Product data sheet Rev. 7 8 March 2012 9 of 27

Table 7. Static characteristics continued [1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Max Min Max - 5-30 A I OFF power-off leakage current A port; V I or V O = 0 V to 3.6 V; V CC(A) =0V; V CC(B) = 0.8 V to 3.6 V B port; V I or V O = 0 V to 3.6 V; V CC(B) =0V; V CC(A) = 0.8 V to 3.6 V [1] V CCO is the supply voltage associated with the output port. [2] V CCI is the supply voltage associated with the data input port. [3] For I/O ports, the parameter I OZ includes the input leakage current. - 5-30 A I CC supply current A port; V I = 0 V or V CCI ; I O = 0 A V CC(A) = 0.8 V to 3.6 V; - 45-190 A V CC(B) = 0.8 V to 3.6 V V CC(A) = 1.1 V to 3.6 V; - 35-140 A V CC(B) = 1.1 V to 3.6 V V CC(A) = 3.6 V; V CC(B) = 0 V - 35-140 A V CC(A) = 0 V; V CC(B) = 3.6 V 5-20 - A B port; V I = 0 V or V CCI ; I O = 0 A V CC(A) = 0.8 V to 3.6 V; - 45-190 A V CC(B) = 0.8 V to 3.6 V V CC(A) = 1.1 V to 3.6 V; - 35-140 A V CC(B) = 1.1 V to 3.6 V V CC(A) = 3.6 V; V CC(B) = 0 V 5-20 - A V CC(A) = 0 V; V CC(B) = 3.6 V - 35-140 A A plus B port (I CC(A) + I CC(B) ); - 80-270 A I O =0A; V I =0 Vor V CCI ; V CC(A) = 0.8 V to 3.6 V; V CC(B) = 0.8 V to 3.6 V A plus B port (I CC(A) + I CC(B) ); I O =0A; V I =0 Vor V CCI ; V CC(A) = 1.1 V to 3.6 V; V CC(B) = 1.1 V to 3.6 V - 65-220 A Table 8. Typical total supply current (I CC(A) + I CC(B) ) V CC(A) V CC(B) Unit 0 V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0 V 0 0.1 0.1 0.1 0.1 0.1 0.1 A 0.8 V 0.1 0.1 0.1 0.1 0.1 0.3 1.6 A 1.2 V 0.1 0.1 0.1 0.1 0.1 0.1 0.8 A 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.4 A 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.2 A 2.5 V 0.1 0.3 0.1 0.1 0.1 0.1 0.1 A 3.3 V 0.1 1.6 0.8 0.4 0.2 0.1 0.1 A Product data sheet Rev. 7 8 March 2012 10 of 27

10. Dynamic characteristics Table 9. Typical power dissipation capacitance at V CC(A) = V CC(B) and T amb = 25 C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V CC(A) = V CC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V C PD power dissipation capacitance [1] C PD is used to determine the dynamic power dissipation (P D in W). P D =C PD V CC 2 f i N+ (C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = load capacitance in pf; V CC = supply voltage in V; A port: (direction A to B); output enabled A port: (direction A to B); output disabled A port: (direction B to A); output enabled A port: (direction B to A); output disabled B port: (direction A to B); output enabled B port: (direction A to B); output disabled B port: (direction B to A); output enabled B port: (direction B to A); output disabled N = number of inputs switching; (C L V 2 CC f o ) = sum of the outputs. [2] f i = 10 MHz; V I =GNDtoV CC ; t r = t f = 1 ns; C L = 0 pf; R L =. 0.2 0.2 0.2 0.2 0.3 0.4 pf 0.2 0.2 0.2 0.2 0.3 0.4 pf 9.5 9.7 9.8 9.9 10.7 11.9 pf 0.6 0.6 0.6 0.6 0.7 0.7 pf 9.5 9.7 9.8 9.9 10.7 11.9 pf 0.6 0.6 0.6 0.6 0.7 0.7 pf 0.2 0.2 0.2 0.2 0.3 0.4 pf 0.2 0.2 0.2 0.2 0.3 0.4 pf Product data sheet Rev. 7 8 March 2012 11 of 27

Table 10. Typical dynamic characteristics at V CC(A) = 0.8 V and T amb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter Conditions V CC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V t pd propagation delay nan to nbn 14.4 7.0 6.2 6.0 5.9 6.0 ns nbn to nan 14.4 12.4 12.1 11.9 11.8 11.8 ns t dis disable time noe to nan 16.2 16.2 16.2 16.2 16.2 16.2 ns noe to nbn 17.6 10.0 9.0 9.1 8.7 9.3 ns t en enable time noe to nan 21.9 21.9 21.9 21.9 21.9 21.9 ns noe to nbn 22.2 11.1 9.8 9.4 9.4 9.6 ns [1] t pd is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. Table 11. Typical dynamic characteristics at V CC(B) = 0.8 V and T amb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter Conditions V CC(A) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V t pd propagation delay nan to nbn 14.4 12.4 12.1 11.9 11.8 11.8 ns nbn to nan 14.4 7.0 6.2 6.0 5.9 6.0 ns t dis disable time noe to nan 16.2 5.9 4.4 4.2 3.1 3.5 ns noe to nbn 17.6 14.2 13.7 13.6 13.3 13.1 ns t en enable time noe to nan 21.9 6.4 4.4 3.5 2.6 2.3 ns noe to nbn 22.2 17.7 17.2 17.0 16.8 16.7 ns [1] t pd is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. Product data sheet Rev. 7 8 March 2012 12 of 27

Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6. Symbol Parameter Conditions V CC(B) Unit 1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V Min Max Min Max Min Max Min Max Min Max V CC(A) = 1.1 V to 1.3 V t pd propagation nan to nbn 0.5 9.4 0.5 7.1 0.5 6.2 0.5 5.2 0.5 5.1 ns delay nbn to nan 0.5 9.4 0.5 8.9 0.5 8.7 0.5 8.4 0.5 8.2 ns t dis disable time noe to nan 2.0 11.9 2.0 11.9 2.0 11.9 2.0 11.9 2.0 11.9 ns noe to nbn 1.5 12.7 1.5 9.8 1.5 9.6 1.0 8.1 1.0 9.0 ns t en enable time noe to nan 1.5 15.3 1.5 15.3 1.5 15.3 1.5 15.3 1.5 15.3 ns noe to nbn 1.0 15.6 1.0 11.5 1.0 10.0 0.5 8.4 0.5 8.0 ns V CC(A) = 1.4 V to 1.6 V t pd propagation nan to nbn 0.5 8.9 0.5 6.4 0.5 5.4 0.5 4.3 0.5 3.9 ns delay nbn to nan 0.5 7.1 0.5 6.4 0.5 6.1 0.5 5.8 0.5 5.7 ns t dis disable time noe to nan 2.0 9.0 2.0 9.0 2.0 9.0 2.0 9.0 2.0 9.0 ns noe to nbn 1.5 11.7 1.5 9.0 1.5 7.8 1.0 6.4 1.0 6.0 ns t en enable time noe to nan 1.5 10.3 1.5 10.3 1.5 10.3 1.5 10.2 1.5 10.2 ns noe to nbn 1.0 14.3 1.0 10.3 1.0 8.4 0.5 6.1 0.5 5.3 ns V CC(A) = 1.65 V to 1.95 V t pd propagation nan to nbn 0.5 8.7 0.5 6.1 0.5 5.0 0.5 3.9 0.5 3.5 ns delay nbn to nan 0.5 6.2 0.5 5.4 0.5 5.0 0.5 4.7 0.5 4.6 ns t dis disable time noe to nan 2.0 7.4 2.0 7.4 2.0 7.4 2.0 7.4 2.0 7.4 ns noe to nbn 1.5 11.3 1.5 8.7 1.5 7.4 1.0 5.8 1.0 5.6 ns t en enable time noe to nan 1.0 8.1 1.0 8.1 1.0 7.9 1.0 7.9 1.0 7.9 ns noe to nbn 0.5 13.8 0.5 10.0 0.5 7.9 0.5 5.7 0.5 4.8 ns V CC(A) = 2.3V to 2.7V t pd propagation nan to nbn 0.5 8.4 0.5 5.8 0.5 4.7 0.5 3.5 0.5 3.0 ns delay nbn to nan 0.5 5.2 0.5 4.3 0.5 3.9 0.5 3.5 0.5 3.4 ns t dis disable time noe to nan 1.1 5.2 1.1 5.2 1.1 5.2 1.1 5.2 1.1 5.2 ns noe to nbn 1.2 10.8 1.2 8.2 1.2 6.9 1.0 5.3 1.0 5.2 ns t en enable time noe to nan 0.5 5.4 0.5 5.4 0.5 5.3 0.5 5.2 0.5 5.2 ns noe to nbn 0.5 13.3 0.5 9.6 0.5 7.6 0.5 5.3 0.5 4.3 ns V CC(A) = 3.0V to 3.6V t pd propagation nan to nbn 0.5 8.2 0.5 5.7 0.5 4.6 0.5 3.4 0.5 2.9 ns delay nbn to nan 0.5 5.1 0.5 3.9 0.5 3.5 0.5 3.0 0.5 2.9 ns t dis disable time noe to nan 0.8 5.0 0.8 5.0 0.8 5.0 0.8 5.0 0.8 5.0 ns noe to nbn 1.2 10.5 1.2 8.1 1.2 6.7 1.0 5.1 0.8 5.0 ns t en enable time noe to nan 0.5 4.4 0.5 4.4 0.5 4.3 0.5 4.2 0.5 4.1 ns noe to nbn 1.0 13.1 1.0 9.6 0.5 7.5 0.5 5.1 0.5 4.1 ns [1] t pd is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. Product data sheet Rev. 7 8 March 2012 13 of 27

Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter Conditions V CC(B) Unit 1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V Min Max Min Max Min Max Min Max Min Max V CC(A) = 1.1 V to 1.3 V t pd propagation nan to nbn 0.5 10.4 0.5 7.9 0.5 6.9 0.5 5.8 0.5 5.7 ns delay nbn to nan 0.5 10.4 0.5 9.8 0.5 9.6 0.5 9.3 0.5 9.1 ns t dis disable time noe to nan 2.0 13.1 2.0 13.1 2.0 13.1 2.0 13.1 2.0 13.1 ns noe to nbn 1.5 14.0 1.5 10.8 1.5 10.6 1.0 9.0 1.0 9.9 ns t en enable time noe to nan 1.5 16.9 1.5 16.9 1.5 16.9 1.5 16.9 1.5 16.9 ns noe to nbn 1.0 17.2 1.0 12.7 1.0 11.0 0.5 9.3 0.5 8.8 ns V CC(A) = 1.4 V to 1.6 V t pd propagation nan to nbn 0.5 9.8 0.5 7.1 0.5 6.0 0.5 4.8 0.5 4.3 ns delay nbn to nan 0.5 7.9 0.5 7.1 0.5 6.8 0.5 6.4 0.5 6.3 ns t dis disable time noe to nan 2.0 9.9 2.0 9.9 2.0 9.9 2.0 9.9 2.0 9.9 ns noe to nbn 1.5 12.9 1.5 9.9 1.5 8.6 1.0 7.1 1.0 6.6 ns t en enable time noe to nan 1.5 11.4 1.5 11.4 1.5 11.4 1.5 11.3 1.5 11.3 ns noe to nbn 1.0 15.8 1.0 11.4 1.0 9.3 0.5 6.8 0.5 5.9 ns V CC(A) = 1.65 V to 1.95 V t pd propagation nan to nbn 0.5 9.6 0.5 6.8 0.5 5.5 0.5 4.3 0.5 3.9 ns delay nbn to nan 0.5 6.9 0.5 6.0 0.5 5.5 0.5 5.2 0.5 5.1 ns t dis disable time noe to nan 2.0 8.2 2.0 8.2 2.0 8.2 2.0 8.2 2.0 8.2 ns noe to nbn 1.5 12.5 1.5 9.6 1.5 8.2 1.0 6.4 1.0 6.2 ns t en enable time noe to nan 1.0 9.0 1.0 9.0 1.0 8.7 1.0 8.7 1.0 8.7 ns noe to nbn 0.5 15.2 0.5 11.0 0.5 8.7 0.5 6.3 0.5 5.3 ns V CC(A) = 2.3V to 2.7V t pd propagation nan to nbn 0.5 9.3 0.5 6.4 0.5 5.2 0.5 3.9 0.5 3.3 ns delay nbn to nan 0.5 5.8 0.5 4.8 0.5 4.3 0.5 3.9 0.5 3.8 ns t dis disable time noe to nan 1.1 5.8 1.1 5.8 1.1 5.8 1.1 5.8 1.1 5.8 ns noe to nbn 1.2 11.9 1.2 9.1 1.2 7.6 1.0 5.9 1.0 5.8 ns t en enable time noe to nan 0.5 6.0 0.5 6.0 0.5 5.9 0.5 5.8 0.5 5.8 ns noe to nbn 0.5 14.7 0.5 10.6 0.5 8.4 0.5 5.9 0.5 4.8 ns V CC(A) = 3.0V to 3.6V t pd propagation nan to nbn 0.5 9.1 0.5 6.3 0.5 5.1 0.5 3.8 0.5 3.2 ns delay nbn to nan 0.5 5.7 0.5 4.3 0.5 3.9 0.5 3.3 0.5 3.2 ns t dis disable time noe to nan 0.8 5.5 0.8 5.5 0.8 5.5 0.8 5.5 0.8 5.5 ns noe to nbn 1.2 11.6 1.2 9.0 1.2 7.4 1.0 5.7 0.8 5.5 ns t en enable time noe to nan 0.5 4.9 0.5 4.9 0.5 4.8 0.5 4.7 0.5 4.6 ns noe to nbn 1.0 14.5 1.0 10.6 0.5 8.3 0.5 5.7 0.5 4.6 ns [1] t pd is the same as t PLH and t PHL ; t dis is the same as t PLZ and t PHZ ; t en is the same as t PZL and t PZH. Product data sheet Rev. 7 8 March 2012 14 of 27

11. Waveforms V I nan, nbn input V M GND t PHL t PLH V OH nbn, nan output V M V OL 001aak285 Fig 5. Measurement points are given in Table 14. V OL and V OH are typical output voltage levels that occur with the output load. The data input (nan, nbn) to output (nbn, nan) propagation delay times V I noe input V M GND t PLZ t PZL V CCO output LOW-to-OFF OFF-to-LOW V OL V X V M t PHZ t PZH V OH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled V Y outputs disabled V M outputs enabled 001aak286 Fig 6. Measurement points are given in Table 14. V OL and V OH are typical output voltage levels that occur with the output load. Enable and disable times Table 14. Measurement points Supply voltage Input [1] Output [2] V CC(A), V CC(B) V M V M V X V Y 0.8 V to 1.6 V 0.5V CCI 0.5V CCO V OL +0.1V V OH 0.1 V 1.65 V to 2.7 V 0.5V CCI 0.5V CCO V OL +0.15V V OH 0.15 V 3.0 V to 3.6 V 0.5V CCI 0.5V CCO V OL +0.3V V OH 0.3 V [1] V CCI is the supply voltage associated with the data input port. [2] V CCO is the supply voltage associated with the output port. Product data sheet Rev. 7 8 March 2012 15 of 27

V I negative pulse 0 V 90 % V M 10 % t W V M t f t r t r t f V I positive pulse 0 V 10 % 90 % V M t W V M V EXT V CC G V I DUT V O RL RT CL RL 001aae331 Fig 7. Test data is given in Table 15. R L = Load resistance. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance. V EXT = External voltage for measuring switching times. Test circuit for measuring switching times Table 15. Test data Supply voltage Input Load V EXT V CC(A), V CC(B) V [1] I t/ V [2] C L R L t PLH, t PHL t PZH, t PHZ t PZL, t [3] PLZ 0.8 V to 1.6 V V CCI 1.0ns/V 15pF 2k open GND 2V CCO 1.65 V to 2.7 V V CCI 1.0ns/V 15pF 2k open GND 2V CCO 3.0 V to 3.6 V V CCI 1.0ns/V 15pF 2k open GND 2V CCO [1] V CCI is the supply voltage associated with the data input port. [2] dv/dt 1.0 V/ns [3] V CCO is the supply voltage associated with the output port. Product data sheet Rev. 7 8 March 2012 16 of 27

12. Typical propagation delay characteristics t pd (ns) 24 20 16 001aai476 (1) t pd (ns) 21 17 001aai477 (1) (2) (3) (4) (5) (6) 12 8 (2) (3) (4) (5) (6) 13 4 0 20 40 60 C L (pf) 9 0 20 40 60 C L (pf) a. Propagation delay (nan to nbn); V CC(A) = 0.8 V b. Propagation delay (nan to nbn); V CC(B) = 0.8 V (1) V CC(B) = 0.8 V. (1) V CC(A) = 0.8 V. (2) V CC(B) = 1.2 V. (2) V CC(A) = 1.2 V. (3) V CC(B) = 1.5 V. (3) V CC(A) = 1.5 V. (4) V CC(B) = 1.8 V. (4) V CC(A) = 1.8 V. (5) V CC(B) = 2.5 V. (5) V CC(A) = 2.5 V. (6) V CC(B) = 3.3 V. (6) V CC(A) = 3.3 V. Fig 8. Typical propagation delay versus load capacitance; T amb = 25 C Product data sheet Rev. 7 8 March 2012 17 of 27

7 001aai478 (1) 7 001aai491 t PLH (ns) t PHL (ns) (1) 5 (2) 5 (3) (2) 3 (4) (5) 3 (3) (4) (5) 1 0 20 40 60 C L (pf) a. LOW to HIGH propagation delay (nan to nbn); V CC(A) = 1.2 V 1 0 20 40 60 C L (pf) b. HIGH to LOW propagation delay (nan to nbn); V CC(A) = 1.2 V 7 001aai479 7 001aai480 t PLH (ns) (1) t PHL (ns) 5 (2) 5 (1) (3) (2) 3 (4) (5) 3 (3) (4) (5) 1 0 20 40 60 C L (pf) 1 0 20 40 60 C L (pf) Fig 9. c. LOW to HIGH propagation delay (nan to nbn); V CC(A) = 1.5 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Typical propagation delay versus load capacitance; T amb = 25 C d. HIGH to LOW propagation delay (nan to nbn); V CC(A) = 1.5 V Product data sheet Rev. 7 8 March 2012 18 of 27

7 001aai481 7 001aai482 t PLH (ns) (1) t PHL (ns) 5 (2) 5 (1) (3) (2) 3 (4) (5) 3 (3) (4) (5) 1 0 20 40 60 C L (pf) a. LOW to HIGH propagation delay (nan to nbn); V CC(A) = 1.8 V 1 0 20 40 60 C L (pf) b. HIGH to LOW propagation delay (nan to nbn); V CC(A) = 1.8 V 7 001aai483 7 001aai486 t PLH (ns) (1) t PHL (ns) 5 5 (1) (2) (3) (2) 3 (4) (5) 3 (3) (4) (5) 1 0 20 40 60 C L (pf) 1 0 20 40 60 C L (pf) Fig 10. c. LOW to HIGH propagation delay (nan to nbn); V CC(A) = 2.5 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Typical propagation delay versus load capacitance; T amb = 25 C d. HIGH to LOW propagation delay (nan to nbn); V CC(A) = 2.5 V Product data sheet Rev. 7 8 March 2012 19 of 27

7 001aai485 7 001aai484 t PLH (ns) (1) t PHL (ns) 5 5 (1) (2) 3 (3) (4) (5) 3 (2) (3) (4) (5) 1 0 20 40 60 C L (pf) 1 0 20 40 60 C L (pf) Fig 11. a. LOW to HIGH propagation delay (nan to nbn); V CC(A) = 3.3 V (1) V CC(B) = 1.2 V. (2) V CC(B) = 1.5 V. (3) V CC(B) = 1.8 V. (4) V CC(B) = 2.5 V. (5) V CC(B) = 3.3 V. Typical propagation delay versus load capacitance; T amb = 25 C b. HIGH to LOW propagation delay (nan to nbn); V CC(A) = 3.3 V Product data sheet Rev. 7 8 March 2012 20 of 27

13. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 D E A X c y H E v M A Z 56 29 Q A 2 A 1 (A ) 3 A pin 1 index 1 28 detail X L p L θ e bp w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions). A UNIT A 1 A 2 A 3 b p c D (1) E (2) e H E L L p Q v w y Z max. 0.15 1.05 0.28 0.2 14.1 6.2 8.3 0.8 0.50 0.5 mm 1.2 0.25 0.5 1 0.25 0.08 0.1 0.05 0.85 0.17 0.1 13.9 6.0 7.9 0.4 0.35 0.1 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT364-1 MO-153 99-12-27 03-02-19 Fig 12. Package outline SOT364-1 (TSSOP56) Product data sheet Rev. 7 8 March 2012 21 of 27

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 4.4 mm SOT481-2 D E A X c y H E v M A Z 56 29 A A 2 A 1 (A ) 3 pin 1 index θ L p L 1 28 detail X e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT A 1 A 2 A 3 b p c D (1) E (2) e H E L L p v w y Z max. (1) mm 1.2 0.15 0.05 1.05 0.80 0.25 0.23 0.13 0.20 0.09 11.4 11.2 4.5 4.3 0.4 6.6 6.2 1 0.75 0.45 0.2 0.07 0.08 0.4 0.1 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT481-2 - - - MO-194 - - - 01-11-24 Fig 13. Package outline SOT481-2 (TSSOP56) Product data sheet Rev. 7 8 March 2012 22 of 27

HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads; 60 terminals; body 4 x 6 x 0.5 mm SOT1134-2 D B A terminal 1 index area E A A 2 A 1 detail X e 2 e 1 b er v w C C A B v w C A B e C L 1 D2 D6 A11 1/2 e A16 B8 B10 et D3 D7 y 1 C C y L er et A10 B7 B11 A17 e E h e 3 e 4 1/2 e B1 B17 A1 terminal 1 index area D5 D1 A32 B20 B18 D h A27 A26 D8 et D4 er X et K er 0 5 mm Dimensions Unit A A 1 A 2 b D D h E E h e e 1 e 2 e 3 e 4 er et K L L 1 v w y y 1 mm max nom min 0.50 0.08 0.05 0.02 0.42 0.40 0.38 0.28 0.23 0.18 4.1 4.0 3.9 1.95 1.85 1.75 6.1 6.0 5.9 3.95 3.85 3.75 0.5 1.0 2.5 3.0 4.5 0.5 0.49 0.25 0.20 0.15 0.28 0.23 0.18 0.195 0.145 0.095 0.1 0.05 0.08 0.1 sot1134-2_po Outline version References IEC JEDEC JEITA European projection Issue date SOT1134-2 - - - - - - - - - 11-08-15 Fig 14. Package outline SOT1134-2 (HXQFN60) Product data sheet Rev. 7 8 March 2012 23 of 27

14. Abbreviations Table 16. Acronym CDM DUT ESD HBM MM Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model 15. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes v.7 20120308 Product data sheet - v.6 Modifications: For type number BX the sot code has changed to SOT1134-2. v.6 20111207 Product data sheet - v.5 Modifications: Legal pages updated. v.5 20110616 Product data sheet - v.4 v.4 20101124 Product data sheet - v.3 v.3 20100622 Product data sheet - v.2 v.2 20100318 Product data sheet - v.1 v.1 20100111 Product data sheet - - Product data sheet Rev. 7 8 March 2012 24 of 27

16. Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 16.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Product data sheet Rev. 7 8 March 2012 25 of 27

Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia s specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia s standard warranty and Nexperia s product specifications. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Product data sheet Rev. 7 8 March 2012 26 of 27

18. Contents 1 General description...................... 1 2 Features and benefits.................... 1 3 Ordering information..................... 2 4 Functional diagram...................... 2 5 Pinning information...................... 4 5.1 Pinning............................... 4 5.2 Pin description......................... 6 6 Functional description................... 6 7 Limiting values.......................... 7 8 Recommended operating conditions........ 7 9 Static characteristics..................... 8 10 Dynamic characteristics................. 11 11 Waveforms............................ 15 12 Typical propagation delay characteristics.. 17 13 Package outline........................ 21 14 Abbreviations.......................... 24 15 Revision history........................ 24 16 Legal information....................... 25 16.1 Data sheet status...................... 25 16.2 Definitions............................ 25 16.3 Disclaimers........................... 25 16.4 Trademarks........................... 26 17 Contact information..................... 26 18 Contents.............................. 27 For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 08 March 2012