Lecture #39 ANNOUNCEMENT Pick up graded HW assignments and exams (78 Cory) Lecture #40 will be the last formal lecture. Class on Friday will be dedicated to a course review (with sample problems). Discussion sections this week will cover sample problems (review for the final exam) Deadline for Best Tutebot contest: 1/4 at 8 PM. will hold extra office hours this Thursday afternoon OUTLINE» Transistor scaling» ilicon-on-insulator technology» Interconnect scaling Reading (Rabaey et al.): ections.5.1, 3.5, 5.6 Lecture 39, lide 1 Transistor caling Average minimum L of MOFETs vs. time teady advances in manufacturing technology (particularly lithography) have allowed for a steady reduction in transistor size. ~13% reduction/year (0.5 every 5 years) How should transistor dimensions and supply voltage (V ) scale together? Lecture 39, lide
cenario #1: Constant-Field caling Voltages and MOFET dimensions are scaled by the same factor >1, so that the electric field remains unchanged x j V x j / t ox / V / L / Doping N A N A Lecture 39, lide 3 1.4 Impact of Constant-Field caling (a) MOFET gate capacitance: L W ε ox C L WC ox t ox gate C Circuit speed improves by gate (b) MOFET drive current: W W V V I C ( V V ) ( C ) T ox T ox L L (c) Intrinsic gate delay : C V gate ( Cgate / )( V / ) CgateV 1 I ( I / ) I I Lecture 39, lide 4
Impact of Constant-Field caling (cont d) (d) Device density: area required per transistor W L 1 1 # of transistors per unit area W L W / L/ (e) Power dissipated per device: I V P P I V (f) Power density: 1 P P WL 1 P ( W / )( L/ ) WL ( )( ) WL Power consumed per function is reduced by Lecture 39, lide 5 V T caling Low V T is desirable for high ON current: I (V - V T ) η 1 < η < But high V T is needed for low OFF current: log I D Low V T I OFF,low VT High V T I OFF,high VT V T cannot be aggressively scaled down! 0 V G Lecture 39, lide 6
ince V T cannot be scaled down aggressively, the power-supply voltage (V ) has not been scaled down in proportion to the MOFET channel length: Lecture 39, lide 7 cenario #: Generalized caling MOFET dimensions are scaled by a factor >1; Voltages (V & V T ) are scaled by a factor U >1 L L / ; W W / ; t ox t ox / V V / U (a) MOFET drive current: I C ox W L (b) Intrinsic gate delay: C V gate gate I W V L V U T ( V V T ) ( Cox) ( C / )( V / U) C gate U ( I / U ) I Note: U is slightly smaller than V I U Lecture 39, lide 8
(c) Power dissipated per device: P Impact of Generalized caling I V I U V U (d) Power dissipated per unit area: P 1 P WL U P U 3 3 > 3 3 1 P P ( W / )( L/ ) U WL WL Reliability (due to high E-fields) and power density are issues! Lecture 39, lide 9 Intrinsic Gate Delay (C gate V / I ) V 0.75V 0.85V Lecture 39, lide 10
ilicon-on-insulator (OI) Technology T OI Transistors are fabricated in a thin single-crystal i layer on top of an electrically insulating layer of io impler device isolation savings in circuit layout area Low pn-junction & wire capacitances faster circuit operation No body effect Higher cost Lecture 39, lide 11 Interconnect caling Relevant parameters: wire width W wire length L wire thickness H wire resistivity ρ wire-to-wire spacing Z inter-level dielectric (ILD) thickness t ILD permittivity ε ILD L ρ H Z ρ W t ILD Lecture 39, lide 1
For local (relatively short) interconnects: W, Z and t ILD scale down by H is not scaled avoids significantly increasing R wire, but increases crosstalk L scales down by a factor L Wire capacitance scales by a factor ε c / L, where ε c accounts for the impact of fringing & interwire capacitances For short & medium-length wires, the resistance of the driving logic gate dominates the wire resistance (i.e. R dr >> R wire ), so that the wire delay scales by ε c / L Lecture 39, lide 13 Global Interconnects For global interconnects (long wires used to route V, GND, and voltage signals across a chip), the wire resistance dominates the resistance of the driving logic gate (i.e. R wire >> R dr ) R wire C wire L The length of the longest wires on a chip increases slightly (~0%) with each new technology generation. In order to minimize increases in global interconnect delay, the crosssectional area of global interconnects has not been scaled, i.e. W and H are not scaled down for global interconnects > Place global interconnects in separate planes of wiring Lecture 39, lide 14
Interconnect Technology Trends Reduce the inter-layer dielectric permittivity low-k dielectrics (ε r ) Use more layers of wiring average wire length is reduced chip area is reduced wire delay gate delay increases Intel 0.13µm Process (Cu) ource: Intel Technical Journal Q0 Lecture 39, lide 15