Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br
ual-well Trench-Isolated CMOS Process (Current) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.2
Circuit Symbols for MOS Transistors NMOS G G S B as 4-terminal device S As 3-terminal device Major carriers are electrons PMOS G G S S Major carriers are holes B as 4-terminal device As 3-terminal device Slide 10.3
NMOS Transistor Zero-Order Model (Perfect Switch) S S G = 0 G = 1 S S Switch off (no electric current) S Switch on Electric current flows until =S Slide 10.4
PMOS Transistor Zero-Order Model (Perfect Switch) G = 0 S S S S Switch on Electric current flows until =S G = 1 Switch off (no electric current) S Slide 10.5
NMOS Transistor Structure S + - V GS G Field oxide n + n + p-substrate Gate oxide substrate (bulk) contact Slide 10.6
NMOS Transistor for V GS =0 S + - V GS G n + n + p-substrate p-n junctions are off (0V bias) Extremely high resistance between drain and source Slide 10.7
NMOS Transistor (Increasing V GS ) S V GS + G - n + n + p-substrate Referred to as the MOS Capacitor Slide 10.8
The MOS Capacitor in Accumulation Poly gate Silicon oxide p-substrate V GS > 0 (but V GS <<V T ) Source: R. Reis 1999 Slide 10.9
The MOS Capacitor in epletion epletion region V GS = V T Negative charges repels mobile holes from the channel surface, thus creating a depletion region below the gate oxide (similar to the one occurring in a pn-junction diode). Source: R. Reis 1999 Slide 10.10
The MOS Capacitor in epletion epletion region V GS = V T epletion region width: W d = 2ε siφ qn A Qd = 2qNAεsiφ epletion region space charge per unit: where N A is the substrate doping and is the voltage across the depletion layer (i.e., the potential at the oxide-silicon boundary) φ Slide 10.11
The MOS Capacitor in Strong Inversion Inversion layer epletion region V GS > V T As V GS increases, the potential at the silicon surface reaches a critical value and the silicon surface inverts to n-type material. This point marks the beginning of a phenomenon known as strong inversion, which occurs when V GS equals twice the Fermi Potential ( φ F ~= 0.3V for typical p-type silicon substrates): φ F = φ T ln N A n i Slide 10.12
The MOS Capacitor in Strong Inversion Inversion layer epletion region V GS > V T Further increases in V GS produce no further changes in the depletion region width (but result in additional electrons in the inversion layer, coming from the n+ source region). Slide 10.13
The MOS Capacitor in Strong Inversion In the presence of an inversion layer, the charge stored in the depletion region is fixed and equals: Q B0 = 2qN A ε si 2φ F But when a substrate bias voltage V SB is applied between source and body, the potential required for strong inversion increases, becoming: 2φ F + V SB And the charge stored in the depletion region is then expressed by: Q B = 2qN A ε si (( 2)φ F + V SB ) Slide 10.14
The Threshold Voltage The value of V GS where strong inversion occurs is called the threshold voltage (V T ) V T is function of several components (most are material constants): The oxide thickness The Fermi voltage The charge of impurities trapped at the surface between channel and gate oxide osage of ions implanted for threshold adjustment Slide 10.15
The Threshold Voltage and The Body Effect V SB has an impact on V T! V T under different body-biasing conditions can be calculate by: V T = V T 0 + γ ( ( 2)φ F + V SB 2φ ) where V T0 is the V T for V SB =0, and coefficient. γ is called the body-effect V T0 is positive for NMOS transistor and negative for PMOS transistor Slide 10.16
The Threshold Voltage and The Body Effect Effect of Well Bias on the Threshold of an NMOS Transistor (assuming 2φ F = 0.6V and γ = 0.4V 0.5 ) V BS < 0 is equivalent to V SB > 0 V GS >0 - + G n + n + p-substrate B In NMOS, V SB > 0.6 V to avoid diodes from being forward biased Slide 10.17
Inversion Mode: V GS > V T S V GS + G n + n + p-substrate epletion region Inversion layer (N channel) A channel between drain and source is created But no current flows in such channel Slide 10.18
Linear Region*: V GS > V T and V S < V GS V T (small V S ) S V GS + G V S < V GS V T I S n + n + p-substrate V(x) + L There is a continuous conductive channel between source and drain Current flows from drain to source * Also called Resistive or Nonsaturated or Triode Region Slide 10.19
Linear Region: V GS > V T and V S < V GS V T (small V S ) S V GS + G V S < V GS V T I S p-substrate V(x) + n + n + L If we know the amount of charge in the channel and the rate it moves, we can compute the current in the channel. Slide 10.20 I = ΔQ Δt
Linear Region: V GS > V T and V S < V GS V T (small V S ) S V GS + G V S < V GS V T V(x) + n + n + L I S V GS + V(x) + + V GC x p-substrate At a point x along the channel, the voltage is V(x) and the gate-to-channel voltage ( V GC ) at such point equals V GS V(x). Slide 10.21
Linear Region: V GS > V T and V S < V GS V T (small V S ) S V GS + G V S < V GS V T I S n + n + p-substrate V(x) + L Assuming that V GS V(x) > V T, the induced channel charge per unit area at point x can be computed by: Q i (x) = C ox [ V GS V (x) V T ] where and C ox = ε ox t ox Is the capacitance per unit area of the gate oxide ε ox = 3.97 ε 0 = 3.5 10 11 F /m Slide 10.22
Linear Region: V GS > V T and V S < V GS V T (small V S ) Induced channel charge per unit area at point x (from previous slide): Q i (x) = C ox [ V GS V (x) V T ] I can be computed by: I = v n (x)q i (x)w drift velocity of carries available charge but v n = µ n ξ(x) = µ n dv dx Mobility (m 2 /V.s) Slide 10.23
Linear Region: V GS > V T and V S < V GS V T (small V S ) Combining the 3 equations in the previous slide leads to: Integrating over L leads to: I dx = µ n C ox W(V GS V V T )dv This term can be ignored for small values of V S W I = k' n L (V GS V T )V S V S 2 2 = k n (V GS V T )V S V S 2 2 Process transconductance parameter: k' n = µ n c ox = µ nε ox t ox Transistor gain factor: W k n = k' n L = µ W nc ox L Slide 10.24
Beginning of Saturation : V GS > V T and V S = V GS V T S V GS + G V S = V GS V T I S n + n + p-substrate At points x where V GS V(x) < V T the induced charge is zero and the conducting channel disappears. L V GS V(x=L) < V T and channel is pinched-off Slide 10.25
Saturation Region: V GS > V T and V S > V GS V T S V GS + G V S > V GS V T I S n + V n + GS V T + p-substrate L Voltage difference over the channel (from pinch-off point to source) remains fixed at V GS V T, and I remains constant Slide 10.26
Saturation Region: V GS > V T and V S > V GS V T Replacing V S by V GS V T in the equation below W I = k' n L (V GS V T )V S V S 2 Yields the drain current for the saturation region: 2 I = k' n 2 W L (V GS V T ) 2 Notice: The square dependency I between and V GS I is no longer function of V S Slide 10.27
Channel Length Modulation I = k' n 2 A more accurate description of I is: W L (V GS V T )2 Increasing V S causes the depletion region at the drain junction to grow, reducing the length of the effective channel! I = I '(1+ λv S ) λ is an empirical parameter called channel length modulation (proportional to the inverse of the channel length). Slide 10.28
Velocity Saturation MOSFET When electric field along the channel reaches, the velocity of carriers tends to saturate (due to scattering effects) For a 0.25µm NMOS, only about 2V between drain and source are needed to reach velocity saturation Very pronounced in short-channel NMOS v = ξ c µ nξ 1+ ξ /ξ c for ξ = ξ c v = v sat for ξ = ξ c Continuity requires that: ξ c = 2v sat /µ n Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.29
MOSFET Velocity Saturation (I for Linear Region) Replacing to: ξ c = 2v sat /µ n where κ(v ) = in the I equation for the linear region leads µ I = n C ox W 1+ (V S /ξ c L) L 1 1+ (V /ξ c L) (V GS V T )V S V S 2 = 2 W = µ n C ox (V L GS V T )V S V S 2 κ(v S ) 2 measures the degree of saturation and V S /L can be interpreted as the average field in the channel For long-channel devices (large L) or small V S, κ 1 For short-channel devices, κ <1 and the derived current is less than it would normally be Slide 10.30
Velocity Saturation (I for Saturation Region) Increasing V S the electric field in the channel ultimately reaches the critical value and the carriers at the drain become velocity saturated. Assuming that drift velocity is saturated (= v sat ) in the former equation: I SAT = v sat C ox W(V GT VSAT) W = κ(v SAT )µ n C ox V L GT V SAT V S 2 2 where V SAT = κ(v GT )V GT (with V GT = V GS V T ) measures the degree of saturation Slide 10.31
Velocity Saturation (Perspective) For short-channel devices and for large enough values of V GT, is substantially less than 1 and thus V SAT < V GT κ(v GT ) The saturation current I SAT displays a linear dependency w.r.t. V GS Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.32
Velocity Saturation Revisited Approximations made to simplify manual calculation 1. Velocity saturates abruptly at v = µ n ξ ξ c for ξ = ξ c v = v sat = µ n ξ c for ξ = ξ c 2. V SAT at which the critical electric field is reached and velocity saturation comes into play is constant and approximated as V SAT Lξ c = Lv sat µ n Slide 10.33
Velocity Saturation Revisited 1. Current equations for resistive region remain the same as for long-channel devices: W I = k' n L (V GS V T )V S V S 2 2 = k n (V GS V T )V S V S 2 2 2. Once V SAT is reached the current abruptly saturates: I SAT = I (V S = V SAT ) W = µ n C ox (V L GS V T )V SAT V SAT 2 2 = v sat C ox W V GS V T V SAT 2 2 Slide 10.34
I -V S Characteristics of NMOS (I-V Curves) I (A 6 x 10-4 VGS = 2.5 V 5 4 3 2 1 V S = V GS - V T Resistive Saturation V GS = 2.0 V V GS = 1.5 V V GS = 1.0 V Quadratic dependence on V GS I (A 2 1.5 1 0.5-4 x 10 2.5 V S = V GS - V T V = 2.5 V GS V SAT = κ(v GT )V GT Velocity Saturation V GS = 2.0 V V GS = 1.5 V V GS = 1.0 V Linear dependence on V GS 0 0 0.5 1 1.5 2 2.5 V S (V) Long-channel NMOS (W/L = 1.5 and L d =10 µm) 0 0 0.5 1 1.5 2 2.5 V S (V) Short-channel NMOS (W/L=1.5 and L d =0.25 µm) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.35
I -V GS Characteristics of NMOS (I-V Curves) 6 x 10-4 V S = 2.5 V (NMOS devices are saturated) 2.5 x 10-4 I (A) 5 4 3 2 1 Subthreshold conductance 0 0 0.5 1 1.5 2 2.5 Source: Rabaey; Chandrakasan; Nikolic, 2003 quadratic V GS (V) Long-channel NMOS (W/L = 1.5 and L d =10 µm) I (A 2 1.5 1 0.5 Subthreshold conductance quadratic linear 0 0 0.5 1 1.5 2 2.5 V GS (V) Short-channel NMOS (W/L=1.5 and L d =0.25 µm) Slide 10.36
I -V S Characteristics of PMOS 0" x 10"-4" V GS = -1.0V I (A -0.2" -0.4" -0.6" V GS = -1.5V V GS = -2.0V The polarities of all voltages and currents are reversed -0.8" V GS = -2.5V -1" -2.5" -2" -1.5" -1" -0.5" 0" V S (V) Short-channel PMOS (W d =0.375 and L d =0.25 µm, W/L=1.5 ) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.37
NMOS x PMOS (I-V Curves) Minimum-size (short-channel) NMOS and PMOS (W d =0.375 and L d =0.25 µm, W/L=1.5 ) -4 x 10 2.5 V S = V GS - V T V = 2.5 V GS 2 1.5 V SAT = κ(v GT )V GT Velocity Saturation V GS = 2.0 V -0.2" -0.4" 0" x 10"-4" V GS = -1.0V V GS = -1.5V I (A 1 V GS = 1.5 V I (A -0.6" V GS = -2.0V 0.5 V GS = 1.0 V -0.8" V GS = -2.5V 0 0 0.5 1 1.5 2 2.5 V S (V) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.38-1" -2.5" -2" -1.5" -1" -0.5" 0" V S (V) Velocity saturation is less pronounced in PMOS (due to higher value of critical electrical field, resulting from smaller mobility of holes)
References MOSFET 1. RABAEY, J; CHANRAKASAN, A.; NIKOLIC, B. igital Integrated Circuits: a design perspective. 2 nd Edition. Prentice Hall, 2003. ISBN: 0-13-090996-3. 2. WESTE, Neil; HARRIS, avid. CMOS VLSI esign: a circuits and systems perspective. Addison-Wesley, 4 th Edition, 2010. ISBN 978-0321547743. Slide 10.39