ECE260B CSE241A Winter 2005 Parasitic Extraction Website: / courses/ ece260bw05 ECE 260B CSE 241A Parasitic Extraction 1
Conventional Design Flow Funct. Spec RTL Behav. Simul. Logic Synth. Stat. Wire Model Front-end Gate-level Net. Gate-Lev. Sim. Back-end Floorplanning Place & Route Parasitic Extrac. ECE 260B CSE 241A Parasitic Extraction 2 Layout
Technology Scaling Process technology evolves with shrinking feature sizes Parasitic effects become more significant with smaller feature sizes Increasing wire resistance, fringing and coupling capacitances... Interconnect delay dominates VLSI system performance The performance of today s DSM ICs is strongly determined by the parasitic effects of the passive structures interconnecting active devices Accurate, high-speed tools and methods are needed to extract and simulate these parasitic effects in order to perform precise timing analysis to the circuit ECE 260B CSE 241A Parasitic Extraction 3
Layout Parasitic Extraction Necessary step after routing Back-annotation Account for non-ideal nature of interconnect Wire capacitance Wire and via resistance Parasitic information is used in post-layout verification Timing verification of synchronous circuits Functional verification of asynchronous circuits Design performance is ultimately limited by parasitics ECE 260B CSE 241A Parasitic Extraction 4
Parasitic Extraction: Why do we need it? Example: to produce RC tree network for elmore delay analysis s R 1 C 1 1 R 2 R 3 C 3 3 2 C 2 R 4 R i 4 C 4 i C i Example: to produce RC tree network for capacitive cross-talk analysis ECE 260B CSE 241A Parasitic Extraction 5
Parasitic Extraction thousands of wires e.g. critical path e.g. gnd/vdd grid identify some ports produce equivalent circuit that models response of wires at those ports ECE 260B CSE 241A Parasitic Extraction 6 Parasitic Extraction tens of circuit elements for gate level spice simulation
Parasitic Extraction (the two steps) Electromagnetic Analysis thin volume filaments with constant current small surface panels with constant charge million of elements Model Order Reduction tens of elements ECE 260B CSE 241A Parasitic Extraction 7
Parasitic Extraction / Back-Annotation Input data Technology data - Metal and via resistances - Capacitance coefficients Library data - Input pin capacitances Design data - Routing - Boundary conditions (load and drive information) Output data Parasitic information: - DSPF - RSPF - Set_load Interpreted parasitic information - Custom WLM - LEF coefficients ECE 260B CSE 241A Parasitic Extraction 8
Active Device Parasitics Gate output capacitance mainly from gate oxide t ox Substrate coupling resistances and capacitances Characterized by cell libraries ECE 260B CSE 241A Parasitic Extraction 9 Figure courtesy, A. Nardi
Interconnect Parasitics Wires are not ideal. Parasitics: Resistance Capacitance Inductance Why do we care? Impact on delay noise energy consumption power distribution Picture from Digital Integrated Circuits, Rabaey, Chandrakasan, Nikolic ECE 260B CSE 241A Parasitic Extraction 10
SEMATECH Prototype BEOL stack, 2000 Global (up to 5) Via Wire Passivation Dielectric Etch Stop Layer Dielectric Capping Layer Intermediate (up to 4) Copper Conductor with Barrier/Nucleation Layer Local (2) Pre Metal Dielectric Tungsten Contact Plug Slide courtesy of Chris Case, BOC Edwards ECE 260B CSE 241A Parasitic Extraction 11
Interconnect Resistance R = ρ L T W T L Sheet Resistance R W R 1 R 2 Resistance seen by current going from left to right is same in each block ECE 260B CSE 241A Parasitic Extraction 12
Resistance Scaling Resistance scales badly True scaling would reduce width and thickness by S each node R ~S 2 for a fixed line length and material Reverse scaling wires get smaller and slower, devices get smaller and faster At higher frequencies, current crowds to edges of conductor (thickness of conduction = skin depth) increased R ECE 260B CSE 241A Parasitic Extraction 13
Interconnect Capacitance Lateral cap w S Line dimensions: W, S, T, H Sometimes H is called T in the literature, which can be confusing ECE 260B CSE 241A Parasitic Extraction 14
Capacitance Estimation Empirical capacitance models are easiest and fastest Handle limited configurations (e.g., range of T/H ratio) Some limiting assumptions (e.g., no neighboring wires) C wire = ox[ Capacitance per unit length W H 0. 77 1. 06 ILD W H ILD 5] 0. 25 1. 06 T 0. wire H ILD Rules of thumb: e.g., 0.2 ff/um for most wire widths < 2um Cf. MOSFET gate capacitance ~1 ff/um width Pattern-matching approaches applied to multilayer crosssections ECE 260B CSE 241A Parasitic Extraction 15
Inductance Inductance is the flux induced by current variation Measures ability to store energy in the form of a magnetic field Consists of self-inductance and mutual inductance terms At high frequencies, can be significant portion of total impedance Z = R + jωl (ω = 2πf = angular freq) ECE 260B CSE 241A Parasitic Extraction 16 S 1 S 2 I 11 = S 1 B 1 ds 1 Self Inductance = 11 d I d 12 = S 2 B 1 ds 2 Mutual Inductance d = 12 d I
Coil Inductance V = L d I/d t V 2 = M 12 d I 1 /d t Faraday s law V = N d (B A) / d t B = µ (N / l) I L = µ N 2 A / l V = voltage N = number of turns of the coil B = magnetic flux A = area of magnetic field circled by the coil l = height of the coil t = time ECE 260B CSE 241A Parasitic Extraction 17
Filament Inductance l i l j L = dv ' dv ij 4 ai a r r ' j V ' i V j Where the integral is over the volume of the conductors, r is the position in a given filament, and l i is the unit vector in the direction of current flow for conductor i ECE 260B CSE 241A Parasitic Extraction 18
Inductance Scaling If L R where =2 f =2 1 t r Copper interconnects R is reduced Faster clock speeds Thick, low-resistance (reverse-scaled) global lines Chips are getting larger long lines large current loops Frequency of interest is determined by signal rise time, not clock frequency Massoud/ ECE Sylvester/ 260B CSE Kawa, 241A Synopsys Parasitic Extraction 19 Slide courtesy of Massoud/Sylvester/ Kawa, Synopsys
Inductance Trends Inductance = weak (log) function of conductor dimensions Inductance = strong function of distance to current return path (e.g., power grid) Want nearby ground line to provide a small current loop (cf. Alpha 21164) Inductance most significant in long, low-r, fast-switching nets Clocks are most susceptible ECE 260B CSE 241A Parasitic Extraction 20
Inductance is Important On-chip inductance is negligible, and usually alleviate performance degradation due to the presence of capacitance Seesaw effect between inductance and capacitance Package inductance is significant when coupled with large magnitude of currents in the same frequency range Complete analysis needs to include package inductance since signals cannot be assumed ideal at pads For the idealized case of a lossless homogeneous dielectric with an array of conductors, the inductance matrix [L] can be derived directly from the capacitance matrix [C] by [ L ]= 1 v 0 2 [C ] 1 where v 0 is the phase velocity of the medium However in the IC domain, these assumptions do not hold up and we need inductance extraction ECE 260B CSE 241A Parasitic Extraction 21
Inductance Return Path Inductance is a loop quantity Knowledge of return path is required, but hard to determine Signal Line Return Path For example, the return path depends on the frequency Massoud/ ECE Sylvester/ 260B CSE Kawa, 241A Synopsys Parasitic Extraction 22 Slide courtesy of Massoud/Sylvester/ Kawa, Synopsys
Frequency-Dependent Return Path At low frequency, minimize impedance minimize resistance R >> L and current tries to R j L use as many returns as possible (parallel resistances) Gnd Gnd Gnd Signal Gnd Gnd Gnd At high frequency, minimize impedance minimize inductance R << L and current tries to R j L use smallest possible loop (closest return path) L dominates, current returns collapse Power and ground lines always available as low-impedance current returns Gnd Gnd Gnd Signal Gnd Gnd Gnd ECE 260B CSE 241A Parasitic Extraction 23 Slide courtesy of Massoud/Sylvester/ Kawa, Synopsys
Extracting Inductance vs. Capacitance Capacitance Locality problem is easy: electric field lines suck up to nearest neighbor conductors Boundary element approach requires discretization of only the surfaces of conductors Charge density over the conductor is rarely uniform, needs to solve the integral form of Laplace s equation for many times Inductance Locality problem is hard: magnetic field lines are not local; current returns can be complex Local calculation is easy: no strong geometry dependence; analytic formulae work very well Current density and direction is constant in each conductor when the frequency is low enough to ignore the skin effect Conductors are divided into bundles of filaments each with a constant current density, compute a circuit solution for return current distribution ECE 260B CSE 241A Parasitic Extraction 24
Outline Problem Statement Parasitics Extraction Methods Resistance extraction Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave) Future Trends ECE 260B CSE 241A Parasitic Extraction 25
Interconnect Resistance Extraction Sheet resistance R Series resistance R = R * Length / Width / Thickness Inaccuracies arise in irregular geometries, e.g., corners of a route Apply Laplace s equation 2 Φ=0, or 2 x 2 2 y 2 2 z 2 =0 Discretize an interconnect conductor into grids ij E V i V j R ij =0 Solve a partial differential equation with known boundary conditions Table Lookup for better efficiency ECE 260B CSE 241A Parasitic Extraction 26
Outline Problem Statement Parasitics Extraction Methods Resistance extraction Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave) Future Trends ECE 260B CSE 241A Parasitic Extraction 27
Parasitic Extraction Accuracy Above 0.5 m feature size, wire cross-section was rectangular Interconnect modeled as parallel plate over ground plane Parallel plate capacitance Fringe capacitance 2-D extraction accurate enough: Area + Fringe C_parallel C_fringe C_fringe ECE 260B CSE 241A Parasitic Extraction 28
Capacitance Extraction 2-D extraction Wire cap includes parallel plate (area), fringing, and coupling cap C = k 1 Area + k 2 Perimeter + k 3 Coupling_length / Coupling_spacing These coefficients are fit in for an average environment of a wire Table Lookup Intra-layer capacitances are not well modeled 3-D extraction Solve for real 3-D geometries of wiring 2.5-D extraction Compromise between speed and accuracy Models 3-D effects by a combination of two orthogonal 2-D structures E.g., two cross-section views on the x-z and y-z planes, z is the vertical axis going through layers ECE 260B CSE 241A Parasitic Extraction 29
How Capacitance Extractor Works Technology pre-characterization generates coefficients through solving the 3-D equations for representative sample of topologies Really, cross-sections through tunnel that contains a section of the victim net Creates look-up table Time consuming, but only done once Each layer of interconnect added roughly doubles time for coefficient generation Pattern compression Reduces the total number of pre-characterization patterns Geometric parameter extraction Reduce the number of geometric parameters considering the shielding effect Extraction matches topologies to entries in look-up table ECE 260B CSE 241A Parasitic Extraction 30
Extraction to Floating Metal Dummy fills (as floating metals) are required by modern CMP process Extraction to floating metal similar to extraction for cross talk analysis Net to net capacitance required Effective capacitance to floating metal dependent on potential of floating metal E.g., Cadence HyperExtract models floating metal as grounded If we model floating metal as grounded, this is pessimistic Below 0.18µm with local fill requirements, fill metal can impact timing ECE 260B CSE 241A Parasitic Extraction 31 Floating metal
Capacitive Extraction Example: Intel 0.25 micron Process 5 metal layers Ti/ Al - Cu/Ti/ TiN Polysilicon dielectric. Taken from Digital Integrated Circuits, 2nd Edition, Rabaey, Chandrakasan, Nikolic fringing parallel ECE 260B CSE 241A Parasitic Extraction 32 Consider only electric field (capacitive) coupling
Capacitive Extraction Why? E.g. Analysis of Delay of Critical Path ECE 260B CSE 241A Parasitic Extraction 33
Capacitance Extraction Problem Formulation Given a collection of N conductors (of any shape and dimension) Calculate the coupling capacitance matrix C fringing parallel q v = [ C =? ] ECE 260B CSE 241A Parasitic Extraction 34
Capacitance Extraction Solution Procedure For i = 1 to N, apply one volt to conductor i and ground all the others solve the electrostatic problem and find the resulting vector of charges on all conductors that is the i-th column of the conductance matrix q=? q i =? q=? q=? q=? v i =1 [ C 1, i C 2, i C N,i ][0 1 0 ]=[ ] q1 q N q 2 ECE 260B CSE 241A Parasitic Extraction 35 q=? 2 =
Overview Problem Statement Parasitics Extraction Methods Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave) Future Trends ECE 260B CSE 241A Parasitic Extraction 36
Inductance and Resistance Extraction Example: IC package Picture Thanks to Coventor lead frames wire bonding IC package ECE 260B CSE 241A Parasitic Extraction 37
Inductance and Resistance Extraction Where do we need to account for inductance? chip to package and package to board connections are highly inductive inductance can create Ldi/dt noise on the gnd/vdd network inductance can limit communication bandwidth inductive coupling between leads or pins can introduce noise pins or solder balls from package to PCB wire bonding and lead frames or solder balls from IC to package PCB package IC on-board decoupling capacitors ECE 260B CSE 241A Parasitic Extraction 38 on-package decoupling capacitors
Inductance and Resistance Extraction Why also resistance? Skin and Proximity effects Simple Example proximity effect: opposite currents in nearby conductors attract each other skin effect: high frequency currents crowd toward the surface of conductors ECE 260B CSE 241A Parasitic Extraction 39
Inductance and Resistance Extraction Skin and Proximity effects (cont.) Why do we care? Skin and proximity effects change interconnect resistance and inductance hence they affect performance (propagation delay) and noise (magnetic coupling) When do we care? frequency is high enough that wire width OR thickness are less than two skin-depths e.g. on PCB at and above 100MHz e.g. on packages at above 1GHz e.g. on-chip at and above 10GHz note. clock at 3GHz has significant harmonics at 10GHz!! ECE 260B CSE 241A Parasitic Extraction 40
Inductance and Resistance Extraction Problem Formulation Given a collection of interconnected N wires of any shape and dimension Identify the M input ports Calculate the MxM resistance and the inductance matrices for the ports, Picture by M. Chou that is the real and immaginary part of the impedance matrix v [ R=? ] j [ L=? ] i = ECE 260B CSE 241A Parasitic Extraction 41
Inductance and Resistance Extraction Solution Procedure Typically instead of calculating impendance we calculate the admittance matrix. For each pair of input terminals, apply a unit voltage source and solve magneto quasit-static problem (MQS) to calculate all terminal currents that is one column of the admittance matrix [R+jwL] -1 ECE 260B CSE 241A Parasitic Extraction 42 [ [ R j L ] 1 [ v ]=[i ] [ Z ] 1 [ v ]=[i ] [Y ] [ v ]=[i ] 2 A= J J j A= J =0 Y 1, i Y 2, i ][0 Y M,i ]=[ i1 1 i M] 2 0 i
Overview Problem Statement Parasitics Extraction Methods Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave) Future Trends ECE 260B CSE 241A Parasitic Extraction 43
Combined RLC Extraction Example: current distributions on powergrid input terminals ECE 260B CSE 241A Parasitic Extraction 44
Combined RLC Extraction Example: analysis of resonances on powergrid * 3 proximity templates per cross-section - 20 non-uniform thin filaments per cross-section ECE 260B CSE 241A Parasitic Extraction 45
Combined RLC Extraction Extraction Example: analysis of substrate coupling ECE 260B CSE 241A Parasitic Extraction 46
Combined RLC Extraction Example: resonance of RF microinductors At frequency of operation the current flows in the spiral and creates magnetic energy storage (it works as an inductor: GOOD) But for higher frequencies the impedance of the parasitic capacitors is lower and current prefers to jump from wire to wire as displacement currents (it works as a capacitor: BAD) Picture thanks to Univ. of Pisa ECE 260B CSE 241A Parasitic Extraction 47
Combined RLC Extraction Problem Formulation Given a collection of interconnected N wires of any shape and dimension Identify the M input ports Calculate the MxM IMPEDANCE matrix for the ports, Picture by M. Chou that is the real and immaginary part of the impedance matrix v i = [ Z =? ] ECE 260B CSE 241A Parasitic Extraction 48
Combined RLC Extraction Solution Procedure Same as RL extraction. Typically calculate admittance matrix For each pair of input terminals, apply a unit voltage source and solve electro-magneto quasit-static problem (EMQS) to calculate all terminal currents that is one column of the admittance matrix [R+jwL] -1 [ Y 1, i Y 2, i ]=[ i1 1 i 0 ][0 M] 2 Y M,i i [Y ] [ v ]=[i ] 2 = 2 A= J J j A= J =0 n J = j ECE 260B CSE 241A Parasitic Extraction 49
Outline Problem Statement Parasitics Extraction Methods Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave) Future Trends ECE 260B CSE 241A Parasitic Extraction 50
The Electromagnetic Interference (EMI) Problem description Electronic circuits produce and are subject to Electromagnetic Interference (EMI). in particular when wavelengths ~wire lengths EMI is a problem because it can severely and randomly affect analog and digital circuit functionality!!! IC IC PC B PCB ECE 260B CSE 241A Parasitic Extraction 51
EMI analysis EMI at board, package and IC level Traces on PCB can pick up EMI and transmit it to IC s IC s can produce high frequency conducted emissions that can radiate from PCB s IC s themselves can directly produce radiated emissions high-frequency current loops Vdd-decap-gnd on package or inside IC s. high-frequency current loops inside IC (near future) IC radiation amplified by heat sinks! IC PCB IC PCB IC ECE 260B CSE 241A Parasitic Extraction 52
EMI a problem for ICs design? So far: dimensions too small and wavelengths too large Trend: larger chip dies and higher frequencies Today s PCB: clocks ~ 300MHz harmonics ~3GHz wavelengths ~10cm dimensions ~10cm d this gives resonances on PCB today, hence it might on IC tomorrow! ECE 260B CSE 241A Parasitic Extraction 53 Future s IC: clocks harmonics wavelengths dimensions ~30GHz ~1cm ~1cm ~3GHz d
EMI analysis Solution Procedure Typically, EMI analysis is a two-step process: 1) determine accurate current distributions on conductors I 1 I 2 2) calculate radiated fields from the current distributions E I 1 I 2 ECE 260B CSE 241A Parasitic Extraction 54
Need for full-board analysis Interconnect impedances depend on complicated return paths. Unbalanced currents generate most of the interference. I 1 I 2 I 1 Hence need FULL-BOARD analysis ECE 260B CSE 241A Parasitic Extraction 55
Need for full-wave analysis Circuit dementions are not negligible compared to wavelength di i dt coupling NOT instantaneus, speed of light creates retardation d v j =L i, j di i dt t c d Need to solve FULLWAVE equations (same as for RLC extraction plus wave term) 2 2 = 2 A 2 = J J j A= ECE 260B CSE 241A Parasitic Extraction 56 J =0 n J = j
Industry Mentor xcalibre Synopsys Raphael Cadence Simplex Fire & Ice, Celestry Nautilus Frequency Columbus MIT FastCap, FastHenry, etc. http://rel-vlsi.mit.edu/ fastcap ECE 260B CSE 241A Parasitic Extraction 57
Outline Problem Statement Parasitics Extraction Methods Capacitance Extraction (electrostatic) RL Extraction (MQS) Combined RLC Extraction (EMQS) Electromagnetic Interference Analysis (fullwave) Future Trends ECE 260B CSE 241A Parasitic Extraction 58
Future Trends Accuracy and efficiency improvement to handle increasing large designs and increasing complex structures Growing inductance effect What happen on PCB today will be in ASIC tomorrow Combining parasitic extraction and model order reduction to characterize interconnect in Laplace domain transfer function parameters (poles, residues) directly ECE 260B CSE 241A Parasitic Extraction 59
Parasitic Extraction (the two steps) Electromagnetic Analysis thin volume filaments with constant current small surface panels with constant charge million of elements Model Order Reduction ECE 260B CSE 241A Parasitic Extraction 60 tens of elements
Thanks ECE 260B CSE 241A Parasitic Extraction 61