32K x 8 EEPROM - 5 Volt, Byte Alterable

32K x 8 EEPROM - 5 Volt, Byte Alterable Description The is a high performance CMOS 32K x 8 E 2 PROM. It is fabricated with a textured poly floating gate technology, providing a highly reliable 5 Volt only nonvolatile memory. The supports a 128-byte page write operation, effectively providing a 24ms/byte write cycle and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the is specified as a minimum 100,000 write cycles per byte and an inherent data retention of 100 years. A 14 A 12 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 I / O 0 I / O 1 I / O 2 V S S Ce r DIP o r F l a t Pa c k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M Y X 28 C 32K 8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 V C C A 13 A 8 A 9 A 11 O E # A 10 I / O 7 I / O 6 I / O 5 I / 0 4 I / O 3 A 6 A 5 A 4 A 3 A 2 A 1 A 0 N C I / O 0 Ce r SOJ o r Ce r LCC A 7 A 12 A 14 N C V C C A 13 4 3 2 1 32 31 30 5 6 7 8 9 10 11 12 13 M Y X 28 C 32K 8 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 I / O 1 I / O 2 V S S N C I / O 3 I / O 4 I / O 5 A 8 A 9 A 11 N C O E # A 10 I / O 7 I / O 6 Figure 1 - Pin Configuration Ce r PG I/O 1 I/O 2 I/O 3 I/O 5 I/O 6 12 13 15 17 18 I/O 0 A 0 V SS I/O 4 I/O 7 11 10 14 16 19 A 1 A 2 CE A 10 9 8 20 21 A 3 A 4 OE A 11 7 6 22 23 A 5 A 12 V CC A 9 A 8 5 2 28 24 25 A 6 A 7 A 14 WE A 13 4 3 1 27 26 A Features Access Time (ns): 70, 90, 120, 150 Simple Byte and Page Write Single 5V Supply No External High Voltages or VPP Control Circuits Self-Timed No Erase Before Write No Complex Programming Algorithms No Overerase Problem Low Power CMOS: Active: 60mA Standby: 500mA Software Data Protection Protects Data Against System Level Inadvertent Writes High Speed Page Write Capability Highly Reliable Direct Write Cell Endurance: 100,000 Write Cycles Data Retention: 100 Years Early End of Write Detection DATA Polling Toggle Bit Polling Timing Packages Operating Temp. Options 70 ns access 90 ns access 120 ns access 150 ns access Ceramic fl at pack CerDIP, 600 mil CerLCC CerPGA CerSOJ Military (-55 C to +125 C) Industrial (-40 C to +85 C) Markings -7-9 -12-15 F CW ECA P ECJ XT IT Revision 1.4-02/13 1

Pin Descriptions Addresses (A0 A14) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE#) Table 1 - Pin Names Parameter A 0 -A 14 I/O 0 -I/0 7 WE# Symbol Address Inputs Data Input/Output Write Enable The Chip Enable input must be LOW to enable all read/write operations. When CE# is HIGH, power consumption is reduced. Output Enable (OE#) CE# Chip Enable OE# Output Enable V CC +5V The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O 0 I/O 7 ) Data is written to or read from the through the I/O pins. V SS NC Figure 2 - Functional Diagram Ground No Connect Write Enable (WE#) The Write Enable input controls the writing of data to the. A 0 A 14 A D D R E S S I N P U T S X B U F F E R S L A T C H E S A N D D E C O D E R 25 6 K - B I T E E P R O M A R R A Y Y B U F F E R S L A T C H E S A N D D E C O D E R I / O B U F F E R S A N D L A T C H E S O E # C O N T R O L L O G I C A N D T I M I N G I / O0 I / O7 D A T A I N P U T S / O U T P U T S V C C V S S Revision 1.4-02/13 2

Device Operation Read Read operations are initiated by both OE# and CE# LOW. The read operation is terminated by either CE# or OE# returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE# or CE# is HIGH. Write Write operations are initiated when both CE# and WE# are LOW and OE# is HIGH. The supports both a CE# and WE# controlled write cycle. That is, the address is latched by the falling edge of either CE# or WE#, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE# or WE#, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 3ms. Page Write Operation The page write feature of the allows the entire memory to be written in typically 0.8 seconds. Page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE# HIGH to LOW transition, must begin within 100ms of the falling edge of the preceding WE#. If a subsequent WE# HIGH to LOW transition is not detected within 100ms, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100ms. Write Operation Status Bits The provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 3. Figure 3 - Status Bit Assignment I / O DATA Polling (I/O 7 ) D P T B 5 4 3 2 1 0 R E S E R V E D T O G G L E B I T D A T A P O L L I N G The features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O 7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O 7 will reflect true data. Toggle Bit (I/O 6 ) The also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O 6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read and write operations. Revision 1.4-02/13 3

DATA Polling I/O 7 Figure 4 - Data Polling Bus Sequence L A S T W R I T E O E # V I H H I G H Z V I / O O H 7 V O L M Y X X 28 H C 25 6 R E A D Y A 0 A 14 A n A n A n A n A n A n A n Figure 5 - Data Polling Software Flow W R I T E A DTA DATA Polling can effectively halve the time for writing to the. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates one method of implementing the routine. W R I T E S C O M P L E T E? N O Y E S S A V E L A S A T TA D A N D A D D R E S S R E A D L A S T A D D R E S S I O 7 C O M P A R E? Y E S N O M Y X X 28 H C 25 6 R E A D Y Revision 1.4-02/13 4

The Toggle Bit I/O 6 Figure 6 - Toggle Bit Bus Sequence L A S T W R I T E O E # I / O 6 * V O H H I G H Z * V O L M Y X X 28 H C 25 6 R E A D Y * I / 6 O b e g i n n i n g a n d e n d i n g 6 s t a t e o f I / O Figure 7 - Toggle Bit Software Flow L A S T W R I T E Y E S L O A D A C C U M F R O M A D D R n The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple memories that is frequently updated. The timing diagram in Figure 6 illustrates the sequence of events on the bus. The software flow diagram in Figure 7 illustrates a method for polling the Toggle Bit. C O M P A R E A C C U M W I T H A D D R n C O M P A R E O K? N O Y E S M Y X X 28 H C 25 6 R E A D Y Revision 1.4-02/13 5

Hardware Data Protection The provides two hardware features that protect nonvolatile data from inadvertent writes. Default V CC Sense - All write functions are inhibited when V CC is 3.5V Typically. Write Inhibit - Holding either OE# LOW, WE# HIGH, or CE# HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. Software Data Protection The offers a software controlled data protection feature. The is shipped from Micross with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the use of external circuits. The host would then have open read and write access of the device once V CC was stable. The can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. Software Algorithm Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 9 and 10 for the sequence. The three-byte sequence opens the page write window enabling the host to write from one to one hundred twentyeight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. Revision 1.4-02/13 6

Software Data Protection Figure 8 - Timing Sequence - Byte or Page Write V C C 0 V ( V C C ) D A TA A D D R E S S A A 5 5 2A A A A 0 W R I T E S O K t W C W R I T E P R O T E C T E D t B L C M A X B Y T E O R P A G E Figure 9 - Write Sequence for Software Data Protection W R I T E D A T A A A T O A D D R E S S W R I T E D A T A 5 5 T O A D D R E S S 2A A A W R I T E D A T A A 0 T O A D D R E S S W R I T E D A T A X X T O A N Y A D D R E S S O P T I O N A L B Y T E O R W R I T E L A S T B Y T E TO L A S T A D D R E S S B Y T E / P A G E L O A D E N A B L E D P A G E W R I T E A L L O W E D Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the will be write protected during power-down and after any subsequent power-up. Note: Once initiated, the sequence of write operations should not be interrupted. A F T E R W Ct R E - E N T E R S D A T A P R O T E C T E D S T A T E Revision 1.4-02/13 7

Resetting Software Data Protection Figure 10 - Reset Software Data Protection Timing Sequence V C C D A T A A D D R E S S A A 5 5 2A A A 8 0 A A 5 5 2A A A 20 t W C S T A N D A R D O P E R A T I N G M O D E Figure 11 - Write Sequence for Resetting Software Data Protection W R I T E D A T A A A T O A D D R E S S W R I T E D A T A 5 5 T O A D D R E S S 2A A A W R I T E D A T A 8 0 T O A D D R E S S In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After t WC, the will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted. W R I T E D A T A A A T O A D D R E S S W R I T E D A T A 5 5 T O A D D R E S S 2A A A W R I T E D A T A 20 T O A D D R E S S A F T E R W C t, R E - E N T E R S U N P R O T E C T E D S T A T E Revision 1.4-02/13 8

System Considerations Because the is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit it is recommended that CE# be decoded from the address bus and be used as the primary device selection input. Both OE# and WE# would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. Because the has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE# will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the l/os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between V CC and V SS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between V CC and V SS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. Revision 1.4-02/13 9

Table 2 - Absolute Maximum Ratings* Temperature under bias -10 C to +85 C -65 C to +135 C Storage temperature -65 C to +150 C Voltage on any pin with respect to V SS -1V to +7V DC output current 10mA Lead temperature (soldering, 10 sec.) 300 C Supply voltage 5V ±10% *Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3 - Recommended Operating Conditions Temperature Min. Max. Commerical 0 C +70 C Industrial -40 C +85 C Military -55 C +125 C Table 4 - DC Operating Characteristics Over the recommended operating conditions unless otherwise specified. Symbol Parameter Limits Min. Typ. 1 Max. Units Test Conditions I CC V CC Active Current (TTL Inputs) 30 60 ma CE# = OE# = V IL ; WE# = V IH All I/O s = Open; Address Inputs =.4V/2.4V Levels @ f = 10MHz I SB1 V CC Standby Current (TTL Inputs) 1 2 CE# = V IH ; OE# = V IL ; All I/O s = Open; Other Inputs = V IH I SB2 V CC Standby Current (CMOS Inputs) 200 500 CE# = V CC - 0.3V; OE# = GND; All I/O s = Open; Other Inputs = V CC - 0.3V I LI Input Leakage Current 10 µa V IN = V SS to V CC ; CE# = V IH I LO Output Leakage Current 10 V OUT = V SS to V CC ; CE# = V IH V IL 2 Input LOW Voltage -1 0.8 V IH 2 Input HIGH Voltage 2 V CC +1 V V OL Output LOW Voltage 0.4 I OL = 6mA V OH Output HIGH Voltage 2.4 I OH = -4mA 1. Typical values are for T A = 25 C and nominal supply voltage. 2. V IL min. and V IH max. are for reference only and are not tested. Revision 1.4-02/13 10

Table 5 - Power-Up Timing Symbol Parameter Max. Units t PUR 1 Power-Up to Read 100 µs t PUW 1 Power-Up to Write 5 ms 1. This parameter is periodically sampled and not 100% tested. Table 6 - Capacitance T A = +25 C; f = 1MHz; V CC = 5V Symbol Test Max. Units Conditions C I/O Input/Output Capacitance 10 V I/O = OV pf C IN Input Capacitance 6 V IN = OV Table 7 - Endurance and Data Retention Parameter Min. Max. Units Endurance 100,000 Cycles Data Retention 100 Years Table 8 - AC Conditions of Test Input Pulse Levels 0V to 3V Input Rise and Fall Times 5ns Input and Output Timing Levels 1.5V Table 9 - Mode Selection CE# OE# WE# Mode I/O Power L H Read D OUT L Active H L Write D IN H X X Standby & Write Inhibit High Z Standby L X X Write Inhibit X H Revision 1.4-02/13 11

Figure 12 - Equivalent AC Load Circuit Figure 13 - Symbol Table O U T P U T 5 V 1. 9 2KΩ 1. 37 KΩ 30 p F WAVEFORM INPUTS OUTPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don t Care: Changes Allowed N/A Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance Revision 1.4-02/13 12

AC Characteristics Over the recommended operating conditions unless otherwise specified. Table 10 - Read Cycle Limits Symbol Parameter -70-90 -12-15 Min. Max. Min. Max. Min. Max. Min. Max Units t RC Read Cycle Time 70 90 120 150 t CE t AA Chip Enable Access Time Address Access Time 70 90 120 150 t OE Output Enable Access Time 35 40 50 50 t LZ 1 t OLZ 1 CE# LOW to Output Active OE# LOW to Output Active 0 0 0 0 ns t HZ 1 t OHZ 1 CE# HIGH to High Z Output OE# HIGH to High Z Output 35 40 50 50 t OH Output Hold from Address Change 0 0 0 0 1. t LZ min., t HZ, t OLZ min. and t OHZ are periodically sampled and not 100% tested, t HZ and t OHZ are measured, with CL = 5pF, from the point when CE#, OE# return HIGH (whichever occurs fi rst) to the time when the outputs are no longer driven. Figure 14 - Read Cycle t R C A D D R E S S t C E t O E O E # V I H t O L Z t O H Z t L Z t O H t H Z D A TA I / O H I G H Z D A T A V A L I D D A T A V A L I D t A A Revision 1.4-02/13 13

Table 11 - Write Cycle Limits Symbol Parameter Min. Typ. 1 Max. Units t WC 2 Write Cycle Time 3 5 ms t AS Address Setup Time 0 t AH Address Hold Time 50 t CS Write Setup Time 0 t CH Write Hold Time 0 t CW CE# Pulse Width 50 t OES OE# HIGH Setup Time 0 t OEH OE# HIGH Hold Time 0 t WP WE# Pulse Width 50 t WPH 3 WE# High Recovery (page write only) 50 t DV Data Valid 1 µs t DS Data Setup 50 t DH Data Hold 0 t DW 3 Delay to next Write after polling is true 10 t BLC Byte Load Cycle 0.15 100 1. Typical values are for T A = 25 C and nominal supply voltage. 2. t WC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 3. t WPH and t DW are periodically sampled and not 100% tested. Figure 15 - WE# Controlled Write Cycle ns ns µs A D D R E S S t W C t A S t A H t C S t C H O E # t O E S t W P t O E H D A TA I N D A T A V A L I D t D S t D H D A TA O U T H I G H Z Revision 1.4-02/13 14

Figure 16 - CE# Controlled Write Cycle t W C A D D R E S S t A S t A H t C W t O E S t O E H O E # t C S t C H D A T A I N D A T A V A L I D t D S t D H D A TA O U T H I G H Z Figure 17 - Page Write Cycle O E # 1 t W P t B L C t W P H 2 A D D R E S S I / O L A S T B Y T E B Y T E 0 B Y T E 1 B Y T E 2 B Y T E n B Y T E n + 1 B Y T E n + 2 * F o r e a c h s u c c e s s i v e w r i t e w i t h i n t h e p a g e w r i t e o p e r a t i o n, A 7 A 14 s h o u l d b e t h e s a m e o r w r i t e s t o a n u n k n o w n a d d r e s s c o u l d o c c u r. t W C 1. Between successive byte writes within a page write operation, OE# can be strobed LOW: e.g. this can be done with CE# and WE# HIGH to fetch data from another memory device within the system for the next write; or with WE# HIGH and CE# LOW effectively performing a polling operation. 2. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE# or WE# controlled write cycle timing. Revision 1.4-02/13 15

Figure 18 - DATA Polling Diagram1 A D D R E S S A N A N A N t O E H t O E S O E # t D W I / O 7 D I N = X D O U T = X D O U T = X t W C Figure 19 - Toggle Bit Timing Diagram 1 t O E H t O E S O E # I / O 6 H I G H Z * * t D W t W C * I / O 6 b e g i n n i n g a n d e n d i n g s t a t e w i l l v a r y, d ew p C. e n d i n g u p o n a c t u a l t 1. Polling operations are by defi nition read cycles and are therefore subject to read cycle timings. Revision 1.4-02/13 16

Packaging Information Figure 20-28-Lead Hermetic Dual In-line Package Type CW 1. 4 6 0 ( 37. 0 8 ) 1. 4 0 0 ( 35. 5 6 ) 0. 5 5 0 ( 13. 9 7 ) 0. 5 10 ( 12. 9 5 ) P I N 1 I N D E X P I N 1 1. 30 0 ( 33. 0 2) R E F. 0. 0 8 5 ( 2. 16 ) 0. 0 4 0 ( 1. 0 2) S E A T I N G P L A N E 0. 15 0 ( 3. 8 1) 0. 125 ( 3. 17 ) 0. 16 0 ( 4. 0 6 ) 0. 125 ( 3. 17 ) 0. 0 30 ( 0. 7 6 ) 0. 0 15 ( 0. 38 ) 0. 110 ( 2. 7 9 ) 0. 0 9 0 ( 2. 29 ) 0. 0 6 2 ( 1. 5 7 ) 0. 0 5 0 ( 1. 27 ) 0. 0 20 ( 0. 5 1) 0. 0 16 ( 0. 4 1) 0. 6 10 ( 15. 4 9 ) 0. 5 9 0 ( 14. 9 9 ) T Y P. 0. 0 10 ( 0. 25 ) 0 15 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) Revision 1.4-02/13 17

Packaging Information (continued) Figure 21-32-Pad Ceramic Leadless Chip Carrier Package Type ECA 0. 0 15 ( 0. 38 ) 0. 0 0 3 ( 0. 0 8 ) 0. 15 0 ( 3. 8 1) B S C 0. 0 20 ( 0. 5 1) x R E4 F 5. P I N 1 0. 0 9 5 ( 2. 4 1) 0. 0 7 5 ( 1. 9 1) 0. 0 22 ( 0. 5 6 ) 0. 0 0 6 ( 0. 15 ) 0. 20 0 ( 5. 0 8 ) B S C 0. 0 5 5 ( 1. 39 ) 0. 0 4 5 ( 1. 14 ) T Y P. ( 4 ) P L C S. 0. 0 28 ( 0. 7 1) 0. 0 22 ( 0. 5 6 ) ( 32) P L C S. 0. 0 5 0 ( 1. 27 ) B S C 0. 0 4 0 ( 1. 0 2) x R E4 F 5. T Y P. ( 3) P L C S. 0. 4 5 8 ( 11. 6 3) 0. 4 4 2 ( 11. 22) 0. 4 5 8 ( 11. 6 3) 0. 30 0 ( 7. 6 2) B S C 0. 120 ( 3. 0 5 ) 0. 0 6 0 ( 1. 5 2) 0. 0 8 8 ( 2. 24 ) 0. 0 5 0 ( 1. 27 ) 0. 5 6 0 ( 14. 22) 0. 5 4 0 ( 13. 7 1) 0. 4 0 0 ( 10. 16 ) B S C 0. 5 5 8 ( 14. 17 ) 32 1 P I N 1 I N D E X C O R D E R 39 26 F H D F 14 39 26 F h d F 14 NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1 % NTL ±0. 0 0 5 (0. 1 2 7 ) Revision 1.4-02/13 18

Packaging Information (continued) Figure 22-28-Lead Ceramic Pin Grid Array Package Type P 12 13 15 17 18 11 10 14 16 19 9 8 20 21 A 0. 0 0 8 7 6 22 23 5 2 28 24 25 0. 0 5 0 A NOTE: LEADS 4, 1 2, 1 8 & 2 6 4 3 1 27 26 T Y P. 0. 10 0 0. 0 8 0 A L L L E A D S 0. 0 8 04 C O R N E R S 0. 0 7 0 0. 0 7 0 0. 10 0 0. 0 8 0 P I N 1 I N D E X 0. 0 7 2 0. 0 6 1 0. 0 20 0. 0 16 0. 6 6 0 ( 16. 7 6 ) 0. 6 4 0 ( 16. 26 ) A 0. 5 6 1 ( 14. 25 ) 0. 5 4 1 ( 13. 7 5 ) A 0. 18 5 ( 4. 7 0 ) 0. 17 5 ( 4. 4 4 ) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) Revision 1.4-02/13 19

Packaging Information (continued) Figure 23-28-Lead Ceramic Flat Pack Type F 1 P I N 1 I N D E X 28 0. 0 19 ( 0. 4 8 ) 0. 0 15 ( 0. 38 ) 0. 0 5 0 ( 1. 27 ) B S C 0. 7 4 0 ( 18. 8 0 ) M A X. 0. 0 4 5 ( 1. 14 ) M A X. 0. 0 0 6 ( 0. 15 ) 0. 0 0 3 ( 0. 0 8 ) 0. 4 4 0 ( 11. 18 ) M A X. 0. 130 ( 3. 30 ) 0. 0 9 0 ( 2. 29 ) 0. 37 0 ( 9. 4 0 ) 0. 25 0 ( 6. 35 ) T Y P. 0. 30 0 2 P L C S. 0. 0 30 ( 0. 7 6 ) M I N. 0. 18 0 ( 4. 5 7 ) M I N. 0. 0 4 5 ( 1. 14 ) 0. 0 25 ( 0. 6 6 ) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) Revision 1.4-02/13 20

Packaging Information (continued) Figure 24-32-Lead Ceramic SOJ Type ECJ 32 1 Revision 1.4-02/13 21

Ordering Information Table 12 - Device Numbering Device Number Package Type Speed Temperature -7 = 70ns CW CerDIP -9 = 90ns -12 = 120ns IT/XT -15 = 150ns -7 = 70ns ECA- CerLCC -9 = 90ns -12 = 120ns IT/XT -15 = 150ns -7 = 70ns F- CerFP -9 = 90ns -12 = 120ns IT/XT -15 = 150ns -7 = 70ns P- CerPGA -9 = 90ns -12 = 120ns IT/XT -15 = 150ns -7 = 70ns ECJ CerSOJ -9 = 90ns -12 = 120ns IT/XT -15 = 150ns IT = Industrial Temperature Range XT = Extended Temperature Range -40 C to +85 C -55 C to +125 C Revision 1.4-02/13 22

Document Title 32K x 8 EEPROM - 5 Volt, Byte Alterable Revision History Revision # History Release Date Status 1.3 Initial Release November 2012 Preliminary 1.4 Added ceramic SOJ package drawing and option Changed status to Released Corrected part number Corrected fi gure designations February 2013 Released Revision 1.4-02/13 23