MITLL Low-Power FDSOI CMOS Process

MITLL Low-Power FDSOI CMOS Process Device Models Revision 2006:2 (September 2006)

2006 by MIT Lincoln Laboratory. All rights reserved. This work was sponsored by the United States Air Force under Air Force Contract #FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government.

CONTENTS CONTENTS SPICE Parameters, BSIMSOI v3.2... 5 Introduction... 5 BSIMSOI v3.x Level Numbers... 5 Parameter Sets... 6 SPICE model parameters.... 6 Device availability... 11 Process corner modeling... 11 Device Characteristics and Related Discussion... 13 MOS Behavior... 13 LVT-FDSOI... 13 MVT-FDSOI... 21 Active and Polysilicon Parasitic Capacitor Behavior... 25 Intentional Capacitor Behavior... 26 CAPN capacitors.... 26 CAPP capacitors.... 28 Contact Information... 31 Revision History... 33 Rev.: 2006:2 (Sep. 06) 3

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SPICE PARAMETERS, BSIMSOI V3.2 1. SPICE PARAMETERS, BSIMSOI V3.2 1.1. Introduction As part of DARPA's NeoCAD program the University of California at Berkeley extended its industry standard SOI SPICE model to include SOI transistors that are fully depleted by the standard definition but are partially depleted under some conditions. The devices fabricated by MITLL fall into this category. The model is in the public domain, available from the Berkeley website, http://www-device.eecs.berkeley.edu/~bsimsoi/. It has also been coded by Richard Shi's group at the University of Washington, Michael Steer's group at North Carolina State University, and Alan Mantooth's group at the University of Arkansas as part of their simulator development in NeoCAD (cjshi@ee.washington.edu, m.b.steer@ieee.org, mantooth@engr.uark.edu). All the major U.S. CAD vendors have also made it available. Note that an SOI transistor is a five-terminal device: drain, gate, source, backgate, body. Thus, all schematics and netlists copied from existing bulk designs have to be reconsidered. Most commonly in SOI design the body terminal is floating, and the device is treated as a four-terminal transistor, where the fourth terminal is the handle wafer, the backgate (Berkeley calls it "e"), not the body. If your netlist causes SPICE to think that the fourth terminal is the body instead of the backgate, your results will be incorrect. Note that the terminal order used for SPICE simulation tools may differ from that required for LVS tools. For questions about the model or the parameter set, please contact Peter Wyatt (wyatt@ll.mit.edu). For questions about using the model in your simulator, please contact your simulator vendor or the Berkeley website. 1.2. BSIMSOI v3.x Level Numbers BSIMSOI v3.x level numbers are as follows: Silvaco SmartSpice 33 Mentor Eldo 56 Synopsis Hspice 57 Cadence Spectre bsimsoi; v3.1 available in IC5.1.41, v3.0 in IC5.0.32; not available in IC4.4.6 Agilent ADS Available through Verilog-A Refer to your simulator documentation for information on which versions of BSIMSOI are supported. For all of these, DO NOT use v2.x, which is for partially depleted transistors only. Version 3.0 added equations to fit the DC characteristics; v3.1 added equations from BSIM4 to fit gate resistance at high frequency and gate oxide tunneling; and v3.2 added the noise model from BSIM4. (The noise parameters have not yet been derived to fit the MITLL devices.) Use soimod=1 to represent the transistors fabricated in the MITLL process. This refers to devices that are fully depleted when turned on at low drain voltage and low backgate voltage and partially depleted under some other conditions. Rev.: 2006:2 (Sep. 06) 5

SPICE PARAMETERS, BSIMSOI V3.2 Berkeley has released a v4.0 of the BSIMSOI model that adds some features that might lead to a better fit, but our parameter set does not support it. 1.3. Parameter Sets 1.3.1. SPICE model parameters. The specific format for the following parameter sets is for Silvaco SmartSpice; it will need some minor changes for other simulators, most importantly, to the LEVEL number. Keep in mind that most UNIX-native simulators require UNIX text files, so "dos2unix" must be used if the parameter set is obtained from a Microsoft Windows file. * See models guide for use of VAR parameters *SPICE Parameters, BSIMSOIv3.2.LIB LowVT * PARAMETERS FOR PROCESS CORNER MODELING.PARAM VAR_N_VTH0=0.PARAM VAR_P_VTH0=0.PARAM VAR_LINT=0.PARAM VAR_WINT=0 *LowVT parameters to be used for QDS1 and 3DM2_tier3..MODEL nf_soi nmos ( LEVEL = 33 +TNOM = 22 VERSION= 3.2 TOX = 4.2E-9 +TSI = 3.8E-8 TBOX = 4E-7 XJ = 1E-7 +NCH = 5.8E17 NSUB = 2E13 VTH0 = 0.54+VAR_N_VTH0 +K1 = 0.53 K2 = 0 K3 = 0 +K3B = 0 K1W1 = 0 K1W2 = 0 +KB1 = 0 W0 = 0 NLX = 0 +DVT0W = 0.5 AGIDL = 3E-5 BGIDL = 4E9 +NGIDL = 0 DVT1W = 1E6 DVT2W = 0 +DVT0 = 0 DVT1 = 0.5 DVT2 = 0 +U0 = 350 UA = 0 UB = 1E-18 +UC = 0 VSAT = 7.5E4 A0 = -0.2 +AGS = 0 B0 = 0 B1 = 0 +FBJTII = 0 ESATII = 1E8 SII0 = 1 +SII1 = 0 SII2 = 0 SIID = 0 +KETA = 0 KETAS = 0 RTH0 = 0.08 +A1 = 0 A2 = 0.99 RDSW = 150 +PRWG = 0 PRWB = 0 WR = 0.76 +WINT = 0+VAR_WINT LINT = 3E-8+VAR_LINT DWG = -3E-8 +DWB = 0 VOFF = -0.2 NFACTOR= 1 +CIT = 0 CDSC = 0.01 CDSCD = 0 +CDSCB = 0 BETA0 = 0 BETA1 = 0 +BETA2 = 0.15 ETA0 = 0.2 ETAB = 0 +DSUB = 0.5 PCLM = 2 PDIBLC1= 0.1 +PDIBLC2= 0 PDIBLCB= 0 DROUT = 0.4 +PVAG = 0 DELTA = 0.01 NGATE = 1.5E20 +ALPHA0 = 4E-7 VDSATII0= 0.9 MOBMOD = 1 +TII = -0.2264 PRT = 10 UTE = -1.8 +KT1 = -0.16 KT1L = 0 LII = -7E-8 6 Rev.: 2006:2 (Sep. 06)

SPICE PARAMETERS, BSIMSOI V3.2 +KT2 = -0.0646 UA1 = 0 UB1 = 0 +UC1 = 0 AT = 3.4E4 TCJSWG = 5E-4 +WL = 0 WLN = 1 WW = 0 +WWN = 1 WWL = 0 LL = 0 +LLN = 2 LW = 0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0 +CJSWG = 8E-10 PBSWG = 0.9 MJSWG = 0.5 +CSDESW = 0 CSDMIN = 1.6E-5 CGDO = 6E-10 +CGSO = 2.5E-10 CGEO = 0 CGSL = 0 +CGDL = 0 CKAPPA = 0.6 CF = 0 +CLC = 5E-8 CLE = 0.6 BINUNIT= 1 +SHMOD = 1 RBODY = 10 RBSH = 100 +CTH0 = 1E-5 NDIODE = 1 NTUN = 10 +VTUN0 = 0 ISBJT = 3E-7 NBJT = 1.5 +LBJT0 = 2E-7 VABJT = 10 AELY = 0 +AHLI = 1E-15 ISDIF = 1.2E-8 ISREC = 1E-3 +ISTUN = 1E-5 XBJT = 1.15 XDIF = 1.11 +XREC = 0.9 XTUN = 0 NTRECF = -0.3 +NTRECR = 10 TT = 3E-10 LN = 2E-6 +NRECF0 = 1.8 NRECR0 = 10 VREC0 = 0.05 +VSDTH = 0.5 VSDFB = -1.5 ASD = 0.5 +DLCB = 0 DLBG = 0 DELVT = 0 +FBODY = 1 ACDE = 0.11 MOIN = 15 +LDIF0 = 1E-3 NDIF = -1 SOIMOD = 1 +VBSA = 0.22 DVBD1 = 0.5 DVBD0 = 0 +NOFFFD = 1 VOFFFD = 0 MOINFD = 1E6 +DK2B = 0.4 K2B = 0.3 WTH0 = 4E-6 +RHALO = 1E15 K1B = 0.85 +RGATEMOD= 1 RSHG = 1.6 XRCRG1 = 12 +XRCRG2 = 1 NGCON = 1 XGW = 0 +XGL = 0 WPCLM = 0.5 LPCLM = 0 ) *.MODEL pf_soi pmos ( LEVEL = 33 +TNOM = 22 VERSION= 3.2 TOX = 4.2E-9 +TSI = 3.8E-8 TBOX = 4E-7 XJ = 1E-7 +NCH = 6E17 NSUB = -5E13 VTH0 = -0.66+VAR_P_VTH0 +K1 = 0.82 K2 = 0 K3 = -5 +K3B = 0 K1W1 = 0 K1W2 = 0 +KB1 = 0 W0 = 0 NLX = 0 +DVT0W = 0 AGIDL = 3E-9 BGIDL = 2E9 +NGIDL = 0.5 DVT1W = 1E6 DVT2W = 0 +DVT0 = 12 DVT1 = 1.5 DVT2 = 0 +U0 = 63 UA = 0 UB = 1E-19 +UC = 0 VSAT = 6E4 A0 = -0.1 +AGS = 0 B0 = 0 B1 = 0 +FBJTII = 0 ESATII = 1E8 SII0 = 1.5 +SII1 = 0 SII2 = 0 SIID = 0 +KETA = 0 KETAS = 0 RTH0 = 0.07 +A1 = 0 A2 = 0.99 RDSW = 500 +PRWG = 0 PRWB = 0 WR = 0.9 +WINT = 6E-8+VAR_WINT LINT = 5E-8+VAR_LINT DWG = 0 +DWB = 0 VOFF = -0.2 NFACTOR= 1.5 +CIT = 0 CDSC = 0.05 CDSCD = 0.1 +CDSCB = 0 BETA0 = 0 BETA1 = 0 Rev.: 2006:2 (Sep. 06) 7

SPICE PARAMETERS, BSIMSOI V3.2 +BETA2 = 0.25 ETA0 = 0.2 ETAB = 0 +DSUB = 0.6 PCLM = 2 PDIBLC1= 1E-3 +PDIBLC2= 0 PDIBLCB= 0 DROUT = 0.4 +PVAG = 0 DELTA = 0.01 NGATE = 1E20 +ALPHA0 = 4E-7 VDSATII0= 0.9 MOBMOD = 1 +TII = -0.2264 PRT = 10 UTE = -1.6 +KT1 = -0.28 KT1L = 8E-9 LII = 0 +KT2 = -0.0646 UA1 = 3.37E-10 UB1 = -3.12E-18 +UC1 = -6.1E-10 AT = 6.5E4 TCJSWG = 5E-4 +WL = 0 WLN = 1 WW = 0 +WWN = 3 WWL = 0 LL = 0 +LLN = 2 LW = 0 LWN = 3 +LWL = 0 CAPMOD = 2 XPART = 0 +CJSWG = 1E-9 PBSWG = 1 MJSWG = 0.5 +CSDESW = 0 CSDMIN = 1.6E-5 CGDO = 5.5E-10 +CGSO = 1E-10 CGEO = 0 CGSL = 0 +CGDL = 0 CKAPPA = 3 CF = 0 +CLC = 1E-6 CLE = 0.6 BINUNIT= 1 +SHMOD = 1 RBODY = 20 RBSH = 10 +CTH0 = 1E-5 NDIODE = 1.01 NTUN = 10 +VTUN0 = 0 ISBJT = 7E-7 NBJT = 1 +LBJT0 = 1E-7 VABJT = 0 AELY = 0 +AHLI = 0 ISDIF = 1E-7 ISREC = 0.02 +ISTUN = 1E-8 XBJT = 1E-20 XDIF = 1.6 +XREC = 0.8 XTUN = 6 NTRECF = 0.1 +NTRECR = -1 TT = 3E-10 LN = 2E-5 +NRECF0 = 1.8 NRECR0 = 10 VREC0 = 0 +VSDTH = 1.0 VSDFB = -0.5 ASD = 0.8 +DLCB = 0 DLBG = 0 DELVT = 0 +FBODY = 1 ACDE = 0 MOIN = 15 +LDIF0 = 1E-3 NDIF = -1 SOIMOD = 1 +VBSA = 0.05 DVBD1 = 0.4 DVBD0 = 1.4 +NOFFFD = 1 VOFFFD = 0 MOINFD = 1E3 +DK2B = 0.4 K2B = 0.15 WTH0 = 4E-6 +RHALO = 1E20 K1B = 0.7 +RGATEMOD= 1 RSHG = 1.6 XRCRG1 = 12 +XRCRG2 = 1 NGCON = 1 XGW = 0 +XGL = 0 WPCLM = 0.2 LPCLM = -0.07 ) *.ENDL LowVT.LIB MidVT *MidVT parameters to be used for 3DM2_tiers1&2.MODEL nf_soi nmos ( LEVEL = 33 +TNOM = 22 VERSION= 3.2 TOX = 4.2E-9 +TSI = 3.8E-8 TBOX = 4E-7 XJ = 1E-7 +NCH = 5.8E17 NSUB = 2E13 VTH0 = 0.62+VAR_N_VTH0 +K1 = 0.53 K2 = 0 K3 = 0 +K3B = 0 K1W1 = 0 K1W2 = 0 +KB1 = 0 W0 = 0 NLX = 0 +DVT0W = 0.5 AGIDL = 3E-5 BGIDL = 4E9 +NGIDL = 0 DVT1W = 1E6 DVT2W = 0 8 Rev.: 2006:2 (Sep. 06)

SPICE PARAMETERS, BSIMSOI V3.2 +DVT0 = 0 DVT1 = 0.5 DVT2 = 0 +U0 = 350 UA = 0 UB = 1E-18 +UC = 0 VSAT = 7.5E4 A0 = -0.2 +AGS = 0 B0 = 0 B1 = 0 +FBJTII = 0 ESATII = 1E8 SII0 = 1 +SII1 = 0 SII2 = 0 SIID = 0 +KETA = 0 KETAS = 0 RTH0 = 0.08 +A1 = 0 A2 = 0.99 RDSW = 150 +PRWG = 0 PRWB = 0 WR = 0.76 +WINT = 0+VAR_WINT LINT = 3E-8+VAR_LINT DWG = -3E-8 +DWB = 0 VOFF = -0.2 NFACTOR= 1 +CIT = 0 CDSC = 0.01 CDSCD = 0 +CDSCB = 0 BETA0 = 0 BETA1 = 0 +BETA2 = 0.15 ETA0 = 0.2 ETAB = 0 +DSUB = 0.5 PCLM = 2 PDIBLC1= 0.1 +PDIBLC2= 0 PDIBLCB= 0 DROUT = 0.4 +PVAG = 0 DELTA = 0.01 NGATE = 1.5E20 +ALPHA0 = 4E-7 VDSATII0= 0.9 MOBMOD = 1 +TII = -0.2264 PRT = 10 UTE = -1.8 +KT1 = -0.16 KT1L = 0 LII = -7E-8 +KT2 = -0.0646 UA1 = 0 UB1 = 0 +UC1 = 0 AT = 3.4E4 TCJSWG = 5E-4 +WL = 0 WLN = 1 WW = 0 +WWN = 1 WWL = 0 LL = 0 +LLN = 2 LW = 0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0 +CJSWG = 8E-10 PBSWG = 0.9 MJSWG = 0.5 +CSDESW = 0 CSDMIN = 1.6E-5 CGDO = 6E-10 +CGSO = 2.5E-10 CGEO = 0 CGSL = 0 +CGDL = 0 CKAPPA = 0.6 CF = 0 +CLC = 5E-8 CLE = 0.6 BINUNIT= 1 +SHMOD = 1 RBODY = 10 RBSH = 100 +CTH0 = 1E-5 NDIODE = 1 NTUN = 10 +VTUN0 = 0 ISBJT = 3E-7 NBJT = 1.5 +LBJT0 = 2E-7 VABJT = 10 AELY = 0 +AHLI = 1E-15 ISDIF = 1.2E-8 ISREC = 1E-3 +ISTUN = 1E-5 XBJT = 1.15 XDIF = 1.11 +XREC = 0.9 XTUN = 0 NTRECF = -0.3 +NTRECR = 10 TT = 3E-10 LN = 2E-6 +NRECF0 = 1.8 NRECR0 = 10 VREC0 = 0.05 +VSDTH = 0.5 VSDFB = -1.5 ASD = 0.5 +DLCB = 0 DLBG = 0 DELVT = 0 +FBODY = 1 ACDE = 0.11 MOIN = 15 +LDIF0 = 1E-3 NDIF = -1 SOIMOD = 1 +VBSA = 0.22 DVBD1 = 0.5 DVBD0 = 0 +NOFFFD = 1 VOFFFD = 0 MOINFD = 1E6 +DK2B = 0.4 K2B = 0.3 WTH0 = 4E-6 +RHALO = 1E15 K1B = 0.85 +RGATEMOD= 1 RSHG = 1.6 XRCRG1 = 12 +XRCRG2 = 1 NGCON = 1 XGW = 0 +XGL = 0 WPCLM = 0.5 LPCLM = 0 ) *.MODEL pf_soi pmos ( LEVEL = 33 +TNOM = 22 VERSION= 3.2 TOX = 4.2E-9 Rev.: 2006:2 (Sep. 06) 9

SPICE PARAMETERS, BSIMSOI V3.2 +TSI = 3.8E-8 TBOX = 4E-7 XJ = 1E-7 +NCH = 6E17 NSUB = -5E13 VTH0 = -0.66+VAR_P_VTH0 +K1 = 0.82 K2 = 0 K3 = -5 +K3B = 0 K1W1 = 0 K1W2 = 0 +KB1 = 0 W0 = 0 NLX = 0 +DVT0W = 0 AGIDL = 3E-9 BGIDL = 2E9 +NGIDL = 0.5 DVT1W = 1E6 DVT2W = 0 +DVT0 = 12 DVT1 = 1.5 DVT2 = 0 +U0 = 63 UA = 0 UB = 1E-19 +UC = 0 VSAT = 6E4 A0 = -0.1 +AGS = 0 B0 = 0 B1 = 0 +FBJTII = 0 ESATII = 1E8 SII0 = 1.5 +SII1 = 0 SII2 = 0 SIID = 0 +KETA = 0 KETAS = 0 RTH0 = 0.07 +A1 = 0 A2 = 0.99 RDSW = 500 +PRWG = 0 PRWB = 0 WR = 0.9 +WINT = 6E-8+VAR_WINT LINT = 5E-8+VAR_LINT DWG = 0 +DWB = 0 VOFF = -0.2 NFACTOR= 1.5 +CIT = 0 CDSC = 0.05 CDSCD = 0.1 +CDSCB = 0 BETA0 = 0 BETA1 = 0 +BETA2 = 0.25 ETA0 = 0.2 ETAB = 0 +DSUB = 0.6 PCLM = 2 PDIBLC1= 1E-3 +PDIBLC2= 0 PDIBLCB= 0 DROUT = 0.4 +PVAG = 0 DELTA = 0.01 NGATE = 1E20 +ALPHA0 = 4E-7 VDSATII0= 0.9 MOBMOD = 1 +TII = -0.2264 PRT = 10 UTE = -1.6 +KT1 = -0.28 KT1L = 8E-9 LII = 0 +KT2 = -0.0646 UA1 = 3.37E-10 UB1 = -3.12E-18 +UC1 = -6.1E-10 AT = 6.5E4 TCJSWG = 5E-4 +WL = 0 WLN = 1 WW = 0 +WWN = 3 WWL = 0 LL = 0 +LLN = 2 LW = 0 LWN = 3 +LWL = 0 CAPMOD = 2 XPART = 0 +CJSWG = 1E-9 PBSWG = 1 MJSWG = 0.5 +CSDESW = 0 CSDMIN = 1.6E-5 CGDO = 5.5E-10 +CGSO = 1E-10 CGEO = 0 CGSL = 0 +CGDL = 0 CKAPPA = 3 CF = 0 +CLC = 1E-6 CLE = 0.6 BINUNIT= 1 +SHMOD = 1 RBODY = 20 RBSH = 10 +CTH0 = 1E-5 NDIODE = 1.01 NTUN = 10 +VTUN0 = 0 ISBJT = 7E-7 NBJT = 1 +LBJT0 = 1E-7 VABJT = 0 AELY = 0 +AHLI = 0 ISDIF = 1E-7 ISREC = 0.02 +ISTUN = 1E-8 XBJT = 1E-20 XDIF = 1.6 +XREC = 0.8 XTUN = 6 NTRECF = 0.1 +NTRECR = -1 TT = 3E-10 LN = 2E-5 +NRECF0 = 1.8 NRECR0 = 10 VREC0 = 0 +VSDTH = 1.0 VSDFB = -0.5 ASD = 0.8 +DLCB = 0 DLBG = 0 DELVT = 0 +FBODY = 1 ACDE = 0 MOIN = 15 +LDIF0 = 1E-3 NDIF = -1 SOIMOD = 1 +VBSA = 0.05 DVBD1 = 0.4 DVBD0 = 1.4 +NOFFFD = 1 VOFFFD = 0 MOINFD = 1E3 +DK2B = 0.4 K2B = 0.15 WTH0 = 4E-6 10 Rev.: 2006:2 (Sep. 06)

SPICE PARAMETERS, BSIMSOI V3.2 +RHALO = 1E20 K1B = 0.7 +RGATEMOD= 1 RSHG = 1.6 XRCRG1 = 12 +XRCRG2 = 1 NGCON = 1 XGW = 0 +XGL = 0 WPCLM = 0.2 LPCLM = -0.07 ).ENDL MidVT 1.3.2. Device availability. SPICE parameter sets that support two variants of the Lincoln Laboratory 180-nm FDSOI process are described. These are the low threshold voltage (LVT) and medium threshold voltage (MVT) processes. Table 1-1 summarizes the 180-nm device availability for recent and upcoming tapeouts. Table 1-1: Summary of Device Availability Run Name Tier LVT MVT YES2 RF07 3DL1 1 3DL1 2 3DL1 3 MIM1 QDS1 3DM2 1 3DM2 2 3DM2 3 1.3.3. Process corner modeling. Because the MITLL FDSOI process is experimental in nature, process variations must be considered in a manner that recognizes the challenges of low-volume prototype fabrication. The model parameters provided for the LVT-FDSOI and MVT-FDSOI CMOS devices utilize four variation parameters, which are defined using.param statements. In some circumstances, such as for device mismatch sensitivity studies, a designer might want to modify the parameter deck to allow these parameters to be local to particular instances. Designers should feel free to customize the deck to allow for the necessary simulations and/or tools for a particular project. Rev.: 2006:2 (Sep. 06) 11

SPICE PARAMETERS, BSIMSOI V3.2 The four global variation parameters have been selected because they introduce shifts in transistor performance that are easy to conceptualize. They do not necessarily capture the entirety of physical effects in the CMOS process, but they do allow for sensitivity analysis based on an approximate understanding of possible variations in fabricated device performance. The parameters VAR_N_VTH0 and VAR_P_VTH0 linearly sum respectively with the default VTH0 parameter in the NMOS and PMOS, thus simulating a linear threshold voltage shift. In practice, this may be induced by a number of physical effects that are not completely modeled by this approximation. VAR_LINT and VAR_WINT linearly sum with the LINT and WINT parameters in both the NMOS and PMOS devices, thus modeling gate length and sidewall implant spacing variations. VAR_LINT and VAR_WINT parameters affect both device current and gate capacitance. Suggested sweep values for these parameters are listed in Table 1-2. The target range column indicates expected variation of delivered "yielding" die with respect to the target value. These represent the device performance goals for the fabrication run. To allow for useful circuits to be obtained from die that fall outside of this target range, a robustness range is also included. Since the MITLL 3D integration is performed at the wafer level, it is often the case that on a particular die not all tiers will fall within the target range. To maximize the number of testable parts, it is desirable to accommodate the robustness range wherever possible. This is particularly true for portions of the circuit that are not performance critical. Note that Table 1-2 reflects die-to-die variation, not local device mismatch. Mismatch of devices within a single circuit has been observed to be much less than the values presented in the table. However, insufficient statistical data have been collected to allow for presentation of a local mismatch model at this time. Table 1-2: Target and Robustness Values for Global Parameters Parameter Target Range Robustness Range Minimum Maximum Minimum Maximum VAR_N_VTH0 75 mv + 75 mv 200 mv +100 mv VAR_P_VTH 75 mv + 75 mv 100 mv +100 mv VAR_LINT 20 nm +20 nm 30 nm +30 nm VAR_WINT 50 nm +50 nm In practice, it is necessary to implement multiple copies of the.model statements to allow for each tier to use an independent parameter set. In this case, the.param statements must be embedded within the appropriate models. This customization is tool and methodology specific. 12 Rev.: 2006:2 (Sep. 06)

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 2. DEVICE CHARACTERISTICS AND RELATED DISCUSSION 2.1. MOS Behavior Typical NMOS and PMOS I-V curves for the MITLL 0.18-µ m low-power FDSOI process are shown in Figures 2-1 through 2-16. Legends on the graphs provide the gate (G) or drain (D) voltage of each curve. Device sizes are given in the captions. (A drawn 0.2-µ m-long device will be fabricated with a 0.18-µ m poly gate.) All devices have 8-µ m width. The kink effect appears strongly on the 8-µ m-wide by 0.5-µ m-long NMOS device as an abrupt change in slope in the drain characteristic and an anomalously steep subthreshold slope in the gate characteristic. It is much less apparent in the 0.2-µ m-long NMOS transistor characteristics. The kink is absent or much smaller in PMOS devices at room temperature and above. 2.1.1. LVT-FDSOI. 0.004 0.0035 0.003 G 0.0 G 0.3 G 0.6 G 0.9 G 1.2 G 1.5 Drain Current (A) 0.0025 0.002 0.0015 0.001 0.0005 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Drain Voltage (V) Figure 2-1: I-V curve for device 8 µ m wide by 0.2 µ m long (neo1 w4 r2c4, D 0, V BG = 0 V). Rev.: 2006:2 (Sep. 06) 13

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 10-2 10-3 10-4 D 0.9 D 1.2 D 1.5 10-5 Drain Current (A) 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -1-0.5 0 0.5 1 1.5 Gate Voltage (V) Figure 2-2: I-V curve for device 8 µ m wide by 0.2 µ m long (neo1 w4 r2c4, G 0, V BG = 0 V). 14 Rev.: 2006:2 (Sep. 06)

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 0.0018 Drain Current (A) 0.0016 0.0014 0.0012 0.001 0.0008 G 0.0 G 0.3 G 0.6 G 0.9 G 1.2 G 1.5 0.0006 0.0004 0.0002 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Drain Voltage (V) Figure 2-3: I-V curve for device 8 µ m wide by 0.5 µ m long (neo1 w4 r2c4, D 0, V BG = 0 V). Rev.: 2006:2 (Sep. 06) 15

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 10-2 10-3 10-4 D 0.9 D 1.2 D 1.5 10-5 Drain Current (A) 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -1-0.5 0 0.5 1 1.5 Gate Voltage (V) Figure 2-4: I-V curve for device 8 µ m wide by 0.5 µ m long (neo1 w4 r2c4, G 0, V BG = 0 V). 16 Rev.: 2006:2 (Sep. 06)

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 0.0014 0.0012 0.001 G 0.0 G -0.3 G -0.6 G -0.9 G -1.2 G -1.5 Drain Current (A) 0.0008 0.0006 0.0004 0.0002 0-1.6-1.4-1.2-1 -0.8-0.6-0.4-0.2 0 Drain Voltage (V) Figure 2-5: I-V curve for device 8 µ m wide by 0.2 µ m long (neo1 w10 r3c2, D 0, V BG = 0 V). Rev.: 2006:2 (Sep. 06) 17

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 10-2 10-3 10-4 10-5 D 0.9 D 1.2 D 1.5 10-6 Drain Current (A) 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -1.5-1 -0.5 0 0.5 1 Gate Voltage (V) Figure 2-6: I-V curve for device 8 µ m wide by 0.2 µ m long (neo1 w10 r3c2, G 0, V BG = 0 V). 18 Rev.: 2006:2 (Sep. 06)

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 0.0004 Drain Current (A) 0.00035 0.0003 0.00025 0.0002 0.00015 G 0.0 G -0.3 G -0.6 G -0.9 G -1.2 G -1.5 0.0001 0.00005 0-1.6-1.4-1.2-1 -0.8-0.6-0.4-0.2 0 Drain Voltage (V) Figure 2-7: I-V curve for device 8 µ m wide by 0.5 µ m long (neo1 w10 r3c2, D 0, V BG = 0 V). Rev.: 2006:2 (Sep. 06) 19

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 10-3 10-4 10-5 10-6 D 0.9 D 1.2 D 1.5 Drain Current (A) 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -1.5-1 -0.5 0 0.5 1 Gate Voltage (V) Figure 2-8: I-V curve for device 8 µ m wide by 0.5 µ m long (neo1 w10 r3c2, G 0, V BG = 0 V). 20 Rev.: 2006:2 (Sep. 06)

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 2.1.2. MVT-FDSOI. For the MVT-FDSOI version of the Lincoln Laboratory fully depleted SOI CMOS process, the threshold voltage of the NMOS devices is increased slightly to reduce leakage. The PMOS design for the MVT-FDSOI process is identical to that for the LVT-FDSOI process. Figures 2-9 through 2-12 show a comparison of the MVT-FDSOI and LVT-FDSOI NMOS, as simulated using the SPICE models provided in Section 1.3. 0.004 0.0035 MVT-FDSOI LVT-FDSOI 0.003 Drain Current (A) 0.0025 0.002 0.0015 0.001 0.0005 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain Voltage (V) Figure 2-9: Simulated I d -V d curves for LVT and MVT NMOS devices with 8-µ m width and 0.2-µ m drawn length, using nominal parameters. The gate voltage has been swept from 0 V to 1.5 V in 0.3-V increments. Rev.: 2006:2 (Sep. 06) 21

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 0.002 0.0018 0.0016 MVT-FDSOI LVT-FDSOI 0.0014 Drain Current (A) 0.0012 0.001 0.0008 0.0006 0.0004 0.0002 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain Voltage (V) Figure 2-10: Simulated I d -V d curves for LVT and MVT NMOS devices with 8-µ m width and 0.5-µ m drawn length, using nominal parameters. The gate voltage has been swept from 0 V to 1.5 V in 0.3-V increments. 22 Rev.: 2006:2 (Sep. 06)

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 10-3 10-4 10-5 10-6 Drain Current (A) 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 MVT-FDSOI LVT-FDSOI 10-15 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Gate Voltage (V) Figure 2-11: Simulated I d -V g curves for LVT and MVT NMOS devices with 8-µ m width and 0.2-µ m drawn length, using nominal parameters. The gate voltage has been swept from 0.9 V to 1.5 V in 0.3-V increments. Rev.: 2006:2 (Sep. 06) 23

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 10-3 10-4 10-5 10-6 Drain Current (A) 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 MVT-FDSOI LVT-FDSOI 10-15 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Gate Voltage (V) Figure 2-12: Simulated I d -V g curves for LVT and MVT NMOS devices with 8-µ m width and 0.5-µ m drawn length, using nominal parameters. The gate voltage has been swept from 0.9 V to 1.5 V in 0.3-V increments. 24 Rev.: 2006:2 (Sep. 06)

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 2.2. Active and Polysilicon Parasitic Capacitor Behavior The curve in Figure 2-17 for a 100 100-µ m 2 n-active capacitor illustrates the buried oxide capacitance, around 90 af/µ m 2 in accumulation and less than 20 af/µ m 2 in inversion. Since CMOS circuits traditionally operate at positive voltage, the inversion condition is typical. For a PSD-doped active, this whole curve shifts to more positive voltage by about 1 V. BSIMSOIv3.x model includes an approximation of this capacitance if the designer provides instance parameters for the area of the source and drain. The area of body contacts can also be included. The model includes peripheral capacitance as well, but the needed parameter has been set to zero. 1 0.9 0.8 0.7 Capacitance (pf) 0.6 0.5 0.4 0.3 0.2 0.1 0-3 -2-1 0 1 2 3 Active-Wafer Voltage (V) Figure 2-13: C-V curve for n-active to handle wafer (neo1 w10 r3c2 cap2). Rev.: 2006:2 (Sep. 06) 25

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 2.3. Intentional Capacitor Behavior 2.3.1. CAPN capacitors. The C-V curves in Figures 2-18 and 2-19 represent poly to CAPN-implanted active with the gate oxide as dielectric. Before gate oxidation, the silicon received the same implant as the edges of the PMOS transistors. Each capacitor is 100 x 100 µ m 2, so the capacitance is around 6.5 ff/µ m 2. 70 60 50 Capacitance (pf) 40 30 20 10 0-2 -1.5-1 -0.5 0 0.5 1 1.5 2 Gate-Source Voltage (V) Figure 2-14: C-V curve for CAPN: NSD-implanted poly with CAPN- and CBP-implanted active (neo1 w4 r2c4 cap13 nmos). 26 Rev.: 2006:2 (Sep. 06)

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 68 67 66 Capacitance (pf) 65 64 63 62 0 0.3 0.6 0.9 1.2 1.5 Gate-Source Voltage (V) Figure 2-15: C-V curve for CAPN over recommended voltage range (neo1 w4 r2c4 cap13 nmos). Rev.: 2006:2 (Sep. 06) 27

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 2.3.2. CAPP capacitors. The C-V curves in Figures 2-20 and 2-21 represent poly to CAPP-implanted active with the gate oxide as dielectric. Before gate oxidation, the silicon received the same implant as the edges of the NMOS transistors. Each capacitor is 100 x 100 µ m 2, so the capacitance is around 6.5 ff/µ m 2. 70 60 50 Capacitance (pf) 40 30 20 10 0-2 -1.5-1 -0.5 0 0.5 1 1.5 2 Gate-Source Voltage (V) Figure 2-16: C-V curve for CAPP: PSD-implanted poly with CAPP- and CBN-implanted active (neo1 w4 r2c4 cap12 pmos) 28 Rev.: 2006:2 (Sep. 06)

DEVICE CHARACTERISTICS AND RELATED DISCUSSION 68 67 66 Capacitance (pf) 65 64 63 62-1.5-1.2-0.9-0.6-0.3 0 Gate-Source Voltage (V) Figure 2-17: C-V curve for CAPP over recommended voltage range (neo1 w4 r2c4 cap12 pmos). Rev.: 2006:2 (Sep. 06) 29

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CONTACT INFORMATION CONTACT INFORMATION For specific inquiries: Technical: Layout submission: Brian Tyrrell Bruce Wheeler (781) 981-5496 (781) 981-2630 tyrrell@ll.mit.edu wheeler@ll.mit.edu Device modeling: Editorial: Peter Wyatt Karen Challberg (781) 981-7882 (781) 981-0858 wyatt@ll.mit.edu challberg@ll.mit.edu For any other questions, comments, or suggestions: MIT Lincoln Laboratory Advanced Silicon Technology Group 244 Wood Street Lexington, MA 02421 Phone: (781) 981-7880 Fax: (781) 981-7889 http://www.ll.mit.edu/ast Rev.: 2006:2 (Sep. 06) 31

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REVISION HISTORY REVISION HISTORY Rev. 2006:2 (Sep. 06) All new subsection 2.1.2 with new Figures 2-9 through 2-12 Renumbering of Figures 2-17 through 2-21 as Figures 2-13 through 2-17 Rev. 2006:1 (Aug. 06) In Section 1.1, revision of para. 1 and para. 2 In Section 1.2, revision of para. 1 and new para. 4 Revision of Section 1.3 with new subsections 1.3.1 1.3.3 Revision of Section 2-1 into subsections 2.1.1 and 2.1.2 All new subsection 2.1.2 with new Figures 2-9 through 2-16 Addition of new Section 2.2 incorporating previous Figure 2-13 and text Renumbering of previous Section 2.2 as Section 2-3 Revision of Section 2-3 with new subsections 2.3.1 and 2.3.2 Rev.: 2006:2 (Sep. 06) 33

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