EV Group. Enabling processes for 3D interposer. Dr. Thorsten Matthias EV Group

EV Group Enabling processes for 3D interposer Dr. Thorsten Matthias EV Group

EV Group in a Nutshell st Our philosophy Our mission in serving next generation application in semiconductor technology Equipment supplier for the semiconductor and MEMS industry 1400+ equipment installations Privately held company founded in 1980 Headquartered in Austria - subsidiaries in USA, JP, KR and TW Worldwide Sales and Customer Support Network Internal process development (2000m 2 class 100 cleanroom) 20% of revenue is invested into R&D annually

Enabling processes for 3D interposer Outline Interposer Process Flow Enabling processes TSV passivation Thin wafer handling Chip-to-Wafer integration Metrology

Interposer Basic concept Passive Interposer Source : Georgia Tech PRC Driver Bandwidth: fine pitch, high speed interconnections Active Interposer Source : Yole Development Fan out high density connections Heat transfer Integrated passives Modular design Source : J. H. Lau, et al., Chip Scale Review, p. 26, Sept/Oct (2010)

Major Applications Roadmap Source : Yole Development

Manufacturing Process Flow (Interposer Example) Via Etching RDL, Passivation and Bumping Insulator/Barrier/Seed Deposition Carrier Wafer Debonding Cu Plating and CMP Multi-Layer Wiring and Bumping (second carrier, optionally) Carrier Wafer Bonding D2W Assembly and Wafer Probing Wafer Thinning Molding and Singulation

EVG 150 : NanoSpray Coating 100µm 200µm TSV passivation with dielectrics Reduced electrical losses for Silicon interposers Via bottom opening with EVG IQ Aligner 50µm 200µm 30µm 200µm

Thin wafer processing Temporary bonding and debonding Process Integration Enables utilization of existing equipment and existing processes (Back thinning, TSV formation, backside metallization, etc..)

Reliable Debonding no damages to topographic structures & no particles TB/DB Unit Processes Precision Coating spin and/or spray coating on high topography & high temperature materials from BSI 100µm adhesive layer bumps Si Thickness Measurement Wafer Alignment no impact by wafer size differences Backside Lithography with Transmitted IR Wafer Bonding no interfacial defects & low TTV Performed on IQ Aligner

Thin wafer processing Temporary bonding and debonding Wafer backside processing Temporary Bonding and Debonding enables utilization of existing equipment and existing processes Silicon carrier based TB/DB technology for easy process integration Carrier TTV, CTE matching, high thermal conductivity, not perforated,.,. Room Temperature Debonding Two step process: Edge Zone Release and Edge Zone Debond Compatible with both Si and glass carriers

Metrology Integrated process control as enabler for HVM Integrated Metrology High throughput to enable 100% inspection of wafers Compatible with 300mm modular EVG systems platform Temporary bonding Thickness and TTV Carrier, Adhesive, Total stack Days / year 350 Hours / day 20 T-put [uph] Wafers processed per year 1/1,000 yield loss $1000/ wafer $2000/ wafer 15 105.000 105 $105.000 $210.000 $525.000 525 $525.000 $1.050.000 $2.625.000 25 175.000 175 $175.000 $350.000 $875.000 875 $875.000 $1.750.000 $4.375.000 35 245.000 245 $245.000 $490.000 $1.225.000 1225 $1.225.000 $2.450.000 $6.125.000 45 315.000 315 $315.000 $630.000 $1.575.000 1575 $1.575.000 $3.150.000 $7.875.000 < $500,000 < $1,000,000 < $3,000,000 > $5,000,000 Wafers lost $5000/ wafer Wafers lost 5/1,000 yield loss $1000/ wafer $2000/ wafer $5000/ wafer Bonding voids Bonded wafer bow and warp

Metrology Advanced process control as enabler for HVM B) Stand alone system EVG40NT Multiple metrology modes Extendable functionality Full wafer in depth analysis Accuracy: <100nm, 3σ Accuracy: <100nm, 3σ EVG40NT Metrology System Accuracy: <100nm, 3σ Accuracy: <100nm, 3σ Scale < 0.20 0.40 0.60 0.80 >0.8 Accuracy: <100nm, 3σ Accuracy: <100nm, 3σ Accuracy: <100nm, 3σ 1 Wafer map: vector plots

Advanced Chip to Wafer Bonding Advanced Chip-to-Wafer (AC2W) Process Flow Source : Fraunhofer IZM AC2W is composed of two consecutive steps.