Lecture Notes for ECE 215: Digital Integrated Circuits

Introduction to Digital Electronics University of Connecticut 2

The World s Most Dynamic Field of Enterprise What is Moore s Law? What is the ITRS? University of Connecticut 3

Properties of Digital Circuits. Logic Function. Quantization of Amplitudes. Regeneration. Directivity. Fan-in, Fan-out. University of Connecticut 4

The Ideal Gate. Zero power dissipation. Rail to rail voltage swing. Abrupt logic transitions at V DD /2. Zero propagation delay. Infinite fan-out. University of Connecticut 5

Inverter VTC V OUT V OH slope = -1 V IL = maximum input voltage interpreted as 0 V IH = minimum input voltage interpreted as 1 V OH = minimum logic 1 output voltage V OL 0 V IL V IH V IN V OL = maximum logic 0 output voltage University of Connecticut 6

Noise Margins. V OUT V NMH = V OH - V IH V OH V OL 0 V IL slope = -1 V IH V IN V NML = V IL - V OL Noise in digital circuits results from the coupling of voltages and currents Noise of amplitude less than the noise margin is attenuated University of Connecticut 7

Switching Characteristics V IN V OUT t PHL t PLH 50% 10% 90% t t R = rise time t F = fall time t PLH = low-to-high propagation delay t PHL = high-to-low propagation delay t F t R t University of Connecticut 8

Power-Delay Product (PDP) Power Dissipation. P = (P H +P L )/2 Propagation Delay. t P = (t PLH +t PHL )/2 Power-Delay Product. PDP=Pt P There is a tradeoff between speed and power dissipation. The lower the PDP, the better the tradeoff. University of Connecticut 9

Levels of Integration SSI - Small-Scale Integration, 1-10 gates (7404 Hex Inverter) MSI - Medium-Scale (10-100 gates) LSI - Large-Scale (100-10k gates) VLSI - Very Large-Scale (>10k gates) University of Connecticut 10

Logic Families Introduction Growth Maturity Saturation Decline Highest performance High design-in activity High-volume production Price stability Decreasing supplier base New Technologies High level of supplier resources Multiple suppliers Limited new designs Not recommmended for new designs Decreasing supplier base Increasing prices FACT ALSTTL / ASTTL FAST 100k ECL HCMOS Volume in Year 2000 ABT BiCMOS VHCMOS FS CMOS LSTTL STTL Tinylogic CMOS 4000 CMOS LVT CMOS LCX / LVX CMOS TTL VCX CMOS 1998 1995 1990 1985 1980 1975 1970 1965 Product Introduction University of Connecticut 11

Fabrication CMOS Process DRAM Process Bipolar Process BiCMOS Process GaAs E/D MESFET Process University of Connecticut 12

CMOS Process pad oxide nitride p-type substrate photoresist photoresist nitride p-type substrate nitride CVD oxide p-type substrate University of Connecticut 13

CMOS Process (cont.) STI STI STI p-type substrate gate oxide polysilicon STI p-doping STI n-doping STI p-type substrate n-well gate oxide polysilicon STI p-doping STI n-doping STI p-type substrate n-well University of Connecticut 14

CMOS Process (cont.) photoresist photoresist poly poly STI p-doping STI n-doping STI p-type substrate n-well n + poly p + poly STI n + n + STI p + p + p-doping n-doping STI p-type substrate n-well n + poly oxide spacer p + poly STI n + n + STI p + p + p-doping n-doping STI p-type substrate n-well silicide n+ poly oxide spacer p + poly STI STI n + n + p + p-doping n-doping p + STI p-type substrate n-well University of Connecticut 15

Testing and Yield x x x x x x x x x x x x x x (a) (b) University of Connecticut 16

IC Packages Through-hole packages Surface mount packages Chip scale packages Bare die modules University of Connecticut 17

Bipolar Devices University of Connecticut 18

Bipolar Logic Families. Transistor-Transistor Logic (TTL). Lowpower Schottky versions are most popular. Emitter-Coupled Logic (ECL). Used in high-end supercomputers. BiCMOS. The best of both worlds? Integrated Injection Logic (I 2 L). Still important commercially. University of Connecticut 19

PN Junction Diode I p n The pn diode follows Schockley s equation: + R V ( V D /φ T 1) I = I e D S University of Connecticut 20

Doping in the PN Diode I p n + R V p-type: p po = N a and n po = n i2 /N a n-type: p no = n i2 /N d and n no = N d University of Connecticut 21

PN Diode: Equilibrium p - - - ++ - + + ρ n Space Charge Density -x p < x < 0: ρ = -qn a E x x 0 < x < x n : ρ = +qn d elsewhere: ρ = 0 Electric Field de/dx = ρ/ε V x Electric Potential dv/dx = -E University of Connecticut 22

PN Diode: Built-in Potential Holes move by diffusion and drift: dp Jp ( diff ) = qd p J p( drift) = qµ p pe dx In equilibrium, Jp ( diff ) + J p ( drift) = 0 Also, by the Einstein relationship, Dp kt φ T V µ = q = = 0. 026 p University of Connecticut 23

PN Diode: Built-in Potential Thus the equilibrium condition is: qµ pe qd dp p = Edx = φ dp p T dx p In terms of potential, dφ = φ d(ln p) T Thus φ o T a d = φ N N ln 2 n i University of Connecticut 24

PN Diode: Depletion Width -x E p x n x xpeo xneo WEo φ o = + = 2 2 2 -E o By charge neutrality, qn x = qn x a p d n By the Poisson equation, Solving: W E o = 2εφ 1 1 + q N N a o qn x = = ε d qn x a p d n ε University of Connecticut 25

PN Diode: Forward Bias I p n In equilibrium, p no + R V = p φ po exp φ o T with a bias V, ( ) p x = p n n p0 V φ exp φ T 0 This is the Law of the Junction: University of Connecticut 26

PN Diode: Forward Bias n po n po e 40V -x p 0 x n V pn ( x) = pno exp exp φ T p no e 40V p no x Forward bias results in injection of excess minority carriers, which give rise to a net DIFFUSION current. ( x xn ) L = D τ L p p p p J x qd dp qdp pno V qdpni V p ( n) p = exp exp dx = 2 Lp φt L N φ p d T University of Connecticut 27

PN Diode: Forward Bias If we include the electron contribution, and also the drift currents of electrons and holes, then I 2 Dp = qani + Lp Nd This is the diode equation, where the reverse saturation current is given by D n L N n a exp V φt 1 I S 2 Dp = qani + L N p d Dn L N n a University of Connecticut 28

PN Diode: Switching Transients n PN diodes exhibit depletion capacitance, and PN diodes store excess minority carriers; this is also a capacitive effect. po exp n po ( V / φ T ) -x p 0 x n p no exp ( V / φ ) p no x T Minority carriers are stored on both sides of the diode. Storage of one type of carrier may dominate, in one-sided diodes. For a p + -n diode, the charge control equation is Qp dqp i( t) = + + τ dt F C dv T dt University of Connecticut 29

PN Diode: Turn-on (fast!) + i(t) p n + v(t) - At t = 0, the source voltage is turned on abruptly. i(t) i(t) rises abruptly p n increasing time t Q p builds up with time v(t) x v(t) increases rapidly p v( t) = φ ln ( x ) n n T t pno University of Connecticut 30

PN Diode: Turn-off Transient + + t=0 v(t) + - p n i(t) At t = 0, the source voltage polarity is switched from FB to RB. For t <0, Q For 0 < t < t SD, = I τ p F F This is the initial condition. ( R ) ( τ )) Q ( t) = τ (I I + I exp t / p F R F F Solving for Q p (t=t SD )=0, t SD This is the storage delay time. = τ F ln 1+ I I F R University of Connecticut 31

PN Diode: Turn-off Transient v(t) i(t) t SD t RR t SD t RR t t Stored minority carriers are removed during the storage delay time: t SD = τ F ln 1+ The depletion layer capacitance charges during the fall time: t F RC D The sum of these delays is called the reverse recovery time. I I F R University of Connecticut 32

PN Diode SPICE Model R S C D I D [ ( D ) ] The SPICE diode model includes Schockley s equation, the series resistance, and both the depletion layer and diffusion capacitances. I D ' = IS exp V '/ Nφ T 1 VD = VD' + I DRS C TT IS CJO D = exp ( VD '/ Nφ T ) + Nφ T VD ' 1 VJ M University of Connecticut 33

PN Diode SPICE Parameters symbol SPICE name description units default typical I S IS saturation current A 1E-14 1E-14 R S RS series resistance Ω 0 10 N emission coefficient 1 1 τ F TT transit time s 0 0.1N CJO zero-bias capacitance F 0 2P φ o VJ built-in potential V 1 0.8 m M grading coefficient 0.5 0.5 University of Connecticut 34

Metal-Semiconductor Diode metal anode n n+ cathode depletion region The MS diode is a majority carrier device. There are no minority carrier storage effects (fast switching). The MS diode follows the diode equation but with a lower turn-on voltage. The SPICE model is the same as for the PN diode, except for the absence of minority carrier storage. University of Connecticut 35

Integrated Circuit Diodes p+ p+ n+ n- epitaxial layer n+ p substrate PN junction ohmic contact SiO 2 p+ Integrated PN Diode p+ Pt 5 Si 2 n+ n- epitaxial layer n+ p substrate MS junction ohmic contact p+ SiO 2 Integrated MS Diode University of Connecticut 36

Bipolar Junction Transistors E B n p n C The BJT comprises two interacting PN junctions. W B The forward-biased EB junction injects electrons into the base. The base is so narrow that most of the injected electrons can diffuse to the reverse-biased CB junction, where they are collected. Some of the injected electrons recombine with holes, so a small base current is required to maintain charge neutrality in the base. University of Connecticut 37

BJT Terminal Currents B C n p n I B I DC I DE I C α F I DE α R I DC From KCL, I = I α I E DE R DC I = α I I C F DE DC E I E Using the diode equation, we obtain the Ebers-Moll Equations: I I E = I = α ES V exp φ I C F ES BE T V exp φ VBC R ICS 1 α exp 1 φt BE T VBC ICS 1 exp 1 φt University of Connecticut 38

BJT Terminal Currents I I E = I = α ES V exp φ I C F ES BE T V exp φ VBC R ICS 1 α exp 1 φt BE T VBC ICS 1 exp 1 φt Ebers-Moll Equations I α = I α = I ES F CS R S Reciprocity Theorem; I S = transport saturation current β F α F = β 1 α F R α R = 1 α R University of Connecticut 39

BJT Modes of Operation Cutoff. V BE < 0; V BC < 0. All currents are essentially zero. Forward Active. V BE > 0; V BC < 0. V BEA = 0.7V; I C = β F I B. Reverse Active. V BE < 0; V BC > 0. V BCA = 0.7V; I E = β R I B. Saturation. V BE > 0; V BC > 0. V BES = 0.8V; V CES = 0.1V. University of Connecticut 40

Integrated NPN Transistors E B C p+ n+ p+ n+ n- epitaxial layer n+ p substrate p+ Junction-isolated transistor 74xx series TTL 10k ECL E B n+ p p- C n+ n+ p substrate Oxide-isolated transistor 74Fxx TTL 74ALSxx TTL 100k ECL University of Connecticut 41

Integrated PNP Transistors C E B p+ p+ p+ n+ n- epitaxial layer n+ p substrate p+ Lateral PNP 74ASxx TTL 74ALSxx TTL Other Bipolar Transistors Multi-emitter NPN (used in many versions of TTL) Schottky-clamped NPN s (used in Schottky TTL) merged transistors (used in I 2 L) University of Connecticut 42

SPICE BJT Model base I CB RB I BE collector RC C BC C BE C CS substrate SPICE uses the Gummel- Poon model: I CB and I BE are Schockleytype current sources including adjustable emission coefficients. C BC and C BE include depletion layer and diffusion components. C CS is the collector-substrate parasitic capacitance. RE emitter RC, RB, and RE are parasitic resistances. University of Connecticut 43

SPICE BJT Model The DC equations used by SPICE are Schockley-type equations, with adjustable emission coefficients and beta values used to model the Kirk Effect and the Sah-Noyce-Schockley Effect. The Early Effect is modeled using VAF. I C = IS exp IS I B = BF exp I = I + I E B C VBE NFφ VBE NFφ T T VBC exp NRφ VBC 1 VAF University of Connecticut 44 IS BR T VBC exp NRφ IS VBC + 1 BR exp 1 NRφ T T 1

SPICE BJT Model The AC equations used by SPICE include the base-emitter, base-collector, and collector-substrate capacitances. C TF IS BE = NEφ C TR IS BC = NCφ C CS CJS = VCS 1 VJS T T exp exp MJS VBE NEφ VBC NCφ T T + + CJE VBE 1 VJE CJC VBC 1 VJC MJE MJC University of Connecticut 45

BJT SPICE DC Parameters symbol SPICE name description units default typical V A R B R E R C IS VAF IKF ISE NE VAR IKR ISC NC RB RBM IRB RE RC junction saturation current forward Early voltage high corner for β F falloff BE saturation current BE emission coefficient reverse Early voltage high corner for β R falloff BC saturation current BC emission coefficient base series resistance min RB at high current I @ RB halfway to RBM emitter series resistance collector series resistance A V A A V A A Ω Ω A Ω Ω 1E-16 0 1.5 0 2 0 RB 0 0 1E-16 200 10E-3 1E-13 2 200 1E-3 1E-13 1.5 100 10 0.1 1 10 University of Connecticut 46

BJT SPICE AC Parameters symbol SPICE name description units default typical C BE0 φ BE m E τ F C BC0 φ BC m C τ R C CS0 φ CS m S CJE VJE MJE TF XTF VTF ITF PTF CJC VJC MJC XCJC TR CJS VJS MJS FC zero-bias EB capacitance BE built-in potential BE grading coefficient forward transit time TF bias dependence coefficient TF dependency on V BC TF dependence on I C excess phase at 1/(2πTF) zero-bias CB capacitance BC built-in potential BC grading coefficient fraction of C BC conn. to RB reverse transit time CS zero-bias capacitance CS built-in potential CS grading coefficient FB depletion capacitance coeff. 0 0.75 0.33 0 0 0 0 0 0.75 0.33 1 0 0 0.75 0 0.5 University of Connecticut 47 F V s V A deg F V s F V 2P 0.85 0.33 1N 30 2P 0.8 0.5 10N 2P 0.8 0.5