182 Int'l Conf. Pr. nd Dist. Proc. Tech. nd Appl. PDPTA'16 A Frmework for Scheduling Rel-Time Systems Zhuo Cheng, Hito Zhng, Ysuo Tn, nd Yuto Lim School of Informtion Science, Jpn Advnced Institute of Science nd Technology, Jpn {chengzhuo, ytn, ylim}@jist.c.jp School of Informtion Science nd Engineering, Lnzhou University, Chin htzhng@lzu.edu.cn Abstrct Rel-time system is plying n importnt role in our society. For such system, sensitivity to timing is the centrl feture of system behviors, which mens tsks in the systems re required to be completed before their dedlines. To gurntee this requirement, the design of scheduling is crucil. In this pper, bsed on stisfibility modulo theories (SMT), we provide frmework to design scheduling for rel-time systems. In the frmework, the problem of scheduling is treted s stisfibility problem. The key work is to formlize the stisfibility problem using first-order lnguge. After the formliztion, SMT solver (e.g., Z3, Yices) is employed to solver such stisfibility problem. An optiml schedule cn be generted bsed on solution model returned by the SMT solver. To demonstrte the prcticlity of the frmework, we give design guidelines for rel-time systems with multiprocessor. Through the demonstrtion, the frmework is found flexible nd sufficiently generl to pply to different kinds of rel-time systems. To the best of our knowledge, it is the first time tht systemticlly introducing SMT to solve series problems covering wide rnge in rel-time scheduling domin. Keywords rel-time scheduling, SMT, multiprocessor, stisfibility problem I. INTRODUCTION Rel-time system is plying n importnt role in our society. For exmple, chemicl nd nucler plnt control, spce missions, flight control, telecommunictions, nd multimedi systems re ll rel-time systems [1]. In such system, sensitivity to timing is the centrl feture of system behviors, which mens, tsks in the system re required to be completed before their dedlines. To provide such gurntee, the design of scheduling is crucil. The reserch on rel-time scheduling hs lsted for decdes, but still lots of chllenges remin [5]. For exmple, limited tsk models for multiprocessor systems, limited policies for ccess to shred resources, ineffective schedulbility tests, limited scheduling methods. In this pper, we try to ddress the chllenge limited scheduling methods. For designing scheduling method, mny reserch hs contributed to this re [8, 9, 10, 11]. But one importnt problem is tht ll the proposed methods re specified on either specific system rchitecture (e.g., uniprocessor) or specific scheduling trget (e.g., mke ll tsk meet dedline). Usully, it is quite difficult, even impossible, to dpt one scheduling method to nother ppliction scenrio. This becomes min obstcle for designing scheduling for new ppliction system nd results in high design cost. In this pper, we try to solve the problem Hito Zhng is the corresponding uthor. by proposing frmework to design scheduling for rel-time systems. The min contributions of this pper re s follows. i) We propose scheduling frmework bsed on stisfibility modulo theories (SMT). In this frmework, the problem of scheduling is treted s stisfibility problem. The key work is to formlize the stisfibility problem using first-order lnguge. We use st model to represent the formlized problem. This st model is set of first-order logic formuls (within liner rithmetic in the formuls) which express ll the scheduling constrints tht desired optimum schedule should stisfy. After the st model is constructed, SMT solver (e.g., Z3 [6], Yices [7]) is employed to solve the formlized problem. An optiml schedule cn be generted bsed on solution model returned by the SMT solver. The correctness of this method nd the optimlity of the generted schedule re strightforwrd. ii) The proposed scheduling frmework is flexible. In the SMT-bsed scheduling method, we define the scheduling constrints s system constrints nd trget constrints. It mens if we wnt to design scheduling to chieve other objectives, only the trget constrint needs to be modified. Or, if we wnt to chieve the sme scheduling objective for nother reltime system with different system rchitecture, only the system constrints need to be modified. iii) We give prcticl design guidelines for scheduling multiprocessor systems. These design guidelines re for systems with multiprocessor, nd of course, they re lso pplicble for system with uniprocessor, s scheduling uniprocessor systems is sub problem of scheduling multiprocessor systems. The model for the multiprocessor system is defined in very generl wy, nd in the design guidelines, we hve considered systems with mixed-criticlity (contining both firm nd soft) rel-time functions, tsk dependency reltion, tsk migrtion cost, heterogeneous processors (processors with different processing speed nd rchitectures), heterogeneous network chnnels (network chnnels with different dt trnsfer speed nd supporting different network protocols). All these efforts mke the frmework prcticble nd sufficiently generl to pply to different kinds of rel-time systems nd different scheduling trgets, which cn benefit system designers to efficiently design scheduling. The reminder of this pper is orgnized s follows. In Section II, we present scheduling frmework which is bsed on stisfibility modulo theories. The system model is denoted in Section III. We give the design guidelines for system constrints in Section IV, while Section V gives the design guidelines for trget constrints. Relted work re summrized in Section VI. Section VII concludes the pper.
Int'l Conf. Pr. nd Dist. Proc. Tech. nd Appl. PDPTA'16 183 Symbol TABLE I. Definition SYMBOLS AND DEFINITIONS t system time instnt δ network precision F set of functions of rel-time system FH F set of functions with firm dedlines FS F set of functions with soft dedlines F i F function of rel-time system, i is the index of the function r i triggered time instnt of function F i d i dedline of function F i v i obtined vlue by completing function F i before dedline T set of ll the tsks in the rel-time systems T i T set of tsks corresponding to function F i τ j T tsk, j is index of the tsk c j computtion cost of τ j m j migrtion cost of τ j from processor to nother one τs i strt tsk of tsk poset (T i, ) τe i end tsk of tsk poset (T i, ) P set of processors p P processor, where is the index of the processor ps speed of processor p TS T tsk set tht cn be completed by processor p TS b T tsk set tht cn migrte on network chnnel n b N P P set of network chnnels n b N network chnnel from processor p to p b ns b speed of n b II. THE SMT-BASED SCHEDULING FRAMEWORK A. Stisfibility Modulo Theories (SMT) Stisfibility modulo theories checks the stisfibility of logic formuls in first-order formultion with regrd to certin bckground theories like liner integer rithmetic or bit-vectors [2]. A first-order logic formul uses vribles s well s quntifiers, functionl nd predicte symbols, nd logic opertors [3]. A formul F is stisfible, if there is n interprettion tht mkes F true. For exmple, formul, b R, (b > +1.0) (b < +1.1), where R is rel number set, is stisfible, s there is n interprettion, 1.05,b 0, tht mkes F true. On the contrst, formul F is unstisfible, if there does not exist n interprettion tht mkes F true. For exmple, if we define, b Z, where Z is integer set, the formul (b >+1.0) (b <+1.1) will be unstisfible. For stisfibility problem tht hs been formlized by first-order logic formuls, SMT solver (e.g., Z3, Yices) cn be employed to solver such problem. If ll the logic formuls re stisfible, SMT solver returns the results st nd solution model which contins n interprettion for ll the vribles defined in the formuls tht mkes the formuls true. For the cse, b R, the model is: 1.05,b 0. If there is n unstisfible logic formul, SMT solver returns the results unst with n empty model, for the cse, b Z. B. The Scheduling Frmework The frmework of the SMT-bsed scheduling is illustrted in Fig. 1. In rel-time system, schedule (execution order of tsks) is generted by scheduler. The problem of scheduling cn be treted s stisfibility problem. In order to use SMT to solve this stisfibility problem, the key work is to formlize the problem using first-order Fig. 1. system Tsk schedule Scheduler Trget SAT Model System Trget Constrints /\ Constrints SMT Solver (e.g., Z3) The frmework for scheduling rel-time system bsed on SMT lnguge. We use st model to represent the formlized problem. This st model is the set of first-order logic formuls (within liner rithmetic in the formuls) which expresses ll the constrints tht the desired schedule should stisfy. There re two kinds of constrints: system constrints nd trget constrints. System constrints re bsed on the specific system. For exmple, if two tsks run on processor, schedule should mke sure tht the execution of these two tsks cnnot hve overlp in time domin. Trget constrint is bsed on the scheduling trget. For exmple, under norml worklod condition, the desired schedule should mke ll the functions meet their dedlines (completed before dedlines). After the st model is constructed, it cn be inputted into SMT solver (e.g., Z3). A solution model will be returned by the SMT solver. This solution model gives n interprettion for ll the vribles defined in the st model, nd under the interprettion, ll the logic formuls in the st model re evluted s true. It mens the stisfibility problem represented by the st model is solved, nd bsed on this interprettion, the desired schedule cn be generted. III. SYSTEM MODEL A. Function Set Function set define the functions tht cn be chieved by rel-time system. Let F = {F 1,F 2,...,F n } denote the function set. Ech function F i F is chieved by corresponding series tsks, represent s poset (T i, ), T i denotes the set of the corresponding tsk, nd denotes the dependency reltion of tsks in T i (the detil of the poset will be explined in the next subsection). For rel-time systems, when functions re triggered t system time instnt r, they re required to be completed before specific time, which is clled dedline, represented by d i. Moreover, different functions hve different degrees of importnce to the system, we use v i to denote the vlues obtined by the system through completing functions F i before its dedline d i. Bsed on bove explntion, we define the function F i =((T i, ),r i,d i,v i ). Note tht, unlike mny reserch on rel-time scheduling tht set dedlines to tsks, we set dedline to the function level rther thn tsk level. This setting cn better reflect the relity tht the dedline requirement is for the functions of rel-time systems, while function is chieved by series tsks cooperted together. This function definition denotes the functions which hve firm dedlines. Tht is, for such function, if it misses its
184 Int'l Conf. Pr. nd Dist. Proc. Tech. nd Appl. PDPTA'16 dedline, system will not obtin ny vlue through completing it. Usully, in complex rel-time system, not ll functions re firm rel-time functions. Some functions re soft reltime functions. For such function, if it misses dedline, it will still be useful for the system, but the vlue obtined by completing such function will be less thn completing it before its dedline. To denote the function with soft dedlines, without losing generlity, we define such functions s: F i = ((T i, ),r i,d i,f i (t)), where f i (t) is the coefficient function to indicte the vlue tht the system cn obtin by completing function F i t system time instnt t. The resonble vlue of the coefficient function is in intervl [0 1]. For convenience, we use FH F to denote the set of functions with firm dedlines, nd use FS F to denote the set of functions with soft dedlines. B. Tsk Poset A multiprocessor rel-time system comprises set of tsks, denoted by T. For ech function, it is chieve by series tsks cooperted together. Poset (T i, ) is used to denote such series tsks, where T i T is the tsk set corresponding to F i, nd T i = {τ 1,τ 2,...,τ m }, where τ j T i is tsk, nd m is the number of tsks. We use τ i,j to indicte tsk τ j T i.we ssume tht, if F > 1, then T i,t j T,i j = T i T j =. Tht is, no tsks re shred by different functions 1. The symbol indictes the dependency reltion between two tsks. Tht is, τ k,τ j T i,τ k τ j indicte tht tsk τ j cn strt to run only fter tsk τ k hs been completed. The dependency reltion is trnsitive. Tht is, τ k τ j,τ j τ l = τ k τ l. Definition (strt tsk). A strt tsk of (T i, ) is such tsk τ i T i tht strts erliest of ll the tsks in T i, tht is, τ j T i,i j = τ i τ j. Definition (end tsk). A end tsk of (T i, ) is such tsk τ i T i tht strts ltest of ll the tsks in T i, tht is, τ j T i,i j = τ j τ i. Without losing generlity, we ssume tht there is one strt tsk nd one end tsk of (T i, ), nd use τs i nd τe i to indicte the strt tsk nd end tsk of tsk poset (T i, ), respectively 2. Ech tsk hs two prmeters, τ j =(c j,m j ), where j is the index of the tsk. c j is the required computtion cost, which mens the number of time slots (ticks of processor) needed by unit speed processor to complete tsk τ j ; nd m j is the required migrtion cost for tsk τ j migrting from processor to nother one. We use the prmeter m j combined with prmeters of network (the detils will be explined lter) to clculted the overheds of migrting tsks. C. Processor Set In multiprocessor rel-time systems, different processors re used to execute tsks. We use P = {p 1,p 2,...,p l } to denote the set of processors, where l is the number of processors. Ech processor p is 2-tuple, p =(ps,ts ), where is the index of the processor. ps is the speed of the 1 Note tht, this ssumption is for concise expression. In rel systems, if tsk τ k T is used by function F i nd F j, we cn use two tsks τ ik nd τ jk, to represent τ k used in function F i nd F j, respectively. 2 To express function with mny strts (end) tsks, we cn set virtul tsk, with empty opertion, strt before ll the strts tsks (strt fter ll the end tsk) to be the strt (end) tsk. Fig. 2. () (b) (c) Different types of network topologies:. ring, b. mesh, c. tree processor. When tsk τ i running on processor p, the number of time slots needed for processor p to complete tsk τ i, represented by tsk completion tc i : tc i = c i ps (1) TS is the tsk set tht cn be completed by processor p. This prmeter is for heterogeneous systems, s in such systems, processors hve different rchitectures, some tsks cn only be executed on some specific processors. If TS =, it mens processor p cnnot be used to execute ny tsk in the system. Processors hve independent locl clocks, they re synchronized with ech other in the time domin through synchroniztion protocol. The mximum difference between the locl clocks of ny two processors in the networked systems is clled network precision (lso clled synchroniztion jitter) which is globl constnt. We denote the network precision with δ. D. Network Chnnel Set In multiprocessor rel-time systems, processors re connected through network chnnels. We use N P Pto denote the set of network chnnel. n n N denotes the network chnnel from processor p to p b, where p,p b P, b. Since we consider bi-directionl network chnnel, we hve n b N = n b N. We use ns b to represent the speed of n b. Note tht, define the network chnnel set s N P P mkes the system model become very generl which includes ny types of network topologies. For exmple, s shown in Fig. 2, the network chnnel set for mesh topology (b in the Fig. 2) equls to P P, while the ring nd tree topologies is the subset of P P. Moreover, this definition is lso suitble for processor with multi-cores. For exmple, for processor A with four cores, in this definition, cn be represented s four processors connect with network chnnels in mesh topology, nd the speed of networks is set bsed on the dt trnsfer speed inside the processor A. When the dt of the computed results of tsk τ i migrtes from processor p to p 3 b, the time slots spent on network chnnel, represented by tm i b, cn be clculted s: tm i b = m i (2) ns b Bsed on tm i b, we cn get the time instnt tht processor p b receives the dt of tsk τ i migrting from processor p 3 For conciseness, we sy tsk τ i migrtes from processor p to p b to men the dt of the computed results of tsk τ i migrtes from processor p to p b in the reset of the pper.
Int'l Conf. Pr. nd Dist. Proc. Tech. nd Appl. PDPTA'16 185 Fig. 3. T T P N An exmple for scheduling multiprocessor rel-time systems through network chnnel n b, represented by r i b,s r b i = s i b + tm i b + δ (3) where, s i b is the strt time of τ i migrting through network chnnel n b, nd δ is the network precision. For distributed rel-time system, different processors re connected through network chnnels which re built by routers. As different routers support different network protocols, some tsks my not be migrted through some network chnnels. To cpture this chrcteristics, similr s the heterogeneous processors, we lso cn define the heterogeneous network chnnels. We use TS b to denote tht tsk set tht cn be trnsferred through network chnnel n b. E. Assumptions Applied to this system model, we require tht ll the prmeters of the functions nd tsks re known prior. This requirement mkes the model become generliztion of the widely studied period tsk model, in which ll the tsks in the system re relesed periodiclly. This mens our method pplies more brodly thn other methods which re specified on period tsk model. To gurntee certin level of determincy, in this pper, tsk preemption is not llowed. To illustrte the defined system model, n exmple of scheduling for multiprocessor rel-time systems is shown in Fig. 3. In this exmple, there re three processors p 1,p 2,p 3 in the system. These processors re connected with ech other through six network chnnels n 1 2,n 2 1,n 1 3,n 3 1,n 2 3,n 3 2, nd these network chnnels support ll the migrtion of ll the tsks in T. The network precision δ is 1. In the system, firm rel-time function F =((T, ), 1, 11) is witing to be executed on the processors. The tsk poset of the function is (T, ) which consists of six tsks. Tsk dependency reltions re described in directed cyclic grph. An edge strting from tsk τ i to tsk τ j represented by dotted line denotes dependency reltion τ i τ j. IV. SYSTEM CONSTRAINTS This subsection describes ll the system constrints expressed in the st model for the defined multiprocessor systems. A. Constrint on strt execution time of functions Tsk set T i corresponding to function F i cn strt to run only fter the function is triggered. Tht is, the strt execution time of the strt tsk of the poset (T i, ) should be lrger thn the triggered time of function F i. F i F, p P s τs i r i (4) where symbol s τsi denotes the strt execution time of tsk τs i on processor p. B. Constrint on strt time of tsk migrtion If tsk τ i migrtes from processor p to processor p b through network chnnel n b, it mens i): tsk τ i hs been completed by processor p ;orii): τ i hs migrted to processor p from nother processor. For the first cse, tsk τ i cn strt to migrte fter it hs been completed, nd for the second cse, tsk τ i cn strt to migrte fter it hs lredy migrted to processor p. τ i T, n b N, n c N (s i b s i + tc i ) (s i b rc ) i where symbol s i b denotes the strt time of tsk τ i migrting through network chnnel n b, s i denotes the strt execution time of tsk τ i on processor p. C. Constrint on tsk dependency For processor p,ifτ i τ j, tsk τ j cn strt to run only fter τ i hs been completed. Similr to the constrints on strt time of tsk migrtion, there re two cses. i): tsk τ i hs been completed by processor p ; ii): tsk τ i hs migrted to processor p from nother processor. For the first cse, τ j cn strt to run fter τ i hs been completed, nd for the second cse, τ j cn strt to run fter τ i hs lredy migrted to processor p. τ i,τ j T, p P, n b N τ i τ j = (s j s i + tc i ) (s j rb ) i D. Constrint on execution of processors A processor cn execute only one tsk t time. This is interpreted s: there is no overlp of the execution time of ny two tsks. τ i,τ j T,i j, p P (s i s j + tc j ) (s j s i + tc i ) E. Constrint on network chnnels A network chnnel cn trnsfer dt of only one tsk t time. Tht is, there is no overlp of the migrtion time of ny two tsks on network chnnel. τ i,τ j T,i j, n b N (s i b s j b + tmj b ) (sj b si b + tm i b) (5) (6) (7) (8)
186 Int'l Conf. Pr. nd Dist. Proc. Tech. nd Appl. PDPTA'16 Fig. 4. The scheduling result for exmple shown in Fig. 3 by using the proposed SMT-bsed scheduling F. Constrint on heterogeneous processors In heterogeneous systems, processors hve different rchitectures, some tsks cn only be executed on some specific processors. For tsks tht cnnot be executed on some processors, the strt execution time of the tsks in such processors re set to +, which mens the tsks will never strt to run on these specific processors. p P, τ i T TS s i (9) =+ G. Constrint on heterogeneous network chnnels For distributed rel-time system, different processors re connected through network chnnels which re built by routers. As different routers support different network protocols, some tsks my not be migrted through some network chnnels. Similr s the constrint on heterogeneous processors, for tsks tht cnnot migrte on some network chnnels, the strt migrtion time of the tsks in such network chnnels re set to +, which mens the tsks will never strt to migrte on these specific network chnnels. n b N, τ i T TS b s i (10) b =+ V. TARGET CONSTRAINTS There re mny trgets cn be considered when we design scheduling for rel-time systems. Which objectives re pproprite in given sitution depends, of course, upon the ppliction. In this section, we give design guidelines for different scheduling trgets. A. Mking ll the functions meet their dedlines Under norml worklod conditions, the desired schedule should mke sure tht every triggered function cn be completed before its dedline. F i F, p P s τe i + tc τe i d i (11) where symbol s τei is the strt execution time of tsk τe i on processor p, nd tc τei is the number of time slots needed for processor p to complete tsk τe i. Bsed on this scheduling trget, recll the exmple shown in Fig. 3, we cn get the solution model M which defines the vlues of the strt time of tsk execution on processor, s j, nd the strt time of tsk migrtion through network, s j b c, for f i F, τ j T i, p P, n b c N. Bsed on the model M, we cn get the scheduling results s shown in Fig. 4. This scheduling sequence cn mke the function F in Fig. 3 meet its dedline. Some chrcteristics of this scheduling sequence should be noticed: Tsk τ 1 hs been executed on processor p 1 from system time t = 1 to t = 3, nd it hs lso been executed on processor p 3 from system time t = 2 to t = 3. This mens, the SMT-bsed scheduling frmework cn hndle the prllel execution of tsks, nd cn mke tsk repetedly run on different processors when such repeted execution is necessry. Tsk τ 2 runs on processor p 2 from t = 6 to t = 7. Although tsk τ 2 needs the computed results from completing tsk τ 1, such computed results cn not only be obtined by completing tsk τ 1 on processor p 2 itself, but lso cn be obtined by trnsferring the computed results from other processor tht hs completed tsk τ 1. Specified to this exmple, t system time t =6, processor p 2 gets the computed results of tsk τ 1 from processor p 1. B. Mximizing obtined vlues of completed functions Under norml worklod conditions, there exist schedule cn mke ll the triggered functions meet their dedlines. However, in prcticl environment, system worklod my vry widely becuse of dynmic chnges of work environment. Once system worklod becomes too hevy so tht there does not exist fesible schedule cn mke ll the functions meet their dedlines, we sy the system is overloded. When system is overlod, one resonble scheduling trget is to mximize the obtined vlues of the completed functions. Let symbol v be the obtined vlues of the completed functions, nd its initil vlue is set to be 0. For functions with firm dedlines, system cn obtin their vlues only when such functions hve been completed before their dedlines. F i FH if p P,s τei v := v + v i end d i (12) For completing functions F i with soft dedlines, the vlue tht the system cn obtin is ccording to the coefficient functions f i (t), where t is the time when the system completes the function, nd it cn be clculted s follows. F i FS if p P,s τei end v := v + f i (s τei d i ) (13) Let symbol sv denote the mximum obtined vlues of the completed functions, nd obviously, sv is no less thn 0 nd no lrger thn the sum of the vlues of the firm dedline functions ( v i for F i FH) nd the vlues of the soft dedline functions when ll the soft dedline tsks re completed before dedlines ( f i (t i ), for F i FS, where t i is the completed
Int'l Conf. Pr. nd Dist. Proc. Tech. nd Appl. PDPTA'16 187 time instnt of tsk τ i, nd t i <d i ), represented s mx. The constrints on the scheduling trget cn be expressed s: v = sv (14) C. Mking firm dedline functions meet dedlines while mximizing obtined vlues of the completed soft dedline functions Since firm dedline functions usully ply importnt roles in rel-time system, when system is under overlod condition, resonble scheduling trget is to first mke sure tht ll the firm dedline functions meet their dedlines, menwhile, mximizing obtined vlues of the completed soft dedline functions. To mke firm dedline functions meet dedlines, we cn get F i FH, p P s τei d i (15) To mximize the obtined vlue of the completed soft dedline functions, the formul is similr s it for the previous scheduling trget. Let symbol v be the obtined vlues of the completed functions, nd its initil vlue is set to be 0. The vlues system cn obtin by completing the soft dedline functions cn be clculted s follows. F i FS if p P,s τei end v := v + f i (s τei d i ) (16) Let symbol sv denote the mximum obtined vlues of the completed soft dedline functions, nd obviously, sv is no less thn 0 nd no lrger thn the vlues of the soft dedline functions when ll the soft dedline tsks re completed before dedlines ( f i (t i ), for F i FS, where t i is the completed time instnt of tsk τ i, nd t i < d i ). The constrints on scheduling trget cn be expressed s: v = sv (17) VI. RELATED WORK The reserch on rel-time scheduling hs lsted for decdes, mny reserch hve been conducted on this re. For reserch on designing scheduling for multiprocessor systems, comprehensive survey cn be found in [5]. In [8], the Proportionte Fir (Pfir) lgorithm ws introduced. Pfir is schedule genertion lgorithm which is pplicble to periodic tsksets with implicit dedlines. It is bsed on the ide of fluid scheduling, where ech tsk mkes progress proportionte to its utiliztion. Pfir scheduling divides the timeline into equl length qunt or slots. Authors in [8] showed tht the Pfir lgorithm is optiml for periodic tsksets with implicit dedlines. In [9], uthors extended the PFir pproch to spordic tsksets, showing tht the EPDF (erliest pseudodedline first) lgorithm, vrint of Pfir, is optiml for spordic tsksets with implicit dedlines executing on two processors, but is not optiml for more thn two processors. Some pproches focus on studying tsk nd messges schedule co-synthesis in switched time-triggered networks. In [10], uthors studied time-triggered distributed systems where periodic ppliction tsks re mpped onto different end sttions (processing units) communicting over switched Ethernet network. They try to solve the scheduling problem using MIP multi-objective optimiztion formultion. In [11], uthors studied the system consisting of communicting eventnd time-triggered tsks running on distributed nodes. These tsks re scheduled in conjunction with the ssocited bus messges by using dynmic nd sttic scheduling methods, respectively. Hitherto, most of the presented methods re either limited to specific tsk model (e.g., [8, 10] limited to periodic tsksets) or simple system rchitecture (e.g., [9] limited to two processors, [11] simple bus network topologies). Compred with these works, our proposed frmework is flexible nd sufficiently generl to pply to vrious kinds of rel-time systems nd vrious scheduling trgets, which mkes tht our frmework pplies much more widely. VII. CONCLUSION In this pper, bsed on stisfibility modulo theories (SMT), we provide frmework to design scheduling for reltime systems. In the frmework, the problem of scheduling is treted s stisfibility problem. After using first-order lnguge to formlize the stisfibility problem, SMT solver is employed to solver such problem. An optiml schedule cn be generted bsed on solution model returned by the SMT solver. To demonstrte the prcticlity of the frmework, we give design guidelines for rel-time systems with multiprocessor. Through the demonstrtion, the frmework is found flexible nd sufficiently generl to pply to different kinds of rel-time systems. By giving the prcticl design guidelines, we believe tht our frmework cn benefit system designers to efficiently design scheduling. REFERENCES [1] F. Zhng nd A. Burns, Schedulbility nlysis for rel-time systems with EDF scheduling, IEEE Trns. Comput., vol. 58, no. 9, pp. 1250 1258, Apr. 2009. [2] C. Brrett, et l., Stisfibility modulo theories, Hndbook of Stisfibility, vol. 185. IOS Press, 2009. [3] L.d. Mour nd N. Bjorner, Stisfibility Modulo Theories: An Appetizer, Forml Methods: Foundtions nd Applictions, vol. 5902, pp. 23 26, 2009. [4] S.S. Crciuns nd R.S. Oliver, SMT-bsed Tsk- nd Network-level Sttic Schedule Genertion for Time-Triggered Networked Systems, Proc. 22th Int. Conf. on Rel-Time Networks nd Systems, NY, USA, pp. 45 54, October, 2014. [5] R.I. Dvis nd A. Burns, A survey of hrd rel-time scheduling for multiprocessor systems, ACM Comput. Surv., vol. 43, no. 5, pp. 35:1 35:44, Oct. 2011. [6] L. Mour nd N. Bjrner, Z3: n efficient SMT solver, Proc. 14th Int. Conf. on Tools nd Algorithms for the Construction nd Anl. of Syst., Budpest, Hungry, LNCS 4963, pp. 337 340, Springer-Verlg, 2008. [7] B. Dutertre, Yices 2.2, Proc. 26th Int. Conf. on Comput. Aided Verifiction, Vienn, Austri, LNCS 8559, pp. 737 744, Springer Interntionl Publishing, 2014. [8] S.K. Bruh, et l., A notion of firness in resource lloction, Algorithmic, vol. 15, no. 6, pp. 600 625, 1996. [9] J. Anderson nd A. Srinivsn, Erly-relese fir scheduling, Proc. of the Euromicro Conference on Rel-Time Systems, 2000. [10] L. Zhng, et l., Tsk- nd network-level schedule co-synthesis of Ethernet-bsed time-triggered systems, Proc. of ASP-DAC, 2014. [11] T. Pop, P. Eles, nd Z. Peng, Holistic scheduling nd nlysis of mixed time/event-triggered distributed embedded systems, Proc. of CODES, 2002.